Abstract: Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modem high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.

Abstract: Methods are disclosed for manufacturing silicon stencil masks for use in charged-particle-beam microlithography. According to the method, a boron-doped layer is formed on a silicon substrate, a mask pattern is formed on the boron doped layer, and the boron-doped layer is etched according to the mask pattern to form voids in the boron-doped layer. The voids do not extend completely through the thickness of the boron-doped layer. In subsequent steps, a silicon nitride layer is applied and etched to form openings in which the silicon substrate is etched away to form struts. Because the boron-doped layer is not completely etched through in the earlier etching step, the mask is much more resistant to fracture in a subsequent cleaning step. In a final step after cleaning, the boron-doped layer is etched to extend the voids completely through the thickness of the boron-doped layer.

Abstract: A method for etching a semiconductor device (10) having BARC layer (22) and nitride layer (20) includes etching BARC layer (22) until reaching a first set point in the fabrication reaction chamber and then etching nitride layer (20) in-situ the fabrication reaction chamber immediately following etching BARC layer (22).

Abstract: Method of preferentially-ordering a thermally sensitive element (50) may comprise the step of forming a first thin film layer of electrically conductive material (75). A thin film layer of thermally sensitive material (80) may be formed on a surface of the first layer of electrically conductive material (75). A second thin film layer of electrically conductive material (85) of lanthanum strontium cobalt oxide (LSCO) may be formed on a surface of the layer of thermally sensitive material (80) opposite the first thin film layer (75). A nucleation layer (87) may be formed in communication with the surface of the layer of thermally sensitive material (80) opposite the first thin film layer (75). The layer of thermally sensitive material (80) may be crystallized beginning at the surface of the thermally sensitive layer (80) in communication with nucleation layer (87). The nucleation layer (87) may be removed.

Abstract: A method is disclosed for forming alignment marks at the outer perimeter of wafers where they are not susceptible to much damage during chemical-mechanical polishing (CMP) process. Complete protection is provided by recessing the alignment mark into the substrate by etching. Recess etching is accomplished at the same time the isolation trenches are formed to delineate device areas. Thus, alignment marks are provided with a protective recess without extra steps. Furthermore, by forming alignment marks at the outer perimeter of the wafer, productivity is improved by providing maximum usage of wafer area for integrated circuits.

Abstract: A etchant recipe including a mixed gas of one of a CH.sub.x F.sub.y group and CO gas is used to etch a silicon nitride layer by plasma etching so as to form a thin polymer layer to protect a silicon layer under the silicon nitride layer from over-etching. Then a soft etching is performed to remove the thin polymer. The etchant recipe is, for example, used in forming a contact opening on a gate of a MOS transistor, on which a silicon nitride layer is formed.

Abstract: An improved etching procedure that uses three processing steps to vastly improve HAR opening profile and improved under-layer selectivity. A new three sequence etching process is provided during which a new three-gas plasma etch is to be used. This new etching sequence is preceded by a new main etch that uses three gasses and followed by a new over-etch procedure that uses the same three gasses and etching conditions as the new main etch.

Abstract: An open loop control method for use with an apparatus for growing a silicon single crystal having a zero dislocation state and an improved diameter and growth rate uniformity in accordance with the Czochralski process. According to the invention, a heat and mass transfer model based on the silicon charged to a crucible is determined as a function of one or more reference parameters. The reference parameter values are determined from the growth of a reference silicon single crystal. A power profile is then determined as a function of the heat and mass transfer model for a given pull rate profile and model diameter profile. The power profile generated is representative of the power supplied to a heater for providing an amount of thermal energy to the crucible for substantially maintaining a thermal equilibrium at the interface between the melt and the crystal.

Abstract: A channel layer is formed in a surface of a semiconductor substrate, and a plurality of trenches are formed in the surface of the semiconductor substrate, the trenches being deeper than the channel layer. Then, gate electrodes are formed in the trenches, respectively, after which body layers are formed between the trenches and source layers are formed adjacent to the trenches.

Abstract: This invention relates to a process for rinsing a substrate which has been provided with a desired resist pattern and subjected to an etching treatment, and optionally, subsequent ashing treatment, said process including the steps of: (I) treating said resist pattern with a remover solution which contains, as a principal ingredient, a salt of hydrofluoric acid and a metallic-ion-free base; (II) rinsing said substrate with a rinse solution for lithography which contains ethylene glycol and/or propylene glycol, and a water-soluble organic solvent other than said glycol; and (III) washing said substrate with water.

Abstract: A shallow trench isolation structure is formed by providing a polish stop layer with an opening aligned with edges of a trench formed in the substrate. The etch stop layer might have a surface composition of SiO.sub.x N.sub.y and a composition of SiN or Si.sub.3 N.sub.4 at a lower surface within the polish stop layer. The composition of the silicon oxynitride surface of the polish stop layer is most preferably chosen so that the material has a refractive index on the order of n.about.1.8 to 2.0. The trench is overfilled with silicon oxide so that a layer of silicon oxide extends over the surface of the etch stop layer. Chemical mechanical polishing is then performed to remove the excess silicon oxide from the surface of the etch stop layer and to define an oxide plug within the trench.

Abstract: Particles counts and concentrations are reduced from the backside of a substrate, such as a semiconductor wafer or flat panel display with the invention, to improve precision and uniformity in subsequent operations, including lithography operations. A semiconductor substrate is placed on a chuck (10) in a track system (30), such as a resist coater, a developer, or other form of spin coater. The substrate is processed accordingly to conventional practice and the substrate is removed. The chuck is then cleaned by dispensing a solvent, for example using EGMEA or PGMEA, through a dispense nozzle (38) of the system. Alternatively, or additionally, a brush (36) or sponge which is at least partially saturated with a solvent (39) is moved across the chuck to remove particles. The chuck cleaning can occur between every wafer, every wafer lot, or less periodically, such as between shifts, as the chuck particle accumulation dictates.

Abstract: Silicon nitride is etched employing a composition containing a fluoride containing compound, certain organic solvents, and water.

Abstract: A microetching composition for copper or copper alloys comprising, (a) an oxidizing agent which can oxidize the copper or copper alloy, (b) a polymer compound which contains polyamine chains or a cationic group or both in the amount of 0.000001 to 1.0% by weight, and (c) water. The composition can produce surfaces of copper or copper alloy exhibiting excellent adhesion to resins such as prepregs and resists, and superior solderability. The composition can be adaptable to the manufacture of printed wiring boards with highly integrated fine line patterns.

Abstract: A substrate processing chamber, particularly a chemical vapor deposition (CVD) chamber used both for thermal deposition of a conductive material and a subsequently performed plasma process. The invention reduces thermal deposition of the conductive material in a pumping channel exhausting the chamber. The pumping channel is lined with various elements, some of which are electrically floating and which are designed so that conductive material deposited on these elements do not deleteriously affect a plasma generated for processing the wafer.

Abstract: Methods for determining an endpoint for a plasma etching process. The plasma etching process is employed to etch a substrate in a plasma processing chamber. The method includes detecting, using a mass analyzer, a density of a predefined compound in the plasma processing chamber. The method further includes outputting from the mass analyzer a variable signal responsive to the detecting. There is also included producing, responsive to the variable signal, a control signal. The control signal is outputted when a predefined density criteria is detected in the variable signal. Additionally, there is included initiating an etch termination procedure, responsive to the control signal, thereby ending the plasma etching process at an end of the etch termination procedure.

Abstract: A gate is formed on a semiconductor substrate by using a bottom anti-reflective coating (BARC) to better control the critical dimension (CD) of the gate as defined via a deep-UV resist mask formed thereon. The wafer stack includes a gate oxide layer over a semiconductor substrate, a polysilicon gate layer over the gate oxide layer, a SiON BARC over the conductive layer, a thin oxide film over the SiON BARC. The resist mask is formed on the oxide film. The SiON BARC improves the resist mask formation process. The wafer stack is then shaped to form one or more polysilicon gates by sequentially etching through selected portions of the oxide film, the BARC, and the gate conductive layer as defined by the etch windows in the resist mask. Once properly shaped, the remaining portions of the resist mask, oxide film and SiON BARC are removed.

Abstract: A process is described for etching contact holes though a dielectric layer down to a silicon surface. Initial etching, until the silicon is exposed, is performed in a suitable plasma environment under high RF power. This results in damage to the newly exposed silicon surface. Said damage is repaired by exposing the silicon and the photoresist to an atmosphere that includes carbon tetrafluoride and atomic oxygen. The latter oxidizes the damaged layer, allowing it to be removed by the former. Much of the photoresist is also removed by the atomic oxygen, any that still remains being then removed using a wet etch. At the user's option, the silicon may be allowed to overetch during the high RF power application and/or a low power RF step may be introduced to partially remove silicon surface damage prior to the atomic oxygen treatment.

Abstract: Method and apparatus are disclosed for growing diamond films on a non-diamond substrate, such as a silicon wafer. The substrate surface is subjected to nucleation by means of a microwave-generated plasma while applying an electrical bias to the substrate and while an electrode is positioned adjacent to but spaced from the substrate surface. After the nucleation step, crystalline diamond is deposited on the nucleated surface from a carbon-containing plasma.

Abstract: A plasma treatment method used to form improved PECVD silicon nitride film passivation layers over metal interconnections on ULSI circuits is achieved. The process is carried out in a single PECVD reactor. After depositing a thin silicon oxide stress-release layer over the metal lines, a plasma-enhanced CVD silicon nitride layer is deposited, and subsequently a plasma treatment step is carried out on the silicon nitride layer. The use of a sufficiently thin silicon nitride layer eliminates photoresist trapping at the next photoresist process step that would otherwise be trapped in the voids (keyholes) that typically form in the silicon nitride passivation layer between the closely spaced metal lines, and can cause corrosion of the metal. The plasma treatment in He, Ar, or a mixture of the two, is then used to densify the silicon nitride layer and to substantially reduce pinholes that would otherwise cause interlevel metal shorts.