Abstract: It is possible to obtain a semiconductor device in which a contact and a wiring provided on the contact can be electrically connected well even if a shift of superposition is caused. Sidewalls 5a, 5b, 5c and 5d formed of a conductive material directly making contact with side faces of wirings 4a and 4b to be provided on contacts 3a and 3b. Consequently, the wirings 4a and 4b and the contacts 3a and 3b can be electrically connected well through the sidewalls 5a, 5b, 5c and 5d.

Abstract: A method for fabricating a triode field emitter array using carbon nanotubes having excellent electron emission characteristics is provided. In the method for fabricating a triode-structure carbon nanotube field emitter array, a catalyst layer is formed on a cathode electrode without forming a base layer, and carbon nanotubes are grown on the catalyst layer using a Spind't process. In this method, a non-reactive layer is formed on a catalyst layer outside the micro-cavity such that the carbon nanotubes can be grown only on the catalyst within the micro-cavity. Accordingly, even through a separation layer is etched and removed, since carbon nanotubes do not exist outside the micro-cavity, it does not happen that carbon nanotubes are drifted into the micro-cavities. Therefore, the fabrication yield is increased, and the fabrication cost is decreased.

Abstract: A method for forming a semiconductor device is disclosed. A semiconductor film comprising silicon is formed on a substrate. The semiconductor film is crystallized. The crystallized semiconductor film is patterned into a marker part for aligning a mask and an insular semiconductor part at the same time. A part of the semiconductor film to become a channel formation region is thinned to a thickness 300 Å or less.

Abstract: A method for manufacturing read-only memory. In each memory cell on a wafer, a gate electrode 3a is formed on a silicon substrate 1 with an intermediary of a gate oxide film 2, and an oxide film 4 is formed to cover the surface of the silicon substrate. After an inter-layer dielectric film 6 is grown on the oxide film 4 by LPCVD, this inter-layer dielectric film 6 is put to rapid thermal processing at 700° C. to 800° C. for about 60 seconds to remove the water content of the inter-layer dielectric film 6. This eliminates chances of insulation deterioration when semi-finished wafers are put into long-term storage. After the steps just before data writing have been finished, the wafers can be put into long-term storage, so that time from decision of data to write until product completion can be reduced.

Abstract: In order to form a self-aligned damascene gate which enables the resistance of the gate to be reduced, a thick layer of dielectric material is formed over a semiconductor substrate in which drain and source regions have previously been implanted and annealed. The dielectric layer is polished for planarity using a chemical-mechanical-polishing (CMP) technique or the like. A gate mask is then used to pattern the dielectric, the interlayer dielectric (ILD) is etched, and the resist is stripped. A gate dielectric is deposited in the form of a CVD nitride, oxynitride, or stacked nitride oxide ONO, or the like. Polysilicon is then deposited over the dielectric, doped by implantation, and annealed. A silicon rich silicide layer is then deposited after which CMP or the like is used to remove the superfluous portions of the silicide, doped polysilicon and gate oxide layers down to the dielectric level.

Abstract: A method of manufacturing a dynamic random access memory cell. A substrate having a transistor therein is provided. A first dielectric layer is formed over the substrate and the transistor. A bit line having a cap layer thereon is formed over the first dielectric layer. A protective layer is formed over the substrate covering the bit line. A second dielectric layer is formed over the protective layer. The second dielectric layer is etched in a self-aligned process. The etching continues penetrating the protective layer and the first dielectric layer until the substrate is exposed so that a node contact opening and an opening for forming the lower electrode of a capacitor are formed at the same time. Thereafter, polysilicon material is deposited into the node contact opening and the lower electrode opening to form a polysilicon layer. The upper surface of the polysilicon layer is slightly below the lower electrode opening.

Abstract: Silicon substrate isolation by epitaxial growth of silicon through windows in a mask made of silicon nitride (202) on silicon oxide (201) with the silicon oxide etched to undercut the silicon nitride; the mask is on a silicon substrate.

Abstract: A method for forming a semiconductor device is provided. The method includes providing a substrate having a gate formed thereon. A first doped region is formed in the substrate. The first doped region extends a first distance from the gate. A second doped region is formed in the substrate. The second doped region extends a second distance from the gate. The first distance is less than the second distance. A semiconductor device includes a substrate, isolation structures defined in the substrate, and a gate disposed on the substrate between adjacent isolation structures. A first doped region is defined in the substrate proximate the gate. The first doped region extends a first distance from the gate. A second doped region is defined in the substrate proximate the gate. The second doped region extends a second distance from the gate. The first distance is less than the first distance.

Abstract: An air gap semiconductor structure and corresponding method of manufacture. The method includes providing a substrate having metallic lines thereon. A high molecular weight sacrificial film is formed over the substrate. A portion of the high molecular weight sacrificial layer is removed to form spacers. A dielectric layer is formed over the substrate, the top surface of the metallic lines and the spacers. Finally, a thermal dissociation operation is conducted to remove the spacers, thereby forming an air pocket on each sidewall of the metallic lines.

Abstract: A memory cell has a vertical MOS transistor which contains a first electrically insulated gate electrode and a second gate electrode. The second gate electrode is partially disposed in a trench whose sidewall is adjoined by the MOS transistor. The first gate electrode is disposed outside the trench and has a tip at an edge of the trench. The tip enables programming with a reduced current flow. The memory cell can be fabricated by self-aligning fabrication with an area requirement of six F2.

Abstract: A method for manufacturing a salicide transistor, a semiconductor storage, and a semiconductor device that can solve both an increase in narrow-line resistance and an increase in P-N-junction leakage, and can give an optimized process as the total LSI device manufacturing process flow. After adding an impurity in the high-concentration source/drain region on a semiconductor substrate, a heat treatment is performed at a first temperature, then a heat treatment is performed for forming salicide at a second temperature higher than a predetermined temperature and lower than the first temperature for a first period of time, an interlayer insulating film is formed, and heat treatment is performed at a third temperature higher than the second temperature and lower than the first temperature. Since the crystallinity of the implanted layer 109 has been recovered before forming the silicide protecting film, salicide can be formed under the conditions where the crystallinity of the diffusion layer is good.

Abstract: A method for forming high voltage devices compatible with low voltage devices on a semiconductor substrate is provided. A substrate is provided. An oxide layer is formed on the substrate. An N well is formed in the substrate. A P well is formed opposite to the N well in the substrate. A plurality of N-field regions are formed as drift regions in the P well and as isolation regions in the N well. A plurality of P-field regions are formed as drift regions in the N well and as isolation regions in the P well region. A plurality of field oxide regions are formed on the N well and the P well in the substrate. N− type doped regions are formed in the P well through an N-grade implantation, prior to a gate oxide layer and a polysilicon layer formation. An N+ type doped region in the N−type doped region is formed as a source/drain region for an NMOS transistor in the P well. A P+ type doped region is formed as a source/drain region for a PMOS transistor in the N well.

Abstract: A method for forming self-aligned contact (SAC) is disclosed to improve device reliability. The method includes forming a dielectric liner over the contact opening before the contact plug is filled in. Optional contact implantation before and after the liner formation can be added to enhance the doping profile of the device.

Abstract: A method for fabricating a type of Trench Mask ROM cell comprises steps including: providing a substrate doped lightly with p-type dopant, sequentially forming a pad oxide layer and a nitride layer on the substrate; etching back the pad oxide layer, the nitride layer and the substrate to form plural trenches; a gate oxide layer being formed on surfaces of each trench; then, implanting n+-type ions into the substrate beneath the pad oxide layer and between each two adjacent trenches; and, forming a polysilicon layer on the gate oxide and pad oxide; finally, implanting n+-type ions into the substrate beneath the gate oxide layer on bottoms of selected trenches. And, it is appreciated that the sequence of the formation of plural trenches and implanting n+-type ions into substrate between each trench can be reversed in the embodiment without affecting subsequent steps.

Abstract: Presented is a process for manufacturing virtual ground electronic memory devices integrated in a semiconductor having a conductivity of a first type and having at least one matrix of floating gate memory cells. In the matrix there are a number of continuous bit lines extending across the substrate as discrete parallel strips, and a number of word lines extending in a transverse direction to the bit lines. The method begins by forming gate regions of the memory cells to produce a number of continuous strips seperated by parallel openings. Then, a dopant is implanted to form, within the parallel openings, the bit lines with conductivity of a second type. Spacers are formed on sidewalls of the gate regions. Then a first layer of a transition metal is deposited into said parallel openings, and the transition metal layer is subjected to a thermal treatment for reacting it with semiconductor substract and forming a silicide layer over the bit lines.

Abstract: Within a method for etching a trench within a silicon oxide layer there is first provided a substrate. There is then formed over the substrate a silicon oxide layer. There is then formed over the silicon oxide layer a masking layer. There is then etched, while employing a plasma etch method in conjunction with the masking layer as an etch mask layer, the silicon oxide layer to form an etched silicon oxide layer defining a trench. Within the method, the plasma etch method employs an etchant gas composition comprising: (1) octafluorocyclobutane; and (2) at least one of carbon tetrafluoride, difluoromethane, hexafluoroethane and oxygen; but excluding (3) a carbon and oxygen containing gas.

Abstract: A method of fabricating a gate stack having an endpoint detect layer and a multi-step etch process to prevent damage to a gate dielectric layer. The special endpoint detect layer emits an endpoint signal that allows the etch chemistry to be changed to a more selective polysilicon to oxide ratio to prevent damage to the gate oxide layer. The invention begins by forming a gate dielectric layer over a substrate. We then form an endpoint detect layer over the gate dielectric layer. A gate stack is formed over the bottom silicon layer. Then a mask is formed over the gate stack. The mask defines a gate electrode. We etch the gate stack and the endpoint detect layer using a multi-step etch comprising at least 3 steps. In a main etch step, the gate stack and the endpoint detect layer are etched using a first etch chemistry. Upon an endpoint detection signal generated by etching the gate stack, the first etch step is stopped.

Abstract: A method comprises the steps of forming a damaged layer on a silicon substrate by subjecting the silicon substrate to a plasma treatment, forming a silicon oxide layer by exposing the surface of the damaged layer to an oxygen plasma to oxidize the surface of the silicon substrate including the damaged layer and selectively eliminating the silicon oxide layer under a condition of a high selective ratio to the silicon, in which the film thickness of the silicon oxide layer is controlled by controlling an ion energy of the oxygen plasma and exposure time of the surface of the damaged layer to the oxygen plasma in accordance with the film thickness of the damaged layer.

Abstract: Field oxide is formed using high pressure. Oxidation of field regions between active regions is accomplished in a two-step process. A first oxide layer is formed in the field region. Then, a second oxide layer is formed on the first oxide layer. The second oxide layer is formed at a pressure of at least approximately 5 atmospheres. In one embodiment, the first oxide layer is formed at atmospheric pressure using a conventional oxidation technique, such as rapid thermal oxidation (RTO), wet oxidation, or dry oxidation. In another embodiment, the first oxide layer is formed, at a pressure of approximately 1 to 5 atmospheres. Wet or dry oxidation is used for the oxidizing ambient. The first oxide layer is formed to a thickness of approximately 500 angstroms or less, and typically greater than 200 angstroms. Temperatures of approximately 600 to 1,100 degrees Celsius are used for the oxidation steps.

Abstract: A low-temperature process for forming a highly conformal barrier film during integrated circuit manufacture by low pressure chemical vapor deposition (LPCVD). The process includes the following steps. First, the process provides ammonia and a silicon-containing gas selected from the group consisting of silane, dichlorosilane, bistertiarybutylaminosilanc, hexachlorodisilane, and mixtures of those compositions. The ratio of the volume of ammonia to the volume of the silicon-containing gas is adjusted to yield silicon concentrations greater than 43 atomic percent in the resultant film. The process applies a deposition temperature of 550° C. to 720° C. The ammonia and the silicon-containing gas are reacted at the deposition temperature to form a silicon-rich nitride film less than 200 Å thick. Finally, the silicon nitride film is deposited by low pressure chemical vapor deposition.