Abstract: A method for forming a top gate polysilicon type thin film transistor is disclosed. Prior to ion implantation, a gate insulating layer except for a gate region is removed to lower an energy level for ion implantation. When two impurity types of a transistor are made on the same substrate, low energy ions are implanted to diminish a photoresist burning problem. Therefore, it is possible to improve conductivity of polysilicon and alleviate damage to the polysilicon.

Abstract: A method for producing a storage cell includes forming a polycrystalline silicon layer on a semiconductor body having at least one selection transistor disposed in a first plane. An interspace is formed between two adjacent structures of the layer and one of the adjacent structures of the layer is placed on a surface of a first silicon plug. A cell plate electrode is formed in the interspace and a trench is formed in the layer. The trench reaches as far as the first plug surface and is filled with an insulating layer. The-layer is removed. A storage capacitor having a high-epsilon or ferroelectric dielectric and a storage node electrode is formed. The capacitor is disposed in a second plane in and above the body. The insulating layer is replaced with silicon to form a second silicon plug directly connected to the first plug. The second plug is electrically connected to the storage node electrode, and the first plane is electrically connected to the second plane through the first and second plugs.

Abstract: A gate structure for an ONO flash memory device includes a first layer of silicon oxide on top of a semiconductor substrate, a second layer of silicon oxide, a layer of silicon nitride sandwiched between the two silicon oxide layers, and a control gate on top of the second layer of silicon oxide. Nitrogen is implanted into the first layer of silicon oxide and then the semiconductor structure is heated using a rapid thermal tool to anneal out the implant damage and to diffuse the implanted nitrogen to the substrate and silicon oxide interface to cause SiN bonds to be formed at that interface. The SiN bonds are desirable because they improve the bonding strength at the interface and the nitrogen remaining in the silicon oxide layer increases the oxide bulk reliability.

Abstract: The present invention relates to a method of forming a self-aligned silicide (salicide) by siliciding a gate area prior to siliciding a source and drain area and/or spacer formation. The method improves transistor speed by lowering the leakage current in the source and drain areas and lowering the polysilicon sheet resistance of the gate. As a result of one embodiment of the present method, a silicide is formed over the gate area that is advantageously thicker than silicide formations over the source and drain areas.

Abstract: A process for manufacturing a silicon-on-insulator wafer from a silicon wafer assembly. The assembly is made of two wafers. One of the wafers contains a fragile layer. The fragile layer is a layer containing a high amount of hydrogen. An amount of energy from an energy source is applied to the assembly to separate the assembly along the fragile layer thus forming a silicon-on-insulator wafer and a leftover wafer. The energy source is selected from the group consisting of: ultrasound, infrared, hydrostatic pressure, hydrodynamic pressure, or mechanical energy. The amount of energy is chosen to be sufficient to transform the fragile layer into a quasi-continuous gaseous layer. Under separation the hydrogen-enriched layer transforms into layer consisting of hydrogen platelets and hydrogen microbubbles.

Abstract: A vertically mountable semiconductor device is described includes a plurality of bond pads disposed proximate to a single edge thereof. The bond pads are bumped with an electrically conductive material. The semiconductor device may also include a support member. Alternatively, the semiconductor device may be laminated to one or more adjacent semiconductor devices. The present invention also includes a method of attaching the semiconductor device to a carrier substrate. Preferably, solder paste is applied to terminals on the carrier substrate. The semiconductor device is oriented vertically over the carrier substrate, such that the bumped bond pads align with their corresponding terminals. The bumps are placed into contact with the solder paste. The bumps and solder paste are then fused to form a joint between the each of the bond pads and their respective terminal, establishing an electrically conductive connection therebetween and imparting structural stability to the semiconductor device.

Abstract: A method for producing a semiconductor device comprising the steps of: (A) forming a gate insulating layer on a surface of a semi-conductive layer, and then, forming a gate electrode on a gate insulating layer; (B) introducing an impurity in regions of the semi-conductive layer where source/drain regions are to be formed, and then, carrying out heat treatment for activation of the introduced impurity, to form source/drain regions in the semi-conductive layer, and (C) introducing an impurity into at least regions of the semi-conductive layer where extension regions are to be formed, and then, carrying out heat treatment for activation of the introduced impurity, to form extension regions in the semi-conductive layer.

Abstract: A pn-junction in a semiconductor element is made in that, within a zone of a first conductivity type, by means of implantation, a first and second zone of a second conductivity type are formed which are initially separated from each other, with subsequent diffusion processes, as a result of lateral diffusion, the first and second zones combine into a connected well, by means of implantation, a further zone of the first conductivity type is formed which completely overlaps the first zone of the second conductivity type and which is larger than the first zone, and which does not touch the second zone of the second conductivity type.

Abstract: A method of forming a planarized metal interconnect comprising the following steps. A semiconductor structure is provided. A low K dielectric layer is formed over the semiconductor structure. A sacrificial layer over is formed over the low K dielectric layer. The sacrificial layer and low K dielectric layer are patterned to form a trench within the sacrificial layer and low K dielectric layer. A barrier layer is formed over the sacrificial layer, lining the trench side walls and bottom. Metal is deposited on the barrier layer to form a metal layer filling the lined trench and blanket filling the sacrificial layer covered low K dielectric layer. The metal layer and the barrier layer are planarized, exposing the upper surface of the sacrificial layer. The sacrificial layer is removed to form a planarized metal interconnect.

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dual amorphization technique. The technique creates a shallow amorphous region and a deep amorphous region 300 nm thick. The shallow amorphous region can be between 10-40 nm below the top surface of the substrate, and the deep amorphous region can be between 150-200 nm below the top surface of the substrate. The process can reduce gate over-melting effects. The process can be utilized for P-channel or N-channel metal oxide semiconductor field effect transistors (MOSFETs).

Abstract: A solid state electronic device (40) comprising a substrate (30) and layers (32 and 34) is fabricated to control the formation of crystalline defects to control at least one characteristic of the device, such as current gain beta. The formation of crystalline defects preferably is controlled by controlling the temperature of the substrate, layers or both.

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dual amorphization technique. The technique creates a shallow amorphous region and a deep amorphous region 300 nm thick. The shallow amorphous region can be between 10-15 nm below the top surface of the substrate, and the deep amorphous region can be between 150-200 nm below the top surface of the substrate. The process can reduce gate over-melting effects. The process can be utilized for P-channel or N-channel metal oxide semiconductor field effect transistors (MOSFETs).

Abstract: The present invention is related to a method for post-oxidation heating of at least one substrate comprising at least a SiO2 layer or a SiO2/poly-Si layer structure, comprising the steps of: creating an inert gaseous ambient in a furnace, said ambient having a partial pressure within a predetermined range and said gaseous ambient comprising helium molecules, which have a suitable diameter for penetrating into the SiO2 and/or the poly-Si material; placing the substrate into said ambient; thereafter heating said furnace to a temperature of at least 200° C. for a predetermined period of time; cooling said furnace while maintaining said gaseous ambient in said predetermined pressure range in said furnace.

Abstract: In a silicon nitride film formation method, a substrate to be subjected to film formation is heated, and silicon tetrachloride and ammonia gases are supplied to the substrate heated to a predetermined temperature. The ratio of the partial pressure of the silicon tetrachloride gas to that of the ammonia gas is set to not less than 0.5.

Abstract: The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual ONO floating gates with an isolation spacer between floating gates. Processes for making the memory device according to the invention are also provided.

Abstract: A method for manufacturing a ferroelectric random access memory (FeRAM) device which includes the steps of preparing an active matrix provided with a transistor, diffusion regions, an isolation region, a bit line, a first insulating layer and a second insulating layer; forming a first conductive layer and then a dielectric layer on the active matrix; carrying out a rapid thermal annealing (RTA) for producing nuclei in the dielectric layer; forming a second conductive on top of the dielectric layer; carrying out a thermal annealing in a furnace; forming a capacitor structure provided with a top electrode, a capacitor thin film and a bottom electrode by patterning the second conductive, the dielectric and the first conductive layers into a first predetermined configuration; carrying out a first recovery; forming a third insulating layer on the capacitor structure and the second insulating layer; patterning the third insulating layer to form a first opening and a second opening; and carrying out a second recover

Abstract: A method for forming a silicone polymer insulation film having a low relative dielectric constant, high thermal stability and high humidity-resistance on a semiconductor substrate is applied to a plasma CVD apparatus. The first step is introducing a silicon-containing hydrocarbon compound expressed by the general formula Si&agr;O&bgr;CxHy (&agr;, &bgr;, x, and y are integers) to the reaction chamber of the plasma CVD apparatus. The silicon-containing hydrocarbon compound has at most two O—CnH2n+1 bonds and at least two hydrocarbon radicals bonded to the silicon. The residence time of the material gas is lengthened by, for example, reducing the total flow of the reaction gas, in such a way as to form a silicone polymer film having a micropore porous structure with a low relative dielectric constant.

Abstract: A method for polishing a dielectric layer containing silicon provides a fluorine-based inorganic compound during a polishing process. The dielectric layer is polished in the presence of the fluorine based compound to accelerate a polishing rate of the dielectric layer.

Abstract: A semiconductor chip assembly includes a semiconductor chip attached to a support circuit. The support circuit includes an insulative base, a conductive trace and a through-hole that extends through the conductive trace. A ball bond connection joint in the through-hole contacts and electrically connects the conductive trace and the pad. A method of manufacturing the assembly includes mechanically attaching the chip to the support circuit such that the through-hole exposes the pad, and then forming the ball bond in the through-hole using thermocompression or thermosonic wire bonding.

Abstract: An integrated sensor is fabricated by etching recesses or depressions into the top side of a semiconductor body and by fabricating sensor components in the recesses or depressions. The sensor components are lowered in the recesses or depressions by approximately half of their height. Electronic components are fabricated in the remaining regions of the top side of the semiconductor body. The remaining regions may be covered with a protective layer if the recesses or depressions are fabricated after the electronic components.