Abstract: In one aspect, the invention includes a method of forming a roughened layer of platinum, comprising: a) providing a substrate within a reaction chamber; b) flowing an oxidizing gas into the reaction chamber; c) flowing a platinum precursor into the reaction chamber and depositing platinum from the platinum precursor over the substrate in the presence of the oxidizing gas; and d) maintaining a temperature within the reaction chamber at from about 0° C. to less than 300° C. during the depositing. In another aspect, the invention includes a platinum-containing material, comprising: a) a substrate; and b) a roughened platinum layer over the substrate, the roughened platinum layer having a continuous surface characterized by columnar pedestals having heights greater than or equal to about one-third of a total thickness of the platinum layer.

Abstract: A method of fabricating a tunneling photodiode is presented comprised of the following steps: forming a p-well in an n-type substrate, forming a thin insulating layer over the surface of the p-type material, and then forming a thin n-type layer over the insulating layer. Preferably, the n and p type semiconductor material could be silicon and the insulating layer could be between about 30 to 40 angstroms of gate quality silicon dioxide. In other embodiments of the invention the materials of either electrode are either n or p-type semiconductors or metals.

Abstract: A method for manufacturing a semiconductor device having a first capacitor in a memory cell region and a second capacitor in a logic region is described. The method includes the steps of: a) forming an interlayer insulating layer on a blanket substrate; b) simultaneously forming a first opening portion and a second opening portion for the first capacitor and the second capacitor, respectively, by selectively etching the interlayer insulating layer; c) simultaneously forming bottom electrodes of the first capacitor and the second capacitor by forming a conductive layer within the first opening portion and the second opening portion; d) forming a dielectric layer on the bottom electrodes of the first capacitor and the second capacitor; and e) forming top electrodes of the first capacitor and the second capacitor on the dielectric layer.

Abstract: A process for improving the yield of semiconductors, such as high electron mobility transistors (HEMTs), which are susceptible to damage during conventional metal lift-off techniques. In accordance with an important aspect of the invention, damage to relatively fragile structures, such as submicron dimensioned structures on semiconductors are minimized by utilizing an adhesive tape to peel off undesired metal in close proximity to submicron dimension structures. By using an adhesive tape to peel off undesired metal, damage to submicron dimension structures is minimized thus improving the yield.

Abstract: For selectively removing a silicon nitride film formed on a bottom of a contact hole or the like in a semiconductor device, plasma etching is performed using a process gas supplied therefor which is comprised of a first fluorine compound including a carbon atom-carbon atom bond [for example, octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6), octafluorocyclopentene (C5F8)], and a second fluorine compound including at least one hydrogen atom and a single carbon atom in one molecule (for example, fluoromethane (CH3F), difluoromethane (CH2F2), trifluoromethane (CHF3)]. According to this method, the silicon nitride film on the bottom can be selectively removed without removing a silicon nitride film formed on a side wall of the contact hole and the like.

Abstract: A method for forming an oxide layer on a silicon substrate includes forming a sacrificial oxide layer on the silicon substrate, implanting nitrogen into the silicon substrate, annealing the silicon substrate having implanted nitrogen, removing the sacrificial oxide layer from the silicon substrate, and forming an oxide layer on the silicon substrate. The dose of nitrogen implanted into silicon is preferably higher than 1e14 cm31 2. The annealing process is preferably performed at temperatures in a range from about 550° C. to about 1000° C. and for a time period between about 1 second and about 2 hours.

Abstract: Improved dielectric layers are formed by surface treating the dielectric layer with a silane plasma prior to forming a subsequent layer thereon. Embodiments include forming a trench in a low k dielectric layer and modifying the side surfaces of the trench by subjecting the dielectric to a silane plasma produced in a PECVD chamber. A conductive feature is formed by depositing a conformal barrier layer on the low k dielectric including the treated side surfaces of the dielectric and depositing a conductive layer within the trench.

Abstract: Particles are removed from the surface of a substrate. Respective position coordinates of the particles on the surface are determined. A beam of electromagnetic energy is directed at the coordinates of each of the particles in turn, such that absorption of the electromagnetic energy at the surface causes the particles to be dislodged from the surface substantially without damage to the surface itself.

Abstract: Grooves are defined in a substrate having device isolation regions by dry etching using silicon nitride films and side wall spacers as masks. Thereafter, the side wall spacers lying on side walls of the silicon nitride films are removed and the substrate is subjected to thermal oxidation, whereby the surface of the substrate at a peripheral portion of each active region is subjected to so-called round processing so as to have a sectional shape having a convex rounded shape.

Abstract: The invention encompasses a method of forming a dielectric material. A nitrogen-comprising layer is formed on at least some of the surface of a rugged polysilicon substrate to form a first portion of a dielectric material. After the nitrogen-comprising layer is formed, at least some of the substrate is subjected to dry oxidation with one or both of NO and N2O to form a second portion of the dielectric material. The invention also encompasses a method of forming a capacitor. A layer of rugged silicon is formed over a substrate, and a nitrogen-comprising layer is formed on the layer of rugged silicon. Some of the rugged silicon is exposed through the nitrogen-comprising layer. After the nitrogen-comprising layer is formed, at least some of the exposed rugged silicon is subjected to dry oxidation conditions with one or both of NO and N2O. Subsequently, a conductive material layer is formed over the nitrogen-comprising layer. Additionally, the invention encompasses a capacitor structure.

Abstract: A method is described for forming a non-volatile memory comprising dividing a substrate into at least a memory array area and a logic device area. An oxide/nitride/oxide (ONO) layer is firstly formed on the substrate, and a photoresist layer is formed on the ONO layer by bit line photo process, and a bit line ion implantation process is performed on the substrate to form the plurality of bit lines structure. Then, a first polysilicon layer is deposited to form a plurality of word lines by word line photo condition. The complementary metal-oxide-semiconductor (CMOS) ONO layer is used to store the charge and the ONO layer is only touched by the photoresist layer once. Furthermore, the separated adjust photo condition of the memory array area and the logic device area can create a safe oxide thickness to solve the problem of leakage path between bit lines to bit lines by using a self-aligned silicide process.

Abstract: A method for manufacturing a semiconductor device constituting an JGHT is provided that allows to manufacture the device using an inexpensive wafer and with high yields, and achieves low losses. Specifically, after an emitter electrode is formed, a reverse principal surface is polished to a specified thickness. The center line average height Ra of the polished surface is controlled to be not more than 1 &mgr;m, and the filtered center line waviness Wca is kept within 10 &mgr;m. The polished surface is selectively cleaned with an aqueous chemical solution to remove particles. To the cleaned surface, phosphorus ions arc implanted for forming a field-stop layer and boron ions are implanted for forming a collector layer. The wafer is then put into a diffusion furnace and annealed at a temperature from 300° C. to 550° C. to form a field-stop layer and a collector layer. Finally, a collector electrode is formed.

Abstract: A method of forming self-aligned recessed MRAM structures is disclosed. Recessed pinned and sense magnetic layers of an MRAM stack are formed in recessed digit lines formed in an insulating layer.

Abstract: Rapid thermal nitridation is carried out to form a nitride film on a lower electrode which is made of silicon, and a tantalum oxide dielectric film is further formed thereon. Then, wet oxidization is carried out to oxidize the lower electrode through the dielectric film and the nitride film, thus an oxide film is formed between the lower electrode and the nitride film. Further, silicon which is not bonded to nitrogen in the nitride film is oxidized, thus an oxide film whose effective thickness is equal to or greater than 2 nm. The oxidization also recrystallizes the dielectric film. Finally, an upper electrode is formed, and the capacitor is completed.

Abstract: The present invention discloses a method for fabricating a non-volatile memory structure from a single layer of polysilicon in a semiconductor substrate, wherein the semiconductor substrate with two active areas, first and second, are divided by isolation regions. In accordance with this method, a doped buried layer is formed in the first active area. Then, a first floating gate is formed on the buried layer and a second floating gate is formed on the second active area from the single layer of polysilicon. Next, two doped regions are formed at opposite sides of the second floating gate in the second active areas. Finally, a floating gate connection line is employed to connect the first and second floating gate for making sure that the two floating gates are in the same potential.

Abstract: In a method for manufacturing a semiconductor device having a first insulation film, a second insulation film formed over the first insulation film, an inlaid interconnection formed in the second insulation film, and an organic film provided on the inlaid interconnection layer and the second insulation film, the organic film having a dielectric constant lower than the second insulation film, the organic film is grown inside a vacuum chamber.

Abstract: A method of making a ball grid array package wherein there is provided a partially fabricated package including a semiconductor die, leads and balls secured to predetermined ones of the leads. The leads and balls are concurrently coated with palladium. The die, leads and at least a portion of each of the balls are then encapsulated. Encapsulation includes providing a mold including a plurality of recesses, each recesses for receiving one of the balls. A plurality of cavities is provided in the package, each extending to one of the leads at the location of one of the balls. A plurality of mold members is provided, each extendable into one of the cavities to apply a force against the ball associated with the lead to which the cavity extends. The partially fabricated package is placed into the mold so that the balls extend into the recesses and the mold members extends into the cavities. The molding material is applied to the mold cavity to provide the encapsulation.

Abstract: A method for reworking integrated circuit (IC) wafers having copper-metallized bond pads exposed in protective overcoat openings and one or more bondable metal layers deposited onto the bond pads by a technology which may produce some parts with off-spec or missing depositions. After identifying the wafer with off-spec metal layers, a layer of glass buffer is deposited over those wafers, which also fill any missing depositions at least partially. The glass-covered surface is then chemically-mechanically polished until the off-spec metal layers and at least a portion of the protective overcoat are removed, without damaging the copper metallization. Finally, a fresh layer of protective overcoat is deposited, selectively opened to expose the bond pads, and provided anew with one or more bondable metal layers.

Abstract: A method of fabricating a silicide layer on a silicon region of a semiconductor structure, the method comprising the steps of: providing a semiconductor structure having at least one silicon region on a surface thereof; depositing a layer comprising nickel and platinum on the at least one silicon layer; annealing the semiconductor structure and the nickel/platinum layer to react the nickel and the platinum with underlying silicon to form a nickel-platinum silicide, wherein annealing step takes place at temperature of between 680° C. and 720° C.

Abstract: Methods are disclosed for the formation of isolation structures and trenches in semiconductor devices, in which lower corners of an isolation trench are rounded after trench formation using an oxidation process which oxidizes substrate material from the trench sidewalls and bottom faster than from the lower corners of the trench. The oxide formed during the rounding process is then removed prior to performing other etch processes, to expose substrate material having rounded lower corners. Thereafter, a liner is formed and the trench is filled with dielectric material to complete the isolation structure.