Abstract: A method of manufacturing a polarization switching surface-emitting laser in which a laser resonance wavelength depends on changing the polarization of the laser, by changing the refractivity of a compound semiconductor mirror layer of the laser depending on polarizations using an electro-optic effect of compound semiconductor materials such as GsAs and applying an electric field thereto.

Abstract: A method of patterning a gate electrode layer having an underlying high-k dielectric layer comprising the following sequential steps. A substrate is provided. A high-k dielectric layer is formed over the substrate. A gate electrode layer is formed over the high-k dielectric layer. The gate electrode layer is patterned to form a patterned gate electrode layer, the patterned gate electrode layer having exposed side walls and a top. Sidewall spacers are formed over the exposed side walls of the patterned gate electrode layer, the sidewall spacers having tops. The patterned gate electrode layer is etched to pull the top of the patterned gate electrode layer down from the tops of the sidewall spacers. The exposed portions of the high-k dielectric layer not under the sidewall spacers and the pulled-down patterned gate electrode layer are removed.

Abstract: A method of manufacturing reduces costs and provides an excellent mass-productivity, super-junction semiconductor device, which facilitates reducing times of heat treatment of the alternating conductivity type layer subjects, and preventing the characteristics of the alternating conductivity type layer from being impaired. A surface MOSFET structure, including p-type base regions, p+-type contact region in p-type base region, an n+-type source region in p-type base region, a gate electrode layer and a source electrode, is formed in the surface portion of an n-type semiconductor substrate through the usual double difflusion MOSFET manufacturing process. An oxide film is deposited by the CVD method on the back surface of the semiconductor substrate, a resist mask for defining p-type partition regions is formed on the oxide film, the oxide film is removed by ion etching, and trenches are dug.

Abstract: A method of manufacturing a low-k semiconductor structure including the steps of forming a low-k dielectric layer, forming a sacrificial etch stop layer adjacent the low-k dielectric layer, and applying energy to the sacrificial etch stop layer to diffuse a component of the sacrificial etch stop layer into the adjacent low-k dielectric layer. This diffusion of the component lowers the dielectric constant of the adjacent low-k dielectric layer.

Abstract: When a thin-film transistor (TFT) is formed on a glass substrate, electric charges caused in the TFT can be removed so as to avoid electrostatic damage in the TFT. A short-circuiting pattern that short-circuits the source region and the drain region of the TFT is added to a polysilicon pattern that constitutes the TFT. This short-circuiting pattern is removed at the same time as or after the wiring formation in the source region and the drain region.

Abstract: A method of forming a semiconductor device includes providing a semiconductor substrate with an active region, covering the active region of the semiconductor substrate with an oxide film, covering the oxide film with a first borophosphosilicate glass film, and covering the first borophosphosilicate glass film with a second borophosphosilicate glass film. The first borophosphosilicate glass film has a boron oxide concentration which is lower than that of the second borophosphosilicate glass film, and is thus a phosphorus diffusion preventing film.

Abstract: A method for forming a silicon carbide layer for use in integrated circuit fabrication is disclosed. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and an inert gas in the presence of an electric field. The electric field is generated using mixed frequency radio frequency (RF) power. The silicon carbide layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the silicon carbide layer is used as a hardmask for fabricating integrated circuit structures such as, for example, a damascene structure. In another integrated circuit fabrication process, the silicon carbide layer is used as an anti-reflective coating (ARC) for DUV lithography.

Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

Abstract: A method of making a connection component includes providing a removable layer having first and second surfaces and forming vias at spaced apart first locations of the removable layer. A conductive material, such as copper, is deposited over the first surface of the removable layer and in each of the vias to form one or more flexible leads including projections which extend downwardly in the vias toward the removable layer. Each lead includes a first end integrally connected with one of the projections and a second end remote from the first end. A substrate is provided over the conductive material. The removable layer is removed so that the first and second ends of the leads are movable away from one another. As a result, at least first or second ends of the leads are connected to the substrate without using a bonding or welding step.

Abstract: A method for improving adhesion of copper films to transition metal based barrier layers. Tantalum or other transition metal based barrier layers are deposited by chemical vapor deposition techniques using transition metal halide precursor materials which generate halogen atom impurities in the barrier layer. The barrier layer is treated with a plasma generated from a nitrogen-containing gas, such as ammonia. Halogen impurity levels are thereby decreased at the surface of the barrier layer. On this surface is subsequently applied a copper film by physical vapor deposition. The copper film exhibits improved adherence to the barrier layer.

Abstract: A method for manufacturing a semiconductor device can form a thick lower electrode made of Pt. The method begins with the preparation of an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conductive plugs. Thereafter, a seed layer is formed on top of the active matrix and a dummy oxide layer is formed on top of the seed layer. Then, the dummy oxide layer is patterned into a predetermined configuration, thereby exposing portions of the seed layer which are located on top of the conductive plugs. The exposed portions are filled with a conductive material to a predetermined thickness. The dummy oxide layer and portions of the seed layer which are not covered with the conductive material are removed, thereby obtaining lower electrodes. A capacitor dielectric layer is on the lower electrodes. Finally, an upper electrode layer is formed on the capacitor dielectric layer.

Abstract: A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

Abstract: A method of forming a damascene structure using a sacrificial conductive layer to provide a uniform focus plane for the photolithography tool during formation of circuit features. In particular, a metal layer is provided between the insulative layer and the photoresist, upon which the capacitive sensors of the photolithography tool focus during the formation of the circuit features, namely, troughs and vias.

Abstract: Within a dual damascene method for forming a dual damascene aperture within a microelectronic fabrication there is employed a bottom etch stop layer formed of a first material and an intermediate etch stop layer formed as a laminate of a second material having formed thereupon a third material. Within the method, the second material serves as an etch stop for the first material and the third material, which may be identical materials. Within the method, there may be etched completely through the bottom etch stop layer to reach a contact region formed there beneath while not etching completely through the intermediate etch stop layer to reach a first dielectric layer formed there beneath.

Abstract: A method for fabricating capacitor-under-bit line (CUB) DRAMs with logic circuits is achieved. CUB are better than capacitor-over-bit line (COB) DRAM circuits because of reduced contact aspect ratios, but CUB require patterning the capacitor top plate over the capacitor rough topography while providing openings to bit line contacts between closely spaced capacitors. A bottom antireflecting coating (BARC) is used in a first method; a non-conform PECVD oxide is used in a second method to make reliable high aspect ratio openings between the capacitors. The BARC is deposited to fill the space between capacitors. A photo-resist layer with improved uniformity is then deposited over the BARC and exposed and developed to form an etch mask with improved resolution for the capacitor top plate. The BARC is plasma etched, and the polysilicon plate is patterned. In the second method a non-conformal PECVD oxide is deposited that is thicker on the top of the capacitors than in the narrow space between capacitors.

Abstract: A method of manufacturing a high voltage device is described. A well region is formed within a substrate of a high voltage device region. A gate structure is made up of a gate oxide layer, a gate and an optional cap layer that are sequentially formed upon the well. Subsequently, using the gate structure as a mask, a large tilt angle light doping process is performed on the well of the high voltage device region of the well, thereby forming a lightly doped source and drain region. Thereupon, a optional thermal drive-in procedure is performed. Next, a spacer is formed on the side of the gate structure. Using the spacer and the gate structure as a mask, a heavy doping self-aligned ion implantation process is performed on the active region of the well, thereby forming a heavily doped source and drain region.

Abstract: The present invention is directed to a method for manufacturing a high performance transistor device with a reduced width or “t-shaped” gate electrode. The method disclosed herein comprises forming a gate insulation layer on a semiconducting substrate, forming a layer of polysilicon above the gate insulation layer, forming a layer of amorphous silicon above the layer of polysilicon, and patterning the layer of polysilicon and the layer of amorphous silicon to define a gate structure. The method further comprises reducing the width of the layer of polysilicon and the layer of amorphous silicon by performing an oxidation process, whereby the layer of polysilicon has a post-oxidation width that is less than the post-oxidation width of the layer of amorphous silicon, and forming a plurality of source/drain regions in the substrate adjacent the gate electrode of the device.

Abstract: The present invention discloses a method for fabricating a semiconductor device using an etch-resistant polymer. The method includes a step for the in-situ generation of a polymer layer on the exposed surfaces of a photoresist film pattern, a pad oxide film, and a hard mask layer. This polymer acts as a protective film and prevents photoresist erosion during trench etching processes and improves the etch selectivity. As a result, trench structures can be formed more easily and with improved dimensional control.

Abstract: The semiconductor device comprises a base substrate, a wiring 54 formed on the base substrate, a first insulating film 48, 56 for covering the upper surface and the side surfaces of the wiring 54, an etching stopper film 58 formed on the base substrate and the first insulating film 48, 56, a conductor plug 36b connected to the base substrate through the etching stopper film 58 and projected upper of the base substrate, and a capacitor 79 having one electrode 68 connected to the upper surface and the side surfaces of the conductor plug 36b. The electrode 68 is formed not only on the upper surface of the conductor plug 36b but also on the side walls thereof, whereby the electrode 68 can be fixed to the conductor plug 36b without failure.

Abstract: One or more capacitors are formed using thermally oxidized films formed on a silicon layer of an SOI substrate. The capacitors may be formed alone or together with other semiconductor elements on a single SOI substrate. A diffuse layer having an impurity in a high density is first formed on the silicon layer, and then an oxidized film is formed on the diffused layer by thermal oxidation. Then, contaminants in the oxidized film are driven-out under a high temperature heat treatment, thereby to improve quality of the oxidized film, such as durability against a high voltage. Plural capacitors may be formed using oxidized films having a respectively different thickness, by repeating thermal oxidation and removal of the oxidized film.