Abstract: An integrated circuit (IC) device includes a fin-type active region on a substrate. A mesa-type channel region protrudes from the fin-type active region in a vertical direction. The mesa-type channel region is integrally connected with the fin-type active region. A gate line substantially surrounds a mesa-type channel region on the fin-type active region. A gate dielectric film is between the mesa-type channel region and the gate line. The mesa-type channel region includes: a plurality of round convex portions, which are convex toward the gate line; a concavo-convex sidewall, which includes a portion of each of the plurality of round convex portions and faces the gate line; and at least one void, which is inside the mesa-type channel region.

Abstract: A light emitting device includes first and second electrodes disposed on a substrate; an insulating layer disposed on the substrate and including a groove extending in a first direction intersecting with the first and the second electrodes, and first and second contact portions that expose areas of the first and the second electrodes; light emitting elements disposed in the groove between the first and the second electrodes, each including first and second ends electrically connected to the first and second electrodes, respectively; a first contact electrode electrically connected to the light emitting elements on the first ends, and electrically connected to the first electrode on the first contact portion; and a second contact electrode electrically connected to the light emitting elements on the second ends, and electrically connected to the second electrode on the second contact portion.

Abstract: A device includes a substrate including a low-resistance top surface and a fin structure including a first fin and a second fin. Each of the first and second fins includes a low-resistance fin-top surface and two low-resistance sidewall surfaces. The device includes an insulation material over the top surface of the substrate and between the first fin and the second fin. The fin-top surface and a first portion of the sidewall surfaces of each of the first and the second fins are above the insulation material. The device further includes a dielectric layer over the insulation material and in direct contact with the fin-top surface and the first portion of the sidewall surfaces of each of the first and the second fins; a first electrode in direct contact with the fin-top surface of the first fin; and a second electrode over the dielectric layer that is over the second fin.

Abstract: A method for forming a drift region of a superjunction transistor and a superjunction transistor device are disclosed. The method includes forming first regions of a first doping type and second regions of a second type in a semiconductor body such that the first and second regions are arranged alternatingly in the body. The first and second regions are formed by: forming trenches in at least one semiconductor layer; implanting first type dopant atoms and second type dopant atoms into opposing sidewalls of the trenches; filling the trenches with a semiconductor material; and diffusing the dopant atoms in a thermal process so that the first type dopant atoms form the first regions and the second type dopant atoms form the second regions. Each trench has a first width, the trenches are separated by mesa regions each having a second width, and the first width is greater than the second width.

Abstract: The reflectance of a low-reflectance alignment mark is increased by coating the alignment mark with a high-reflectance film layer. This improves the strength of the light signal and reduces variation in the light signal.

Abstract: Provided is an electrostatic discharge protection device, including: a darlington structure formed in a substrate, and a diode string formed in the substrate and including a plurality of diodes connected in series. A first end of the darlington structure is connected to a first voltage, and a second end of the darlington structure is connected to a second voltage. An anode of the diode string is connected to a third end of the darlington structure. A cathode of the diode string is connected to the second voltage.

Abstract: The present application discloses an array substrate, a display panel, and a display apparatus. The array substrate includes a hole-punching area, a wiring area at least partially surrounding the hole-punching area and a wire-wrapping area between the hole-punching area and the wiring area, the array substrate includes: a substrate and a first wiring layer arranged on the substrate; a shielding assembly at least including a first shielding layer arranged on a side of the first wiring layer, the side of the first wiring layer being away from the substrate, and the first shielding layer being insulated from the first signal wires in the first wiring layer, the first shielding layer being electrically connected to a first fixed potential terminal, wherein an orthographic projection of the first shielding layer on the substrate covers an orthographic projection of the first wire-wrapping segment of the first signal wire on the substrate.

Abstract: An imaging device may include a plurality of single-photon avalanche diode (SPAD) pixels. The SPAD pixels may be overlapped by microlenses to direct light incident on the pixels onto photosensitive regions of the pixels and a containment grid with openings that surround each of the microlenses. During formation of the microlenses, the containment grid may prevent microlens material for adjacent SPAD pixels from merging. To ensure separation between the microlenses, the containment grid may be formed from material phobic to microlens material, or phobic material may be added over the containment grid material. Additionally, the containment grid may be formed from material that can absorb stray or off-angle light so that it does not reach the associated SPAD pixel, thereby reducing crosstalk during operation of the SPAD pixels.

Abstract: An overlay mark, an overlay measurement method using the same, and a manufacturing method of a semiconductor device using the same are provided. The overlay mark is for measuring an overlay based on an image, is configured to determine a relative misalignment between at least two pattern layers, and includes first to fourth overlay marks. The first overlay mark has a pair of first Moire patterns disposed on a center portion of the overlay mark. The second overlay mark has a pair of second Moire patterns disposed so as to face each other with the first Moire patterns interposed therebetween. The third overlay mark has a pair of third Moire patterns disposed on a first diagonal line with the first Moire patterns interposed therebetween. The fourth overlay mark has a pair of fourth Moire patterns disposed on a second diagonal line with the first Moire patterns interposed therebetween.

Abstract: A light-emitting device includes a substrate, first and second light-emitting elements, a first frame, and first and second wavelength conversion members. The first light-emitting element is disposed on a first surface or first wirings of the substrate and electrically connected to the first wirings via first connecting members. The second light-emitting element is disposed on a surface of the first light-emitting element, and electrically connected to the second wirings via second connecting members. The first frame surrounds the first and second light-emitting elements in a top view. The first wavelength conversion member is disposed in a region surrounded by the first frame. The second wavelength conversion member is disposed in at least a part of the region surrounded by the first frame in the top view. A chromaticity of light converted by the first wavelength conversion member differs from a chromaticity of light converted by the second wavelength conversion member.

Abstract: A transient voltage suppressor (TVS) device includes a MOS-triggered silicon controlled rectifier (SCR) as the high-side steering diode and a silicon controlled rectifier (SCR) for the low-side steering diode. In one embodiment, the MOS-triggered SCR includes alternating p-type and n-type regions and a diode-connected MOS transistor integrated therein to trigger the silicon controlled rectifier to turn on. In one embodiment, the SCR of the low-side steering diode includes alternating p-type and n-type regions where the p-type region adjacent the n-type region forming the cathode terminal is not biased to any electrical potential.

Abstract: An integrated circuit is disclosed comprising at least one first field effect transistor, having at least one first source contact and at least one first drain contact and at least one first gate contact, and at least one second field effect transistor, having at least one second source contact and at least one second drain contact and at least one second gate contact, wherein the first drain contact is connected to the second drain contact, and the first source contact is coupled to the second gate contact, wherein the first source contact, the first drain contact, the first gate contact, the second source contact, the second drain contact and the second gate contact are implemented as structured metallization layers on a single substrate, and the first and second drain contacts share at least one single dedicated surface area on said substrate.

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure in the semiconductor substrate for isolating a first active region and a second active region, a first device formed in the first active region, and a second device formed in the second active region. The first device has a first gate dielectric layer and a first gate electrode over the first gate dielectric layer. The first gate electrode includes at least one of Ta and C, and has a first work function for a first conductivity. The second device has a second gate dielectric layer and a second gate electrode over the second gate dielectric layer. The second gate electrode includes at least one of Ta, C, and Al, and has a second work function for a second conductivity. The second conductivity is different from the first conductivity.

Abstract: A super junction semiconductor device includes a substrate of a first conductive type, the substrate including an active region, a peripheral region surrounding the active region and a transition region interposed between the active region and the peripheral region, an epitaxial layer disposed on the substrate, the epitaxial layer having a the first conductive type, a plurality of pillars extending in a vertical direction and arranged within the epitaxial layer, gate structures disposed on the epitaxial layer in both the active region and the transition region, and the each of the gate structures extending across the epitaxial layer and the pillars in a horizontal direction, and a reverse recovery layer of a second conductive type, the reverse recovery layer having a vertical formation heights different as between on the pillars and on the epitaxial layer, the reverse recovery layer configured to dissipate a reverse recovery current in the transition layer.

Abstract: A mark for overlay error measurement and overlay error measurement is provided. The mark includes a first pattern and a second pattern. The first pattern is disposed on a first surface of a substrate. The second pattern is disposed on a second surface of the substrate. The second surface of the substrate is opposite to the first surface of the substrate. The first pattern overlaps at least a portion of the second pattern, and the first pattern and the second pattern collaboratively define a first overlay error.

Abstract: A display device is disclosed, which includes: a substrate; a first transistor disposed on the substrate; and a second transistor disposed on the substrate. The first transistor includes: a first active layer; a first electrode and a second electrode electrically connecting to the first active layer; and a conducting layer at least partially covering one of the first electrode and the second electrode. The second transistor includes a second active layer. Herein, one of the first active layer and the second active layer includes a polysilicon layer, and the other one of the first active layer and the second active layer includes a metal oxide layer.

Abstract: The light emitting element according to the present disclosure comprises a first active layer that emits light having a first wavelength by injecting current, a second active layer that emits light having a second wavelength different from the first wavelength by absorbing the light having the first wavelength, and a first reflecting mirror in which a reflectance of light having the first wavelength is higher than a reflectance of light having the second wavelength, wherein the first reflecting mirror is disposed at a position closer to an emission end, from which the light emitted by the first active layer or the second active layer exits outside, than the first active layer and the second active layer.

Abstract: An optoelectronic device includes first and second light-emitting diodes, each LED having: a first semiconductor portion, with a first type of doping, having a wire-like shape along an axis and having side surfaces parallel to this axis; an active portion arranged at least partially on a top end of the first portion; and a second semiconductor portion, with a second type of doping, arranged at least partially on all or part of the active portion. The optoelectronic device further includes an electrically resistive layer having an electrical resistance that is higher than that of the active portion, covering at least all or part of the side surfaces of the first portion and all or part of the surface of the top end of the first portion not covered by the active portion. The resistive layers of the first and second LEDs are separated from one another.

Abstract: The present disclosure provides an organic light-emitting diode display panel, a method for preparing the same, and a display device. The organic light-emitting diode display panel includes a substrate, a light-emitting structure layer arranged on the substrate, and a light modulation layer arranged on a light exiting path of the light-emitting structure layer and configured to adjust a direction of an emergent light beam.

Abstract: Systems for apparatuses formed of light emitting devices. Solutions for controlling the off-state appearance of lighting system designs is disclosed. Thermochromic materials are selected in accordance with a desired off-state of an LED device. The thermochromic materials are applied to a structure that is in a light path of light emitted by the LED device. In the off-state the LED device produces a desired off-state colored appearance. When the LED device is in the on-state, the thermochromic materials heat up and become more and more transparent. The light emitted from the device in its on-state does not suffer from color shifting due to the presence of the thermochromic materials. Furthermore, light emitted from the LED device in its on-state does not suffer from attenuation due to the presence of the thermochromic materials. Techniques to select and position thermochromic materials in or around LED apparatuses are presented.