Patents Examined by Bilkis Jahan
  • Patent number: 11476363
    Abstract: A semiconductor device includes a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a trench, and a contact layer. The first gate structure is disposed on a front-side of the buried dielectric layer, and the second gate structure is disposed on a backside of the buried dielectric layer. The first source/drain region and a second source/drain region are disposed between the first gate structure and the second gate structure. The trench is formed in the buried dielectric layer, and the contact layer is disposed in the trench and electrically coupled to the second source/drain region, where the contact structure and the second gate structure are formed of the same material.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: October 18, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Ching-Yang Wen, Li Wang, Kai Cheng
  • Patent number: 11469136
    Abstract: A technique to make silicon oxide regions from porous silicon and related semiconductor structures is disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: October 11, 2022
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Simone Dario Mariani, Fabrizio Fausto Renzo Toia, Marco Sambi, Davide Giuseppe Patti, Marco Morelli, Giuseppe Barillaro
  • Patent number: 11469236
    Abstract: Integrated circuitry comprises a first conductive line buried within semiconductive material of a substrate. The first conductive line comprises conductively-doped semiconductor material directly above and directly against metal material in a vertical cross-section. A second conductive line is above the semiconductive material and is laterally-spaced from the first conductive line in the vertical cross-section. The second conductive line comprises metal material in the vertical cross-section. Insulative material is directly above the first and second conductive lines. A first conductive via extends through the insulative material and through the conductively-doped semiconductor material to the metal material of the first conductive line. A second conductive via extends through the insulative material to the metal material of the second conductive line. Other embodiments and aspects, including method, are disclosed.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: October 11, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Si-Woo Lee
  • Patent number: 11450765
    Abstract: A quantum dot device is disclosed that includes a fin and a gate above the fin. The fin may extend away from a base and include a quantum well stack in which one or more quantum dots may be formed during operation of the quantum dot device. The gate may include a gate electrode material having a first portion and a second portion, where the first portion is above the quantum well stack and the second portion is a portion that is not above the quantum well stack and is separated from the base by an insulating material. The quantum dot device may further include a metal structure between the second portion of the gate electrode material and the base, forming a portion of a diode provided in series with the gate, which diode may provide at least some ESD protection for the quantum dot device.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: September 20, 2022
    Assignee: Intel Corporation
    Inventors: Hubert C. George, Ravi Pillarisetty, Lester Lampert, James S. Clarke, Nicole K. Thomas, Roman Caudillo, Kanwaljit Singh, David J. Michalak, Jeanette M. Roberts
  • Patent number: 11450564
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a source/drain region adjacent to two sides of the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a contact hole in the ILD layer to expose the source/drain region; forming a barrier layer in the contact hole; performing an anneal process; and performing a plasma treatment process to inject nitrogen into the contact hole.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: September 20, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jin-Yan Chiou, Wei-Chuan Tsai, Yen-Tsai Yi, Li-Han Chen, Hsiang-Wen Ke
  • Patent number: 11450657
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first well, a second well and doped regions. The substrate has heavily doped and lightly doped regions over the heavily doped region. The first wells are disposed in the lightly doped region and arranged as an array. The first wells have a conductive type opposite to a conductive type of the heavily doped and lightly doped regions. The second well is disposed in the substrate over the lightly doped region, and has an active region defined by an isolation structure. The first wells are overlapped with the second well. Top ends of the first wells are lower than a bottom end of the second well. The doped regions are separately located in the active region, and have a conductive type opposite to a conductive type of the second well.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: September 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Hsi-Yu Kuo, Yu-Lin Chu
  • Patent number: 11444088
    Abstract: Some embodiments include a method of forming an integrated assembly. A structure is provided to have conductive lines, and to have rails over the conductive lines and extending in a direction which crosses the conductive lines. Each of the rails includes pillars of semiconductor material. The rails have sidewall surfaces along spaces between the rails. The pillars have upper segments, middle segments and lower segments. First-material liners are formed along the sidewall surfaces of the rails. A second material is formed over the liners. First sections of the liners are removed to form gaps between the second material and the sidewall surfaces of the rails. Second sections of the liners remain under the gaps. Conductive material is formed within the gaps. The conductive material is configured as conductive lines which are along the middle segments of the pillars.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: September 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Hong Li, Ramaswamy Ishwar Venkatanarayanan, Sanh D. Tang, Erica L. Poelstra
  • Patent number: 11437406
    Abstract: A semiconductor device may be provided, including a substrate which includes a first semiconductor layer having a well region arranged within the first semiconductor layer, a buried insulator layer arranged over the first semiconductor layer, and a second semiconductor layer arranged over the buried insulator layer. The semiconductor device may include a capacitive structure including: the well region, at least one contact to the well region, at least a portion of the buried insulator layer over the well region, at least a portion of the second semiconductor layer, a source region and a drain region arranged over the second semiconductor layer, a gate dielectric layer arranged over the second semiconductor layer and arranged laterally between the source region and the drain region, and a gate layer arranged over the gate dielectric layer. The well region, the source region, and the drain region may have the same conductivity type.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: September 6, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Phyllis Shi Ya Lim, Handoko Linewih, Shu Zhong, Chor Shu Cheng
  • Patent number: 11437478
    Abstract: A semiconductor device, its manufacturing method, and a radiation measurement method are presented, relating to semiconductor techniques. The semiconductor device includes: a substrate comprising a base area and a collector area adjacent to each other; a plurality of semiconductor fins on the substrate, wherein the plurality of semiconductor fins comprises at least a first semiconductor fin and a second semiconductor fin on the base area and separated from each other, the first semiconductor fin comprises an emission area adjacent to the base area, and the second semiconductor fin comprises a first region adjacent to the base area; a first gate structure on the second semiconductor fin; and a first source and a first drain at two opposite sides of the first gate structure and at least partially in the first region. Radiation in a semiconductor apparatus can be measured through this semiconductor device.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: September 6, 2022
    Inventor: Fei Zhou
  • Patent number: 11430863
    Abstract: A semiconductor device includes a source region, a drain region, and a gate insulating film formed on a substrate, a gate electrode formed on the gate insulating film, a first insulating film pattern formed to extend from the source region to a part of a top surface of the gate electrode, and a spacer formed on a side surface of the gate electrode in a direction of the drain region.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: August 30, 2022
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Guk Hwan Kim
  • Patent number: 11430782
    Abstract: The present disclosure provides a silicon controlled rectifier and a manufacturing method thereof. The silicon controlled rectifier comprises: a P-type substrate; an N-type well 60, an upper portion of which is provided with a P-type heavily doped region 20 and an N-type heavily doped region 28; an N-type well 62, an upper portion of which is provided with a P-type heavily doped region 22 and an N-type heavily doped region 26; and a P-type well 70 connecting the N-type well 60 and the N-type well 62, an upper portion of which is provided with a P-type heavily doped region 24; wherein a first electrode is in mirror symmetry with a second electrode with respect to the P-type heavily doped region 24, and shallow trench isolations are respectively provided between the P-type heavily doped region 24 and each of the N-type heavily doped region 28 and the N-type heavily doped region 26.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: August 30, 2022
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventor: Tianzhi Zhu
  • Patent number: 11424343
    Abstract: A method of forming a fin field effect transistor device is provided. The method includes forming a plurality of vertical fins on a substrate. The method further includes forming a bottom source/drain layer adjacent to the plurality of vertical fins, and growing a doped layer on the bottom source/drain layer and sidewalls of the plurality of vertical fins. The method further includes forming a dummy gate liner on the doped layer and the bottom source/drain layer, and forming a dummy gate fill on the dummy gate liner. The method further includes forming a protective cap layer on the dummy gate fill, and removing a portion of the protective cap layer to expose a top surface of the plurality of vertical fins.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: August 23, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Choonghyun Lee, Shogo Mochizuki
  • Patent number: 11424239
    Abstract: Embodiments may relate to a package substrate that is to couple with the die. The package substrate may include a signal line that is communicatively coupled with the die. The package substrate may further include a conductive line. The package substrate may further include a diode communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed.
    Type: Grant
    Filed: December 21, 2019
    Date of Patent: August 23, 2022
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel A. Elsherbini, Feras Eid, Veronica Aleman Strong, Johanna M. Swan
  • Patent number: 11424355
    Abstract: A method of fabricating a gate stack for a power transistor device includes thermally oxidizing a surface of a Group IIIA-N layer on a substrate to form a first dielectric layer of an oxide material that is >5 A thick. A second dielectric layer being silicon nitride or silicon oxynitride is deposited on the first dielectric layer. A metal gate electrode is formed on the second dielectric layer.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: August 23, 2022
    Assignee: Texas Instruments Incorporated
    Inventor: Nicholas Stephen Dellas
  • Patent number: 11424321
    Abstract: The present invention provides a semiconductor structure and a preparation method thereof. A transition metal and an impurity are co-doped on a buffer layer above a substrate layer to reduce the leakage current of a semiconductor device, to improve the pinch-off behavior, and to avoid the device current collapse, moreover, the ranges of the concentration of the transition metal and the impurity in the buffer layer are controlled to ensure the balance of the leakage current during the dynamic characteristics of the device.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: August 23, 2022
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventors: Kai Cheng, Kai Liu
  • Patent number: 11417811
    Abstract: A light emitting element includes a semiconductor stacked body, an insulating film, first and second electrodes, a second external connection portion, and first external connection portions. The first semiconductor layer is exposed at a plurality of exposed portions disposed in a plurality of rows in plan view. The first external connection portions include at least one smaller-size first external connection portion disposed between adjacent ones of the rows other than the outermost one of the rows, and at least one larger-size first external connection portion extending from the end region, in which a spacing between a first outer edge of a second semiconductor layer and the exposed portions in the outermost one of the rows is narrower than a spacing between the exposed portions in adjacent ones of the rows, to at least a position between the outermost one of the rows and an adjacent one of the rows.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: August 16, 2022
    Assignee: NICHIA CORPORATION
    Inventors: Koichi Takenaga, Takanori Fukumori, Satoshi Shichijo, Hiroki Fukuta, Kunihito Sugimoto
  • Patent number: 11410995
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes a well region extending in a first direction; a gate electrode disposed within the substrate and overlapping the well region; a gate dielectric layer disposed within the substrate and laterally surrounding the gate electrode; a plurality of first protection structures disposed over the gate electrode; a second protection structure extending in a second direction different from the first direction over the gate dielectric layer; and an insulating layer extending in the second direction between the second protection structure and the gate dielectric layer.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jhu-Min Song, Chien-Chih Chou, Kong-Beng Thei, Fu-Jier Fan
  • Patent number: 11410990
    Abstract: A silicon carbide MOSFET device includes a gate pad area, a main MOSFET area and a secondary MOSFET area. A main source contact is electrically coupled to the source region of each of the main MOSFETs, and a separate secondary source contact is electrically coupled to the source region of each of the secondary MOSFETs. A gate contact electrically connects to each of the insulated gate members of the main and secondary MOSFETs. An asymmetric gate clamping circuit is coupled between the secondary source contact and the gate contact. In a first mode of operation of the MOSFET device the main source contact is electrically coupled with the secondary source contact to activate the gate clamping circuit. When activated, the circuit clamping a gate-to-source voltage to a first clamp voltage in an on-state of the MOSFET device, and to a second clamp voltage in an off-state of the MOSFET device.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: August 9, 2022
    Assignee: SEMIQ INCORPORATED
    Inventors: Rahul R. Potera, Carl A. Witt
  • Patent number: 11404309
    Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Jen Chang, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
  • Patent number: 11404457
    Abstract: An image sensor may include a substrate including a plurality of unit pixel regions and having first and second surfaces facing each other. Each of the unit pixel regions may include a plurality of floating diffusion parts spaced apart from each other in the substrate, storage nodes provided in the substrate to be spaced apart from and facing the floating diffusion parts, a transfer gate adjacent to a region between the floating diffusion parts and the storage nodes, and photoelectric conversion parts sequentially stacked on one of the first and second surfaces. Each of the photoelectric conversion parts may include common and pixel electrodes respectively provided on top and bottom surfaces thereof and each pixel electrode may be electrically connected to a corresponding one of the storage nodes.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: August 2, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gwi-Deok Ryan Lee, Taeyon Lee