Patents Examined by Bilkis Jahan
  • Patent number: 10734574
    Abstract: A perpendicular synthetic antiferromagnetic (pSAF) structure and method of making such a structure is disclosed. The pSAF structure comprises a first high perpendicular Magnetic Anisotropy (PMA) multilayer and a second high PMA layer separated by a thin Ruthenium layer. Each PMA layer is comprised of a first cobalt layer and a second cobalt layer separated by a nickel/cobalt multilayer. After each of the first and second PMA layers and the Ruthenium exchange coupling layer are deposited, the resulting structure goes through a high temperature annealing step, which results in each of the first and second PMA layers having a perpendicular magnetic anisotropy.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: August 4, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Bartlomiej Adam Kardasz, Mustafa Michael Pinarbasi, Jacob Anthony Hernandez
  • Patent number: 10729382
    Abstract: Systems and methods for determining a model for predictive inference on an operation of a machine. A processor is configured to acquire time series data, the times series data includes training data and test data, the time series data represents an operation of the machine for a period of time, and the training data includes observations labeled with an outcome of the predictive inference. Apply recursive and stable filters for filtering at a training time, at a test time or both, such that a data point in the filtered time series data corresponds to an observation in the time series data that is a function of the corresponding observation and past observations in the time series data preceding the corresponding observation. Determine the model for the predictive inference using the training data, based on filtering the training data with filters to produce filtered time series data, and store in memory.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: August 4, 2020
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Amir massoud Farahmand, Daniel Nikolaev Nikovski
  • Patent number: 10734437
    Abstract: A chip-scale packaging process for wafer-level camera manufacture includes aligning an optics component wafer with an interposer wafer having a photoresist pattern that forms a plurality of transparent regions, bonding the aligned optics component wafer to the interposer wafer, and dicing the bonded optics component wafer and interposer wafer such that each optics component with interposer has a transparent region. The process further includes dicing an image sensor wafer, aligning the pixel array of each image sensor with the transparent region of a respective optics component with interposer, and bonding each image sensor to its respective optics component with interposer. Each interposer provides alignment between its respective optics component center and its respective pixel array center of the image sensor based on the respective transparent region. The interposer further provides a back focal length for focusing light from the optics component onto a top surface of the pixel array.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: August 4, 2020
    Assignee: OmniVision Technologies, Inc.
    Inventors: Teng-Sheng Chen, Chia-Yang Chang, Yi Qin
  • Patent number: 10727160
    Abstract: Thermal management technology is disclosed. A thermal management component in accordance with the present disclosure can comprise a heat spreader having a plurality of microchannels. The thermal management component can also comprise a plurality of fins directly coupled to the heat spreader to provide surface area for heat transfer. In another aspect, a thermal management component can comprise a heat spreader having a plurality of microchannels, and an inlet port and an outlet port in fluid communication with the plurality of microchannels. The thermal management component can also comprise a plurality of fins coupled to the heat spreader to provide surface area for heat transfer. Additionally, the thermal management component can comprise a fluid conduit thermally coupled to the plurality of fins and fluidly coupled to the outlet port and the inlet port to facilitate flow of a heat transfer fluid through the microchannels and the fluid conduit.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Devdatta P. Kulkarni, Richard J. Dischler, Je-Young Chang
  • Patent number: 10720413
    Abstract: Disclosed is an LED package, an LED module and a method for manufacturing the LED package. The LED package includes a lead frame comprising an insulating substrate and a plurality of first pins to a plurality of fourth pins formed on the insulating substrate, a plurality of first bonding pads to a plurality of fourth bonding pads, and a plurality of first wires to a plurality of fourth wires; a plurality of pixel units, each of which includes a first LED element, a second LED element and a third LED element; and an encapsulating composition covering the lead frame and allowing light to transmit. The LED package includes the plurality of LED elements of pixel units and implements internal interconnection with additional wires, thereby reducing the number of bonding pads of the LED package, and thus the manufacturing cost is reduced and the product reliability is improved.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: July 21, 2020
    Assignee: HANGZHOU MULTI-COLOR OPTOELECTRONICS CO., LTD.
    Inventors: Zhongyong Jiang, Wenyue Fu
  • Patent number: 10720511
    Abstract: Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: July 21, 2020
    Assignee: MaxPower Semiconductor Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
  • Patent number: 10720364
    Abstract: A method of forming a fin field effect transistor circuit is provided. The method includes forming a plurality of vertical fins on a substrate, and forming a protective liner having a varying thickness on the substrate and plurality of vertical fins. The method further includes removing thinner portions of the protective liner from the substrate to form protective liner segments on the plurality of vertical fins. The method further includes removing portions of the substrate exposed by removing the thinner portions of the protective liner to form trenches adjacent to at least one pair of vertical fins and two substrate mesas. The method further includes laterally etching the substrate mesa to widen the trench, reduce the width of the substrate mesa to form a supporting pillar, and undercut the at least one pair of vertical fins, and forming a first bottom source/drain layer in the widened trench.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: July 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Choonghyun Lee
  • Patent number: 10720372
    Abstract: Disclosed is a cooling assembly for circuit boards. In one embodiment, the assembly includes a circuit board that is thermally and physically coupled to a heat spreader by a thermal interface. In one configuration, the circuit board is formed from a semiconductor material and includes a first board surface on which integrated circuits are mounted and a second board surface opposite the first board surface. The heat spreader is formed from a thermally conductive material and includes a plurality of vanes that are spaced apart from one another. The thermal interface is coupled between at least one area of the second board surface of the circuit board and a contact area of each of the plurality of vanes. Heat generated by the integrated circuits is conducted from at least one integrated circuit to the plurality of vanes of the heat spreader through the circuit board and the thermal interface.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: July 21, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Douglas Patrick Kelley
  • Patent number: 10714396
    Abstract: The method includes prior to depositing a gate on a first vertical FET on a semiconductor substrate, depositing a first layer on the first vertical FET on the semiconductor substrate. The method further includes prior to depositing a gate on a second vertical FET on the semiconductor substrate, depositing a second layer on the second vertical FET on the semiconductor substrate. The method further includes etching the first layer on the first vertical FET to a lower height than the second layer on the second vertical FET. The method further includes depositing a gate material on both the first vertical FET and the second vertical FET. The method further includes etching the gate material on both the first vertical FET and the second vertical FET to a co-planar height.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 10714428
    Abstract: Some embodiments are directed to a semiconductor power device and a method of assembling such a device is provided. The semiconductor power device includes a first substrate, a second substrate and an interconnect structure. The first substrate includes a switching semiconductor element, a first electrically conductive layer(s) and a first receiving element. The second substrate includes a second receiving element and a second electrically conductive layer(s). The interconnect structure provides an electrical connection between the first electrically conductive layer and the second electrically conductive layer. The interconnect structure further includes a plurality of interconnect elements of an electrical conductive material. At least one of the plurality of interconnect elements is an alignment interconnect element.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: July 14, 2020
    Assignee: AGILE POWER SWITCH 3D—INTEGRATION APSI3D
    Inventors: Jean-Michel Francis Reynes, Jacques Pierre Henri Favre, Renaud André Lacabanne
  • Patent number: 10714397
    Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first semiconductor material and a second semiconductor material, patterning the semiconductor layer to form a preliminary active pattern, oxidizing at least two sidewalls of the preliminary active pattern to form an oxide layer on each of the at least two sidewalls of the preliminary active pattern, at least two upper patterns and a semiconductor pattern being formed in the preliminary active pattern when the oxide layers are formed, the semiconductor pattern being disposed between the at least two upper patterns, and removing the semiconductor pattern to form an active pattern, the active pattern including the at least two upper patterns. A concentration of the second semiconductor material in each of the at least two upper patterns is higher than a concentration of the second semiconductor material in the semiconductor pattern.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: July 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Mirco Cantoro, Maria Toledano Luque, Yeoncheol Heo, Dong Il Bae
  • Patent number: 10714590
    Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing at least one fin on a semiconductor substrate; forming a stacked channel layer having at least one sacrificial layer on the fin and a channel layer on the sacrificial layer; forming a dummy gate structure on the stacked channel layer; forming openings in the stacked channel layer at both sides of the dummy gate structure; removing portions of the sacrificial layer under the dummy gate structure to form grooves on sidewall surfaces of the openings; and forming a protective layer in the grooves.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: July 14, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) Corporation
    Inventor: Fei Zhou
  • Patent number: 10707130
    Abstract: Systems and methods for dicing a sample by a Bessel beam matrix are disclosed. The method for dicing a sample by a Bessel beam matrix may comprise generating a Bessel beam matrix including multiple Bessel beams arranged in a matrix form, according to a predetermined dicing layout of the sample; controlling a focus position of each Bessel beam in the generated Bessel beam matrix; and focusing simultaneously the Bessel beams of the Bessel beam matrix at the respective controlled focus positions within the sample for dicing.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: July 7, 2020
    Assignee: The Chinese University of Hong Kong
    Inventors: Shih-Chi Chen, Hiu Hung Lee, Dapeng Zhang, Erxuan Zhao, Yina Chang, Dihan Chen
  • Patent number: 10707087
    Abstract: Representative implementations provide techniques for processing integrated circuit (IC) dies and related devices, in preparation for stacking and bonding the devices. The disclosed techniques provide removal of processing residue from the device surfaces while protecting the underlying layers. One or more sacrificial layers may be applied to a surface of the device during processing to protect the underlying layers. Processing residue is attached to the sacrificial layers instead of the device, and can be removed with the sacrificial layers.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: July 7, 2020
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Cyprian Emeka Uzoh, Guilian Gao
  • Patent number: 10700001
    Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mirng-Ji Lii, Chung-Shi Liu, Chin-Yu Ku, Hung-Jui Kuo, Alexander Kalnitsky, Ming-Che Ho, Yi-Wen Wu, Ching-Hui Chen, Kuo-Chio Liu
  • Patent number: 10700248
    Abstract: A light emitting device includes: a rectangular substrate, a light emitting element, a reflective member disposed at one or more lateral sides of the light emitting element while being away from therefrom, a light guide member, and a light transmissive member on the light guide member. The reflective member includes one or more first reflective members opposing lateral faces of the light emitting element, and a second reflective member outside the first reflective member. The first reflective members have inner lateral faces opposing each other each having an oblique or curved portion slanted so that a distance therebetween increases towards the light transmissive member from a side close to the substrate. The second reflective member covers outer lateral faces of the light transmissive member and the first reflective members, and an upper face of the second reflective member is flush with an upper face of the light transmissive member.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: June 30, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Tadaaki Ikeda, Toru Hashimoto
  • Patent number: 10692847
    Abstract: Discussed generally herein are methods and devices for multichip packages that include an inorganic interposer. A device can include a substrate including low density interconnect circuitry therein, an inorganic interposer on the substrate, the inorganic interposer including high density interconnect circuitry electrically connected to the low density interconnect circuitry, the inorganic interposer including inorganic materials, and two or more chips electrically connected to the inorganic interposer, the two or more chips electrically connected to each other through the high density interconnect circuitry.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Daniel Sobieski, Kristof Darmawikarta, Sri Ranga Sai Boyapati, Merve Celikkol, Kyu Oh Lee, Kemal Aygun, Zhiguo Qian
  • Patent number: 10685956
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first well, a second well, and first and second doped regions. The substrate has heavily doped and lightly doped regions. The lightly doped region is disposed over the heavily doped region. The first well is disposed in the lightly doped region. The first well has a conductive type complementary to a conductive type of the heavily doped and lightly doped regions. The second well is disposed in the substrate over the lightly doped region. A location of the first well overlaps a location of the second well. The first and the second doped regions are located in the second well within the active region, and spaced apart from each other. The first and the second doped regions have a same conductive type complementary to a conductive type of the second well.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsi-Yu Kuo, Yu-Lin Chu
  • Patent number: 10686098
    Abstract: A nitride semiconductor light emitting element includes: an n-side layer; a p-side layer; an active layer disposed between the n-side layer and the p-side layer, the active layer comprising: a well layer containing Al, Ga, and N, and a barrier layer containing Al, Ga, and N, wherein an Al content of the barrier layer is higher than an Al content of the well layer; and an electron blocking structure layer between the active layer and the p-side layer, the electron blocking structure comprising: a first electron blocking layer disposed between the p-side layer and the active layer, a second electron blocking layer disposed between the p-side layer and the first electron blocking layer, and an intermediate layer disposed between the first electron blocking layer and the second electron blocking layer.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: June 16, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Koji Asada, Tokutaro Okabe
  • Patent number: 10677860
    Abstract: A magnetic sensor includes a magnetoresistive body that is disposed over a surface of an insulator, a protective film that is provided over a surface of the insulator, including over the magnetoresistive body, and an open portion that runs along at least a portion of a perimeter of the magnetoresistive body and penetrates the protective film in a thickness direction of the protective film. In the magnetic sensor, a separation distance between an inside wall of the open portion and the magnetoresistive body, this being a minimum distance with respect to the magnetoresistive body, is configured so as to be longer than an alignment margin dimension of the open portion with respect to the magnetoresistive body.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: June 9, 2020
    Assignee: KABUSHIKI KAISHA TOKAI-RIKA-DENKI-SEISAKUSHO
    Inventor: Yoichi Ishizaki