Patents Examined by Bilkis Jahan
  • Patent number: 11955544
    Abstract: A semiconductor device includes a semiconductor layer that has a transistor structure including a p type source region, a p type drain region, an n type body region between the p type source region and the p type drain region, and a gate electrode facing the n type body region and a voltage-regulator diode that is disposed at the semiconductor layer and that has an n type portion connected to the p type source region and a p type portion connected to the gate electrode, in which the transistor structure and the voltage-regulator diode are unified into a single-chip configuration.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: April 9, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Kentaro Nasu
  • Patent number: 11955445
    Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: April 9, 2024
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Guilian Gao, Bongsub Lee, Gaius Gillman Fountain, Jr., Cyprian Emeka Uzoh, Laura Wills Mirkarimi, Belgacem Haba, Rajesh Katkar
  • Patent number: 11957001
    Abstract: A bank has an opening including a first opening and a second opening. The second opening extends from the first opening in such a direction that the second opening overlaps the first electrode. The second opening at least partially overlaps the first electrode. The first electrode has an end close to the first opening and overlapping the second opening. The second opening has a maximum width smaller than a maximum width of the first opening. The widths are measured perpendicular to the direction in which the second opening extends from the first opening.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: April 9, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Youhei Nakanishi, Shota Okamoto
  • Patent number: 11948966
    Abstract: In an embodiment a radiation emitting semiconductor chip includes a semiconductor layer sequence with a plurality of active regions and a main extension plane, wherein each active region has a main extension direction, wherein each active region is configured to emit electromagnetic radiation from an emitter region extending parallel to the main extension plane, wherein at least two active regions overlap in plan view, wherein the emitter regions are arranged at grid points of a regular grid connected by at least one grid line, and wherein the main extension direction of at least one active region encloses an angle of at least 10° and at most 80° with the grid lines of the regular grid.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: April 2, 2024
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Tansen Varghese, Bruno Jentzsch
  • Patent number: 11942536
    Abstract: Systems and methods for manufacturing two-dimensional (2D) gas channel for vertical transistors. The system can include a semiconductor device. The semiconductor device can include a channel structure surrounding a first dielectric core. The channel structure can include a first two-dimensional (2D) material and a second 2D material. The semiconductor device can include a source metal surrounding a first portion of the channel structure. The semiconductor device can include a drain metal surrounding a second portion of the channel structure. The semiconductor device can include a gate metal surrounding a third portion of the channel structure.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: March 26, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Robert D. Clark, H. Jim Fulford, Mark I. Gardner
  • Patent number: 11942471
    Abstract: A semiconductor chip includes a first electrode connected to a gate of a power device, a second electrode connected to an emitter or a source of the power device, a third electrode, and a gate protection element. The gate protection element includes a first node and a second node, and a plurality of stages of p-n junctions formed between the first node and the second node. When one of the first electrode and the second electrode is a target electrode and the other is a non-target electrode, and the first node is connected to the third electrode and the second node is connected to the target electrode. Then, the first electrode, the second electrode, the third electrode and the gate protection element are formed in the same semiconductor chip.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: March 26, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshito Tanaka, Hideaki Hashimoto
  • Patent number: 11944016
    Abstract: A magnetoresistive random access memory, including a substrate, a conductive plug in the substrate, wherein the conductive plug has a notched portion on one side of the upper edge of the conductive plug, and a magnetic memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction on the bottom electrode and a top electrode on the magnetic tunnel junction, wherein the bottom surface of the magnetic memory cell and the top surface of the conductive plug completely align and overlap each other.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: March 26, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hung-Chan Lin, Yu-Ping Wang, Hung-Yueh Chen
  • Patent number: 11942378
    Abstract: Techniques related to III-N transistors having improved performance, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include first and second crystalline III-N material layers separated by an intervening layer other than a III-N material such that the first crystalline III-N material layer has a first crystal orientation that is inverted with respect to a second crystal orientation of the second crystalline III-N material layer.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: March 26, 2024
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
  • Patent number: 11942560
    Abstract: A semiconductor device structure and a method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, a first electrode and a second electrode. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The third nitride semiconductor layer is disposed on the second nitride semiconductor layer. The first electrode is disposed on the second nitride semiconductor layer and spaced apart from the third nitride semiconductor layer. The second electrode covers an upper surface of the third nitride semiconductor layer and is in direct contact with the first nitride semiconductor layer.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: March 26, 2024
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventor: Anbang Zhang
  • Patent number: 11935943
    Abstract: A method of manufacturing a semiconductor device, the method including: forming, in a first region of a substrate, an active fin and a sacrificial gate structure intersecting the active fin; forming a first spacer and a second spacer on the substrate to cover the sacrificial gate structure; forming a mask in a second region of the substrate to expose the first region of the substrate; removing the second spacer from the first spacer in the first region of the substrate by using the mask; forming recesses at opposite sides of the sacrificial gate structure by removing portions of the active fin; forming a source and a drain in the recesses; and forming an etch-stop layer to cover both sidewalls of the sacrificial gate structure and a top surfaces of the source and drain.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: March 19, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun Kwan Yu, Seung Hun Lee, Yang Xu
  • Patent number: 11935885
    Abstract: A device includes standard cells in a layout of an integrated circuit. The standard cells include a first standard cell and a second standard cell disposed next to each other. The first standard cell is configured to operate as an electrostatic discharge (ESD) protection circuit and includes a first gate and a second gate. The first gate includes a first gate finger and a second gate finger that are arranged over a first active region, for forming a first transistor and a second transistor, respectively. The second gate is separate from the first gate. The second gate includes a third gate finger and a fourth gate finger that are arranged over a second active region, for forming a third transistor and a fourth transistor, respectively. The first transistor and the second transistor are connected in parallel, and the third transistor and the fourth transistor are connected in parallel.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzu-Heng Chang, Kuo-Ji Chen, Ming-Hsiang Song
  • Patent number: 11929305
    Abstract: In a method for manufacturing an electrostatic discharge protection circuit, an electrostatic discharge device structure is formed during a front side processing of a semiconductor substrate in a first area. Contact pads are formed on the front side on the electrostatic discharge device structure and in a second area. During back side processing of the semiconductor substrate, a metal connection between the first electrostatic discharge device structure and the second area is formed.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: March 12, 2024
    Assignee: Infineon Technologies AG
    Inventors: Andre Schmenn, Klaus Diefenbeck, Joost Adriaan Willemen
  • Patent number: 11923305
    Abstract: Some embodiments include an apparatus having a structure with a surface which comprises tungsten. The apparatus has titanium-nitride-containing protective material along and directly against the surface. The structure may be a digit line of a memory array. Some embodiments include a method in which an assembly is formed to have a tungsten-containing layer with an exposed tungsten-containing upper surface. Titanium-nitride-containing protective material is formed over and directly against the tungsten-containing upper surface. Additional material is formed over the protective material, and is spaced from the tungsten-containing upper surface by the protective material. The additional material may comprise silicon nitride and/or silicon dioxide.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: March 5, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Luca Fumagalli, Davide Colombo
  • Patent number: 11923449
    Abstract: A manufacturing method for a semiconductor device is provided. The method includes: forming a recess at a top surface of a substrate; forming a channel layer and a barrier layer in order, to conformally cover surfaces of the recess; filling up the recess with a conductive material; removing a top portion of the conductive material, such that a lower portion of the conductive material remained in the recess forms a gate electrode; and forming an insulating structure on the gate electrode. A hetero junction formed at an interface of the channel layer and the barrier layer is external to the substrate, and a two dimensional electron gas or a two dimensional hole gas is induced along the hetero junction external to the substrate.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: March 5, 2024
    Assignee: Winbond Electronics Corp.
    Inventors: Hao-Chuan Chang, Kai Jen
  • Patent number: 11925012
    Abstract: A method for forming a capacitor array structure includes the following steps: providing a substrate, a capacitor contact being exposed on a surface of the substrate, and the substrate including an array region and a peripheral region; forming a bottom supporting layer covering the substrate and the capacitor contact, the bottom supporting layer having a gap therein; forming a filling layer filling the gap and covering the capacitor contact and the surface of the bottom supporting layer, a thickness of the filling layer located at the peripheral region being larger than that of the filling layer located at the array region; forming supporting layers and sacrificial layers alternately stacked in a direction perpendicular to the substrate; forming a capacitor hole; sequentially forming a lower electrode layer on an inner wall of the capacitor hole.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: March 5, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Chaojun Sheng, Wenjia Hu
  • Patent number: 11917819
    Abstract: A three-dimensional semiconductor memory device may include a first stack block including first stacks arranged in a first direction on a substrate, a second stack block including second stacks arranged in the first direction on the substrate, and a separation structure provided on the substrate between the first stack block and the second stack block. The separation structure may include first mold layers and second mold layers, which are stacked in a vertical direction perpendicular to a top surface of the substrate.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: February 27, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junhyoung Kim, Kwang-Soo Kim, Geunwon Lim, Jisung Cheon
  • Patent number: 11908859
    Abstract: A semiconductor device includes a first to sixth regions, a first gate, a first metal contact and a second metal contact. The second region is disposed opposite to the first region with respect to the first gate. The first metal contact couples the first region to the second region. The fourth region is disposed opposite to the third region with respect to the first gate. The second metal contact is coupling the third region to the fourth region. The fifth region is disposed between the first gate and the second region, and is disconnected from the first metal contact and the second metal contact. The sixth region is disposed between the first gate and the first region, and is disconnected from the first metal contact and the second metal contact.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Feng Chang, Po-Lin Peng, Jam-Wem Lee
  • Patent number: 11908735
    Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Jen Chang, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
  • Patent number: 11908783
    Abstract: Provided is a wiring substrate and its manufacturing method in which a thick wiring layer capable of being applied with a large current and a thin wiring layer capable of being subjected to microfabrication coexist in the same layer. The wiring substrate includes: an insulating film located over a first wiring and having a via; and a second wiring over the insulating film. The second wiring has a stacked structure including a first layer and a second layer covering the first layer. The second layer is in direct contact with the first wiring in the via. A thickness of the second layer in a region overlapping with the first layer is different from a thickness of the second layer in the via.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: February 20, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventor: Naoki Hayashi
  • Patent number: 11908817
    Abstract: A method includes polishing a semiconductor substrate of a first die to reveal first through-vias that extend into the semiconductor substrate, forming a dielectric layer on the semiconductor substrate, and forming a plurality of bond pads in the dielectric layer. The plurality of bond pads include active bond pads and dummy bond pads. The active bond pads are electrically coupled to the first through-vias. The first die is bonded to a second die, and both of the active bond pads and the dummy bond pads are bonded to corresponding bond pads in the second die.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Chih-Chia Hu