Abstract: A semiconductor device includes at least a first lateral MOSFET formed on a semiconductor substrate. The first lateral MOSFET has an interface defined by a plurality of trenches along which the current flow can be modulated by a perpendicular electric field. The portion of the interface lies on a plane substantially perpendicular to the plane of the substrate. The interface is configured such that at least a portion of the current flow along the portion of the interface that lies on a plane substantially perpendicular to the plane of the substrate is in a direction substantially parallel to the plane of the substrate.

Abstract: A semiconductor integrated circuit including: a substrate of a first conductivity type; a buried insulating film provided on the substrate; an active layer of the first conductivity type provided on the buried insulating film; a first impurity region of a second conductivity type formed within the active layer; an electric field relaxation layer of the second conductivity type formed within the active layer and surrounding the first impurity region; a second impurity region of the first conductivity type formed within the active layer and surrounding the electric field relaxation layer; and a groove formed surrounding the second impurity region and reaching the buried insulating film.

Abstract: A product includes a semiconductor substrate, with at least first and second thin-film layers disposed on the substrate and patterned to define a matrix of dies, which are separated by scribe lines and contain active areas circumscribed by the scribe lines. A plurality of overlay targets are formed in the first and second thin-film layers within each of the active areas, each overlay target having dimensions no greater than 10 ?m×10 ?m in a plane parallel to the substrate. The plurality of overlay targets include a first linear grating formed in the first thin-film layer and having a first grating vector, and a second linear grating formed in the second thin-film layer, in proximity to the first linear grating, and having a second grating vector parallel to the first grating vector.

Abstract: An array substrate and a display panel. The array substrate provided in the embodiments of the present application includes: a base including a flat portion and a recess portion so that the base includes a concave hole corresponding to the bending area; a semiconductor component layer provided on the base and including a plurality of interlayer insulation layers and a plurality of metal layers, the interlayer insulation layers being not aligned horizontally in the peripheral area and the wire switching area to form a stepped hole including a first hole and a second hole, wherein a third metal layer of the metal layers extends along a sidewall and a bottom of the stepped hole and is electrically connected to a first metal layer of the metal layers.

Abstract: A high voltage device is used as a lower switch in a power stage of a switching regulator. The high voltage device includes at least one lateral diffused metal oxide semiconductor (LDMOS) device, a first isolation region, a second isolation region, a third isolation region, and a current limiting device. The first isolation region is located in a semiconductor layer, and encloses the LDMOS device. The second isolation region has a first conductivity type, and encloses the first isolation region in the semiconductor layer. The third isolation region has a second conductivity type, and encloses the second isolation region in the semiconductor layer. The current limiting device is electrically connected to the second isolation region, and is configured to operably suppress a parasitic silicon controlled rectifier (SCR) from being turned on.

Abstract: A display substrate, including: a first film layer arranged on a side of a base substrate, a second film layer arranged on a side of the first film layer away from the base substrate and an adhesive material portion arranged therebetween; wherein the first film layer has a first surface and a second surface respectfully facing the second film layer and the first film layer, and the first surface is at least partially in contact with the second surface; the adhesive material portion is arranged at least partially in a non-flat contact area formed between the first film layer and the second film layer, to adhere the first film layer and the second film layer; an adhesion between the adhesive material portion and each of the first film layer and the second film layer is greater than an adhesion between the first film layer and the second film layer.

Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

Abstract: A semiconductor device includes a semiconductor layer that has a transistor structure including a p type source region, a p type drain region, an n type body region between the p type source region and the p type drain region, and a gate electrode facing the n type body region and a voltage-regulator diode that is disposed at the semiconductor layer and that has an n type portion connected to the p type source region and a p type portion connected to the gate electrode, in which the transistor structure and the voltage-regulator diode are unified into a single-chip configuration.

Abstract: A bank has an opening including a first opening and a second opening. The second opening extends from the first opening in such a direction that the second opening overlaps the first electrode. The second opening at least partially overlaps the first electrode. The first electrode has an end close to the first opening and overlapping the second opening. The second opening has a maximum width smaller than a maximum width of the first opening. The widths are measured perpendicular to the direction in which the second opening extends from the first opening.

Abstract: In an embodiment a radiation emitting semiconductor chip includes a semiconductor layer sequence with a plurality of active regions and a main extension plane, wherein each active region has a main extension direction, wherein each active region is configured to emit electromagnetic radiation from an emitter region extending parallel to the main extension plane, wherein at least two active regions overlap in plan view, wherein the emitter regions are arranged at grid points of a regular grid connected by at least one grid line, and wherein the main extension direction of at least one active region encloses an angle of at least 10° and at most 80° with the grid lines of the regular grid.

Abstract: A semiconductor device structure and a method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, a first electrode and a second electrode. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The third nitride semiconductor layer is disposed on the second nitride semiconductor layer. The first electrode is disposed on the second nitride semiconductor layer and spaced apart from the third nitride semiconductor layer. The second electrode covers an upper surface of the third nitride semiconductor layer and is in direct contact with the first nitride semiconductor layer.

Abstract: Techniques related to III-N transistors having improved performance, systems incorporating such transistors, and methods for forming them are discussed. Such transistors include first and second crystalline III-N material layers separated by an intervening layer other than a III-N material such that the first crystalline III-N material layer has a first crystal orientation that is inverted with respect to a second crystal orientation of the second crystalline III-N material layer.

Abstract: A semiconductor chip includes a first electrode connected to a gate of a power device, a second electrode connected to an emitter or a source of the power device, a third electrode, and a gate protection element. The gate protection element includes a first node and a second node, and a plurality of stages of p-n junctions formed between the first node and the second node. When one of the first electrode and the second electrode is a target electrode and the other is a non-target electrode, and the first node is connected to the third electrode and the second node is connected to the target electrode. Then, the first electrode, the second electrode, the third electrode and the gate protection element are formed in the same semiconductor chip.

Abstract: Systems and methods for manufacturing two-dimensional (2D) gas channel for vertical transistors. The system can include a semiconductor device. The semiconductor device can include a channel structure surrounding a first dielectric core. The channel structure can include a first two-dimensional (2D) material and a second 2D material. The semiconductor device can include a source metal surrounding a first portion of the channel structure. The semiconductor device can include a drain metal surrounding a second portion of the channel structure. The semiconductor device can include a gate metal surrounding a third portion of the channel structure.

Abstract: A magnetoresistive random access memory, including a substrate, a conductive plug in the substrate, wherein the conductive plug has a notched portion on one side of the upper edge of the conductive plug, and a magnetic memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction on the bottom electrode and a top electrode on the magnetic tunnel junction, wherein the bottom surface of the magnetic memory cell and the top surface of the conductive plug completely align and overlap each other.

Abstract: A device includes standard cells in a layout of an integrated circuit. The standard cells include a first standard cell and a second standard cell disposed next to each other. The first standard cell is configured to operate as an electrostatic discharge (ESD) protection circuit and includes a first gate and a second gate. The first gate includes a first gate finger and a second gate finger that are arranged over a first active region, for forming a first transistor and a second transistor, respectively. The second gate is separate from the first gate. The second gate includes a third gate finger and a fourth gate finger that are arranged over a second active region, for forming a third transistor and a fourth transistor, respectively. The first transistor and the second transistor are connected in parallel, and the third transistor and the fourth transistor are connected in parallel.

Abstract: A method of manufacturing a semiconductor device, the method including: forming, in a first region of a substrate, an active fin and a sacrificial gate structure intersecting the active fin; forming a first spacer and a second spacer on the substrate to cover the sacrificial gate structure; forming a mask in a second region of the substrate to expose the first region of the substrate; removing the second spacer from the first spacer in the first region of the substrate by using the mask; forming recesses at opposite sides of the sacrificial gate structure by removing portions of the active fin; forming a source and a drain in the recesses; and forming an etch-stop layer to cover both sidewalls of the sacrificial gate structure and a top surfaces of the source and drain.

Abstract: In a method for manufacturing an electrostatic discharge protection circuit, an electrostatic discharge device structure is formed during a front side processing of a semiconductor substrate in a first area. Contact pads are formed on the front side on the electrostatic discharge device structure and in a second area. During back side processing of the semiconductor substrate, a metal connection between the first electrostatic discharge device structure and the second area is formed.

Abstract: A method for forming a capacitor array structure includes the following steps: providing a substrate, a capacitor contact being exposed on a surface of the substrate, and the substrate including an array region and a peripheral region; forming a bottom supporting layer covering the substrate and the capacitor contact, the bottom supporting layer having a gap therein; forming a filling layer filling the gap and covering the capacitor contact and the surface of the bottom supporting layer, a thickness of the filling layer located at the peripheral region being larger than that of the filling layer located at the array region; forming supporting layers and sacrificial layers alternately stacked in a direction perpendicular to the substrate; forming a capacitor hole; sequentially forming a lower electrode layer on an inner wall of the capacitor hole.

Abstract: A manufacturing method for a semiconductor device is provided. The method includes: forming a recess at a top surface of a substrate; forming a channel layer and a barrier layer in order, to conformally cover surfaces of the recess; filling up the recess with a conductive material; removing a top portion of the conductive material, such that a lower portion of the conductive material remained in the recess forms a gate electrode; and forming an insulating structure on the gate electrode. A hetero junction formed at an interface of the channel layer and the barrier layer is external to the substrate, and a two dimensional electron gas or a two dimensional hole gas is induced along the hetero junction external to the substrate.