Abstract: A micro-light-emitting diode (microLED) display panel includes a substrate; a plurality of microLEDs disposed and arranged in rows and columns on the substrate; a driver disposed on the substrate; a plurality of first blocking walls respectively disposed between rows of the microLEDs; and a plurality of second blocking walls respectively disposed between the microLEDs of the same row.

Abstract: A first chip comprises a first set of one or more metal layers having a first thickness and comprising at least one metal layer that has a first CTE. A first volume of the first chip is adjacent to the first set of one or more metal layers. A second volume of the first chip comprises one or more electronic or photonic structures, and a second set of one or more metal layers that has a second thickness at least twice as large as the first thickness. At least one metal layer in the second set has a second CTE. A set of one or more metal structures of the first chip is adjacent to the second volume and comprises at least one metal structure electrically connected to at least a portion of at least one metal layer in the second set of one or more metal layers.

Abstract: The present disclosure provides a transistor, a method for configuring the same, an electrostatic discharge (ESD) protection circuit, and an electronic device for ESD protection. The transistor comprises a P-type well, a body terminal region, a source region, and a metal silicide layer. The body terminal region and the source region are disposed within the P-type well. The body terminal region is adjacent to the source region. The metal silicide layer is disposed on surfaces of the body terminal region and the source region, and electrically connected to the body terminal region and the source region separately. A metal and contact structures are provided on the metal silicide layer to adjust the resistance between the emitter of the parasitic bipolar transistor of the transistor and the body terminal region or between the base of the parasitic bipolar transistor and the source region, for ESD protection.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.

Abstract: An organic electroluminescence module, an encapsulating method, and a display device are provided. The organic electroluminescence module includes a substrate, an organic electroluminescent device disposed on the substrate, a first encapsulation layer disposed on a side of the organic electroluminescent device away from the substrate, and a second encapsulation layer disposed on a side of the first encapsulation layer away from the substrate. The first encapsulation layer is capable of preventing a gas generated by the second encapsulation layer from entering the organic electroluminescent device.

Abstract: A semiconductor device includes a semiconductor substrate having first and second regions therein, a first lower semiconductor pattern, which protrudes from the semiconductor substrate in the first region and extends in a first direction across the semiconductor substrate, and a first gate electrode, which extends across the first lower semiconductor pattern and the semiconductor substrate in a second direction. A plurality of semiconductor sheet patterns are provided, which are spaced apart from each other in a third direction to thereby define a vertical stack of semiconductor sheet patterns, on the first lower semiconductor pattern. A first gate insulating film is provided, which separates the plurality of semiconductor sheet patterns from the first gate electrode. A second lower semiconductor pattern is provided, which protrudes from the semiconductor substrate in the second region. A plurality of wire patterns are provided, which are spaced apart from each other on the second lower semiconductor pattern.

Abstract: Disclosed are a display substrate and a preparation method thereof, and a display apparatus. The display substrate includes a substrate and a plurality of sub-pixels, at least one sub-pixel includes a pixel drive circuit and a light emitting device connected to the pixel drive circuit, the pixel drive circuit includes a plurality of transistors, wherein at least one transistor includes an active layer and two gate electrodes. The substrate is provided with a semiconductor layer and a plurality of conductive layers disposed on one side of the semiconductor layer away from the substrate, at least one conductive layer is provided with at least one electrode plate, and there is an overlapping region between an orthographic projection of the electrode plate on the substrate and an orthographic projection of the active layer between the two gate electrodes on the substrate.

Abstract: The present disclosure provides a semiconductor structure and substrate thereof, and a method for manufacturing the same. In the method for manufacturing the substrate, at least one of groove is provided in each unit sub-region on a surface of a premanufactured substrate, and the premanufactured substrate includes at least one unit region, each of the at least one unit region includes at least two unit sub-regions; in one of the at least one unit region, the at least two unit sub-regions respectively have different porosities, the premanufactured substrate is annealed to form a substrate, wherein openings of the grooves are healed to form self-healing layers, and the grooves that are not fully healed form gaps. When a susceptor transfers heat to the substrate, the unit sub-regions with different porosities respectively have different heat conduction efficiencies.

Abstract: A display device may include a display area including pixel areas each including an emission area, a non-display area, and a pixel disposed in each of the pixel areas. The pixel may include a first electrode, a second electrode spaced apart from the first electrode and surrounding a periphery of the first electrode, a third electrode spaced apart from the second electrode and surrounding a periphery of the second electrode, a fourth electrode spaced apart from the third electrode and surrounding a periphery of the third electrode, light emitting elements disposed between the first to fourth electrodes, and first and second conductive lines disposed under the first to fourth electrodes with an insulating layer disposed therebetween. The first conductive line may be electrically connected to the first electrode, and the second conductive line may be electrically connected to the fourth electrode.

Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a gate structure disposed on the semiconductor substrate, a first well region of a first conductivity type disposed in the semiconductor substrate, a first doped region of the first conductivity type, a second doped region of a second conductivity type, a third doped region of the first conductivity type, and a fourth doped region of the second conductivity type. The first and second doped regions are disposed in the first well region and connected with each other. The second doped region is an emitter of a first bipolar junction transistor. The third and fourth doped regions are disposed in the semiconductor substrate and connected with each other. The third and second doped regions are located at two opposite sides of the gate structure in a first horizontal direction. The third doped region is an emitter of a second bipolar junction transistor.

Abstract: A number of Monolithic Microwave Integrated Circuit (MMIC) devices including combinations of PIN and Schottky diodes, with integrated passive electrical components fabricated and electrically connected among them, are described herein, along with new process techniques for forming the MMIC devices. In one example, a monolithic semiconductor includes a substrate, a plurality of layers of semiconductor materials over the substrate, Schottky and Ohmic contacts on a first subset of the plurality of layers for a Schottky diode, and PIN diode Ohmic contacts on a second subset of the plurality of layers for a PIN diode. The device can also include an etch stop layer between the first subset of the plurality of layers and the second subset of the plurality of layers. The etch stop layer facilitates selective etching and isolation of the Schottky diode from the PIN diode by consecutive etchings.

Abstract: The present invention relates to an LDMOS device and a method of forming the device, in which a barrier layer includes n etch stop layers. Insulating layers are formed between adjacent etch stop layers. Since an interlayer dielectric layer and the insulating layers are both oxides that differ from the material of the etch stop layers, etching processes can be stopped at the n etch stop layers when they are proceeding in the oxides, thus forming n field plate holes terminating at the respective n etch stop layers. A lower end of the first field plate hole proximal to a gate structure is closest to a drift region, and a lower end of the n-th field plate hole proximal to a drain region is farthest from the drift region. With this arrangement, more uniform electric field strength can be obtained around front and rear ends of the drift region, resulting in an effectively improved electric field distribution throughout the drift region and thus in an increased breakdown voltage.

Abstract: Methods are disclosed for forming fins in transistors. In one embodiment, a method of fabricating a device includes forming silicon fins on a substrate and forming a dielectric layer on the substrate and adjacent to the silicon fins such that an upper region of each silicon fin is exposed. Germanium may then be epitaxially grown germanium on the upper regions of the silicon fins to form germanium fins.

Abstract: A method of manufacturing an optoelectronic device including-light-emitting diodes comprising the forming of three-dimensional semiconductor elements made of a III-V compound, each comprising a lower portion and an upper portion and, for each semiconductor element, the forming of an active area covering the top of the upper portion and the forming of at least one semiconductor area of the III-V compound covering the active area. The upper portions are formed by vapor deposition at a pressure lower than 1.33 mPa.

Abstract: The present disclosure discloses a display panel and a display device. The display panel comprises a driving chip and fan-out wires. Fan-out wires in a first fan-out wire group are electrically connected to corresponding output terminals through a second side of an adjacent driving chip; each of the fan-out wires in the first fan-out wire group comprises a first fan-out section and a second fan-out section that are connected and located on different layers. The present disclosure adopts a wire-changing jumper design to prevent signal disorder caused by inconsistent orders of the output terminals and the fan-out wires.

Abstract: A doping concentration distribution in an accumulation region in a depth direction of a semiconductor substrate has a maximum portion at which a doping concentration reaches a maximum value, an upper gradient portion in which the concentration decreases from the maximum portion to a base region, a lower gradient portion in which the concentration decreases from the maximum portion to a drift region, and a kink portion at which a differential value of the doping concentration distribution exhibits an extreme value in a region except a region in which the differential value exhibits a maximum value or a minimum value.

Abstract: A fabrication method of a display panel and a drying device are provided by the present application. In the display panel of the present application, an electrical field for drying on a pixel electrode layer is used to fix charged groups in a solution of a light-emitting functional layer, which prevents a solvent from driving the movement of the charged groups when the solvent is volatilized, thereby obtaining a light-emitting functional layer with a uniform film thickness. Moreover, the use of the electric field for drying fixes the charged groups so that a drying treatment is performed without strict pumping control during the solvent volatilization process.

Abstract: Disclosed are a light emitting diode and a method for manufacturing a light emitting diode. The light emitting diode includes a first-type layer, a light emitting layer, a second-type layer and an electrode layer; the first-type layer includes a first-type gallium nitride; the light emitting layer is located on the first-type layer; the light emitting layer includes a quantum point; the second-type layer is located on the light emitting layer; the second-type layer includes a second-type gallium nitride or an indium tin oxide; and the electrode layer is located on the second-type layer.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similarly to the plurality of first memory cells.

Abstract: The present disclosure provides a method for manufacturing a semiconductor device and a semiconductor device. The method for manufacturing a semiconductor device includes: providing a substrate; forming a plurality of first structures extending in a first direction on the substrate; forming a sacrificial layer on sidewalls of the first structures; forming an outer spacer layer on a sidewall of the sacrificial layer; removing part of the outer spacer layer to obtain a patterned outer spacer layer that exposes part of the sacrificial layer; and removing the sacrificial layer to form air gaps between the patterned outer spacer layer and the first structures.