Patents Examined by Bilkis Jahan
  • Patent number: 11855088
    Abstract: A method includes the following operations: disconnecting at least one of drain regions that are formed on a first active area, of first transistors, from a first voltage; and disconnecting at least one of drain regions that are formed on a second active area, of second transistors coupled to the first transistors from a second voltage. The at least one of drain regions of the second transistors corresponds to the at least one of drain regions of the first transistors.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Feng Chang, Po-Lin Peng, Jam-Wem Lee
  • Patent number: 11848321
    Abstract: A semiconductor device is provided. The semiconductor device comprises an output circuit configured to be electrically connected between a driving circuit and an external load circuit, and a protection circuit electrically connected to the output circuit and the driving circuit. The protection circuit comprises a first transistor having a base electrode, a collector electrode and an emitter electrode and a second transistor having a base electrode, a collector electrode and an emitter electrode. The base electrode of the first transistor is electrically connected to the collector electrode of the second transistor.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hong-Shyang Wu, Kuo-Ming Wu
  • Patent number: 11837599
    Abstract: A semiconductor device includes an electrostatic protection circuit 1 and a MOSFET 2 including a gate terminal. The electrostatic protection circuit 1 includes a positive-side power supply terminal 3, a negative-side power supply terminal 5, a first protection diode 4, a second protection diode 6, a resistance element 7, and a bipolar transistor 8. The second protection diode 6 includes an anode terminal electrically connected to the negative-side power supply terminal 5 via the resistance element 7, and a cathode terminal electrically connected to the gate terminal. The bipolar transistor 8 includes a base terminal, an emitter terminal, and a collector terminal. The bipolar transistor 8 is electrically connected to the anode terminal of the second protection diode 6, the gate terminal, and the positive-side power supply terminal 3. The electrostatic protection circuit 1 is formed on a semiconductor substrate made of silicon carbide.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: December 5, 2023
    Assignee: HITACHI, LTD.
    Inventors: Masahiro Masunaga, Shinji Nomoto, Ryo Kuwana, Isao Hara
  • Patent number: 11837646
    Abstract: A device includes a substrate including a low-resistance top surface and a fin structure including a first fin and a second fin. Each of the first and second fins includes a low-resistance fin-top surface and two low-resistance sidewall surfaces. The device includes an insulation material over the top surface of the substrate and between the first fin and the second fin. The fin-top surface and a first portion of the sidewall surfaces of each of the first and the second fins are above the insulation material. The device further includes a dielectric layer over the insulation material and in direct contact with the fin-top surface and the first portion of the sidewall surfaces of each of the first and the second fins; a first electrode in direct contact with the fin-top surface of the first fin; and a second electrode over the dielectric layer that is over the second fin.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 11837684
    Abstract: Submount structures for light-emitting diode (LED) packages are provided. Submounts may include a base material that is configured to provide high thermal conductivity and a ceramic layer on the base material that is configured to provide high reflectivity for one or more LED chips that are mounted thereon. In certain aspects, the base material may include a ceramic base having a ceramic material that is different than a material of the ceramic layer. In certain aspects, submounts may also include additional ceramic layers configured to provide high reflectivity. In certain aspects, LED packages include electrical traces that are arranged either on one or more ceramic layers or at least partially embedded within one or more ceramic layers. The arrangement of such ceramic layers may provide increased reflectivity in areas where it may be difficult for other reflective materials to be present, such as gaps formed between tightly spaced electrical traces.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: December 5, 2023
    Assignee: CreeLED, Inc.
    Inventors: David Suich, Daniel E. Stasiw, Samuel Richard Harrell, Jr.
  • Patent number: 11817457
    Abstract: Disclosed is a reconfigurable complementary metal oxide semiconductor (CMOS) device with multiple operating modes (e.g., frequency multiplication mode, etc.). The device includes an N-type field effect transistor (NFET) and a P-type field effect transistor (PFET), which are threshold voltage-programmable, which are connected in parallel, and which have electrically connected gates. The threshold voltages of the NFET and PFET can be concurrently programmed and the operating mode of the device can be set depending upon the specific combination of threshold voltages achieved in the NFET and PFET. Optionally, the threshold voltages of the NFET and PFET can be concurrently reprogrammed to switch the operating mode. Such a device is relatively small and achieves frequency multiplication and other functions with minimal power consumption. Also disclosed are methods for forming the device and for reconfiguring the device (i.e., for concurrently programming the NFET and PFET to set or switch operating modes).
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: November 14, 2023
    Assignee: GlobalFoundries Dresden Module One Limited Liability Company & Co. KG
    Inventors: Stefan D√ľnkel, Dominik M. Kleimaier
  • Patent number: 11804524
    Abstract: A Metal Oxide Semiconductor (MOS) cell design has traditional planar cells extending in a first dimension, and trenches with their length extending in a third dimension, orthogonal to the first dimension in a top view. The manufacturing process includes forming a horizontal channel, and a plurality of trenches discontinued in the planar cell regions. Horizontal planar channels are formed in the mesa of the orthogonal trenches. A series connected horizontal planar channel and a vertical trench channel are formed along the trench regions surrounded by the first base. The lack of a traditional vertical channel is important to avoid significant reliability issues (shifts in threshold voltage Vth). The planar cell design offers a range of advantages both in terms of performance and processability. Manufacture of the planar cell is based on a self-aligned process with minimum number of masks, with the potential of applying additional layers or structures.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: October 31, 2023
    Assignee: MQSEMI AG
    Inventors: Munaf Rahimo, Iulian Nistor
  • Patent number: 11804549
    Abstract: An integrated circuit device includes a device isolation trench defining an active area, a gate trench extending in a first direction across the active area and the device isolation film, a gate dielectric film covering an inner wall of the gate trench, and a conductive line filling a part of the gate trench above the gate dielectric film. The active area includes a fin body portion located under the conductive line, and a thinner fin portion protruding from the fin body portion toward the conductive line and having a width less than a width of the fin body portion in the first direction.
    Type: Grant
    Filed: December 16, 2022
    Date of Patent: October 31, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-seung Lee, Yun-seung Kang, Soung-hee Lee, Sang-gyo Chung, Hyun-chul Lee
  • Patent number: 11804481
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure (ESD device) includes: a bipolar transistor comprising a collector region, an emitter region and a base region; and a lateral ballasting resistance comprising semiconductor material adjacent to the collector region.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: October 31, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Robert J. Gauthier, Jr., Meng Miao, Alain F. Loiseau, Souvick Mitra, You Li, Wei Liang
  • Patent number: 11804446
    Abstract: Provided is a semiconductor device capable of improving the divisibility of a wafer by concentrating crack stress by disposing notch patterns on a scribe line of a wafer, by locally removing a metal thin film in a scribe line and propagating a dividing energy in a vertical direction of a die surface. A semiconductor device includes: die regions spaced apart from each other in a wafer, scribe line regions disposed between neighboring ones of the die regions and covered with a metal material layer, and one or more open areas disposed in each of the scribe line regions and formed by locally removing the metal material layer, wherein each of the open areas includes one or more notch patterns indicating a direction in which the scribe line region is extended.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: October 31, 2023
    Assignee: SK hynix Inc.
    Inventors: Hyung Jin Park, Jung Wook Kim, Hyo Jun Lee
  • Patent number: 11799027
    Abstract: A semiconductor device includes an active region which is surrounded by a device isolation region on a semiconductor substrate and which extends in a first direction; a silicon pillar which separates the active region along the first direction into a first lower diffusion layer and a second lower diffusion layer; a first gate electrode covering a first side face of the silicon pillar which is located on a side of the first lower diffusion layer; a second gate electrode covering a second side face of the silicon pillar which is located on a side of the second lower diffusion layer; a conductive layer provided on a top face of the silicon pillar; and a device isolation insulating film contacting with a third side face of the silicon pillar which is different from the first side face and the second side face.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: October 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Yuki Munetaka, Kazuo Ogawa
  • Patent number: 11798941
    Abstract: In in a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes a gate structure disposed over a channel region of a fin structure, and a first source/drain epitaxial layer disposed at a source/drain region of the fin structure. A first opening is formed over the first source/drain epitaxial layer by etching a part of the ILD layer and an upper portion of the first source/drain epitaxial layer. A second source/drain epitaxial layer is formed over the etched first source/drain epitaxial layer. A conductive material is formed over the second source/drain epitaxial layer.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: October 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yuan Lu, Sai-Hooi Yeong
  • Patent number: 11784050
    Abstract: A microelectronic device may have side surfaces each including a first portion and a second portion. The first portion may have a highly irregular surface topography extending from an adjacent surface of the microelectronic device. The second portion may have a less uneven surface extending from the first portion to an opposing surface of the microelectronic device. Methods of forming the microelectronic device may include creating dislocations in the wafer in a street between the one or more microelectronic devices by implanting ions and cleaving the wafer responsive to failure of stress concentrations near the dislocations through application of heat, tensile forces or a combination thereof. Related packages and methods are also disclosed.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: October 10, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Andrew M. Bayless, Brandon P. Wirz
  • Patent number: 11769758
    Abstract: A light emitting device includes a backplane, an array of light emitting diodes attached to a front side of the backplane, a transparent conductive layer contacting front side surfaces of the light emitting diodes, an optical bonding layer located over a front side surface of the transparent conductive layer, a transparent cover plate located over a front side surface of the optical bonding layer, and a black matrix layer including an array of openings therethrough, and located between the optical bonding layer and the transparent cover plate.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: September 26, 2023
    Assignee: NANOSYS, INC.
    Inventor: Brian Kim
  • Patent number: 11756791
    Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first, fourth, and sixth semiconductor regions of a first conductivity type, a junction region, a fifth semiconductor region of a second conductivity type, and a gate electrode. The junction region includes a second semiconductor region of the first conductivity type and a third second semiconductor region of the second conductivity type. The second semiconductor regions and the third semiconductor regions are alternately provided in a second direction perpendicular to a first direction. A concentration of at least one first element selected from the group consisting of a heavy metal element and a proton in the junction region is greater a concentration of the first element in the fourth semiconductor region, or a density of traps in the junction region is greater than that in the first semiconductor region and greater than that in the fourth semiconductor region.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: September 12, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Shingo Sato, Yuhki Fujino, Hiroaki Yamashita
  • Patent number: 11756954
    Abstract: A silicon carbide MOSFET device includes a gate pad area, a main MOSFET area and a secondary MOSFET area. A main source contact is electrically coupled to the source region of each of the main MOSFETs, and a separate secondary source contact is electrically coupled to the source region of each of the secondary MOSFETs. A gate contact electrically connects to each of the insulated gate members of the main and secondary MOSFETs. An asymmetric gate clamping circuit is coupled between the secondary source contact and the gate contact. In a first mode of operation of the MOSFET device the main source contact is electrically coupled with the secondary source contact to activate the gate clamping circuit. When activated, the circuit clamping a gate-to-source voltage to a first clamp voltage in an on-state of the MOSFET device, and to a second clamp voltage in an off-state of the MOSFET device.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: September 12, 2023
    Assignee: SEMIQ INCORPORATED
    Inventors: Rahul R. Potera, Carl A. Witt
  • Patent number: 11756921
    Abstract: A method includes determining a first offset between a first alignment mark on a first side of a first wafer and a second alignment mark on a second side of the first wafer; aligning the first alignment mark of the first wafer to a third alignment mark on a first side of a second wafer, which includes detecting a location of the second alignment mark of the first wafer; determining a location of the first alignment mark of the first wafer based on the first offset and the location of the second alignment mark of the first wafer; and, based on the determined location of the first alignment mark, repositioning the first wafer to align the first alignment mark to the third alignment mark; and bonding the first side of the first wafer to the first side of the second wafer to form a bonded structure.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: September 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Tai Chang, Tung Ying Lee
  • Patent number: 11749562
    Abstract: A method for depositing a film to form an air gap within a semiconductor device is disclosed. An exemplary method comprises pulsing a metal halide precursor onto the substrate and pulsing an oxygen precursor onto a selective deposition surface. The method can be used to form an air gap to, for example, reduce a parasitic resistance of the semiconductor device.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: September 5, 2023
    Assignee: ASM IP Holding B.V.
    Inventor: Chiyu Zhu
  • Patent number: 11735460
    Abstract: An integrated circuit device includes an engineered substrate including a substantially single crystal layer and a buffer layer coupled to the substantially single crystal layer. The integrated circuit device also includes a plurality of semiconductor devices coupled to the buffer layer. The plurality of semiconductor devices can include a first power device coupled to a first portion of the buffer layer and a second power device coupled to a second portion of the buffer layer. The first power device includes a first channel region comprising a first end, a second end, and a first central portion disposed between the first end and the second end. The second power device includes a second channel region comprising a third end, a fourth end, and a second central portion disposed between the third end and the fourth end.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: August 22, 2023
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Dilip Risbud, Ozgur Aktas, Cem Basceri
  • Patent number: 11732351
    Abstract: Described herein are conformal films and methods for forming a conformal metal or metalloid doped silicon nitride dielectric film wherein the conformal metal is zirconium, hafnium, titanium, tantalum, or tungsten. A method includes providing a substrate in a reactor; introducing into the reactor an at least one metal precursor which reacts; purging the reactor with a purge gas; introducing into the reactor an organoaminosilane precursors to react on at least a portion of the surface of the substrate to provide a chemisorbed layer; introducing a plasma comprising nitrogen and an inert gas into the reactor to react with at least a portion of the chemisorbed layer and provide at least one reactive site wherein the plasma is generated; and optionally purge the reactor with an inert gas; and the steps are repeated until a desired thickness of the conformal metal nitride film is obtained.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: August 22, 2023
    Assignee: Versum Materials US, LLC
    Inventors: Xinjian Lei, Moo-Sung Kim, Jianheng Li