Patents Examined by Bilkis Jahan
  • Patent number: 10916492
    Abstract: A semiconductor substrate and a method of manufacturing the same are provided. The semiconductor substrate includes a carrier and a conductive post. The carrier has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The carrier has a through hole extending between the first surface and the second surface. The carrier has a first opening on the lateral surface. The conductive post is disposed within the through hole.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: February 9, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tsann Huei Lee, Lu-Ming Lai
  • Patent number: 10916616
    Abstract: A display device includes a substrate including a display area and a peripheral area and being flexible around a bending axis in the peripheral area, a data line and a driving voltage line in the display area, an inorganic insulating layer defines an opening corresponding to the flexible area, a first and second conductive layers in the peripheral area and being spaced apart from each other around the opening, an organic insulating layer covering the first and second conductive layers, and a connection conductive layer connecting the first and second conductive layers via contact holes of the organic insulating layer, and the first and second conductive layers includes a same material as that of one of the data line and the driving voltage line, and the connection conductive layer includes a same material as that of the other of the data line and the driving voltage line.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: February 9, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Donghyun Lee, Deukjong Kim, Keunsoo Lee
  • Patent number: 10903129
    Abstract: An electronic device includes an electronic element, and a wire bonded to the electronic element. The electronic element includes a bonding pad to which the wire is bonded. The main component of the bonding pad is Al. A metal is mixed in the wire, and the mixed metal is one of Pt, Pd and Au.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: January 26, 2021
    Assignee: ROHM CO., LTD
    Inventors: Motoharu Haga, Kaoru Yasuda, Akinori Nii, Yuto Nishiyama
  • Patent number: 10903054
    Abstract: The present technology includes improved gas distribution designs for forming uniform plasmas during semiconductor processing operations or for treating the interior of semiconductor processing chambers. While conventional gas distribution assemblies may receive a specific reactant or reactant ratio which is then distributed into the plasma region, the presently described technology allows for improved control of the reactant input distribution. The technology allows for separate flows of reactants to different regions of the plasma to offset any irregularities observed in process uniformity. A first precursor may be delivered to the center of the plasma above the center of the substrate/pedestal while a second precursor may be delivered to an outer portion of the plasma above an outer portion of the substrate/pedestal. In so doing, a substrate residing on the pedestal may experience a more uniform etch or deposition profile across the entire surface.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: January 26, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Saravjeet Singh, Kenneth D. Schatz, Alan Tso, Marlin Wijekoon, Dimitri Kioussis
  • Patent number: 10892224
    Abstract: Some embodiments include an apparatus having a structure with a surface which comprises tungsten. The apparatus has titanium-nitride-containing protective material along and directly against the surface. The structure may be a digit line of a memory array. Some embodiments include a method in which an assembly is formed to have a tungsten-containing layer with an exposed tungsten-containing upper surface. Titanium-nitride-containing protective material is formed over and directly against the tungsten-containing upper surface. Additional material is formed over the protective material, and is spaced from the tungsten-containing upper surface by the protective material. The additional material may comprise silicon nitride and/or silicon dioxide.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Luca Fumagalli, Davide Colombo
  • Patent number: 10886395
    Abstract: A method for fabricating a tunnel field effect transistor (TFET) includes the steps of providing a substrate and then forming an interfacial layer on the substrate. Preferably, the step of forming the interfacial layer includes the steps of: performing a plasma treatment process to inject a first gas containing nitrogen; injecting a second gas containing oxygen; and injecting a precursor to react with the first gas and the second gas for forming the interfacial layer.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: January 5, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: An-Chi Liu, Chun-Hsien Lin
  • Patent number: 10883045
    Abstract: A method includes obtaining a potassium hexafluorosilicate (PFS)-based powder, obtaining a fluidization material, and mixing the PFS-based powder with the fluidization material to form a PFS-based mixture. The PFS-based mixture is configured to be mixed with a resinous material to form a flowing phosphor blend configured to be placed onto a light source to form a phosphor on the light source.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: January 5, 2021
    Assignee: CURRENT LIGHTING SOLUTIONS, LLC
    Inventors: William Winder Beers, Fangming Du, Clark David Nelson
  • Patent number: 10879233
    Abstract: A capacitive element is fabricated by forming a sacrificial trench isolation and directionally etching through the sacrificial trench isolation and into an underlying semiconductor substrate to form an electrode trench. The electrode trench is then clad with an insulating material and filled with a conductive material. The conductive fill provided one capacitor electrode and the semiconductor substrate forms another capacitor electrode, with the insulating material cladding forming the capacitor dielectric layer.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: December 29, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • Patent number: 10879251
    Abstract: An integrated circuit includes a substrate, a first isolation feature, and a plurality of memory cells. The substrate has a cell region, a peripheral region, and a transition region between the cell region and the peripheral region. A top surface of the cell region is lower than a top surface of the peripheral region, and the substrate includes at least one protrusion portion in the transition region. The first isolation feature is in the transition region and covers the protrusion portion of the substrate. The memory cells are over the cell region of the substrate.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Chin-Wen Chan, Chih-Ren Hsieh
  • Patent number: 10879398
    Abstract: An integrated circuit device includes a device isolation trench defining an active area, a gate trench extending in a first direction across the active area and the device isolation film, a gate dielectric film covering an inner wall of the gate trench, and a conductive line filling a part of the gate trench above the gate dielectric film. The active area includes a fin body portion located under the conductive line, and a thinner fin portion protruding from the fin body portion toward the conductive line and having a width less than a width of the fin body portion in the first direction.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: December 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-seung Lee, Yun-seung Kang, Soung-hee Lee, Sang-gyo Chung, Hyun-chul Lee
  • Patent number: 10868003
    Abstract: A semiconductor device includes first and second transistors each having a high-k metal gate disposed over a respective channel region of the transistors. The semiconductor device further includes first and second dielectric features in physical contact with an end of the respective high-k metal gates. The first and second transistors are of a same conductivity type. The two high-k metal gates have a same number of material layers. The first transistor's threshold voltage is different from the second transistor's threshold voltage, and at least one of following is true: the two high-k metal gates have different widths, the first and second dielectric features have different distances from respective channel regions of the two transistors, and the first and second dielectric features have different dimensions.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Chang Wen, Chang-Yun Chang, Hsien-Chin Lin, Bone-Fong Wu, Ya-Hsiu Lin
  • Patent number: 10865099
    Abstract: A MEMS device includes a first layer and a second layer including a same material, a third layer disposed between the first layer and the second layer, a first air gap separating the first layer and the third layer, a second air gap separating the second layer and the third layer, a plurality of first pillars exposed to the first air gap and arranged in contact with the first layer and the third layer, a plurality of second pillars exposed to the second air gap and arranged in contact with the second layer and the third layer.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen Hsiung Yang, Chun-Wen Cheng, Chia-Hua Chu, En-Chan Chen
  • Patent number: 10867929
    Abstract: A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tzuan-Horng Liu, Ming-Fa Chen, Chao-Wen Shih, Sung-Feng Yeh
  • Patent number: 10861999
    Abstract: A high efficiency configuration for a solar cell module comprises solar cells conductively bonded to each other in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: December 8, 2020
    Assignee: SunPower Corporation
    Inventors: Ratson Morad, Gilad Almogy, Itai Suez, Jean Hummel, Nathan Beckett, Yafu Lin, John Gannon, Michael J. Starkey, Robert Stuart, Tamir Lance, Dan Maydan
  • Patent number: 10861904
    Abstract: An imaging device includes at least one unit pixel cell including a photoelectric converter that converts incident light into electric charges. The photoelectric converter includes: a first electrode; a light-transmitting second electrode; a first photoelectric conversion layer disposed between the first electrode and the second electrode and containing a first material having an absorption peak at a first wavelength; and a second photoelectric conversion layer disposed between the first photoelectric conversion layer and the second electrode and containing a second material having an absorption peak at a second wavelength different from the first wavelength. The absolute value of the ionization potential of the first material is larger by at least 0.2 eV than the absolute value of the ionization potential of the second material.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: December 8, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Manabu Nakata, Masumi Izuchi, Shinichi Machida, Yasunori Inoue
  • Patent number: 10861887
    Abstract: An image sensor may include a substrate including a plurality of unit pixel regions and having first and second surfaces facing each other. Each of the unit pixel regions may include a plurality of floating diffusion parts spaced apart from each other in the substrate, storage nodes provided in the substrate to be spaced apart from and facing the floating diffusion parts, a transfer gate adjacent to a region between the floating diffusion parts and the storage nodes, and photoelectric conversion parts sequentially stacked on one of the first and second surfaces. Each of the photoelectric conversion parts may include common and pixel electrodes respectively provided on top and bottom surfaces thereof and each pixel electrode may be electrically connected to a corresponding one of the storage nodes.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: December 8, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gwi-Deok Ryan Lee, Taeyon Lee
  • Patent number: 10861808
    Abstract: A method includes polishing a semiconductor substrate of a first die to reveal first through-vias that extend into the semiconductor substrate, forming a dielectric layer on the semiconductor substrate, and forming a plurality of bond pads in the dielectric layer. The plurality of bond pads include active bond pads and dummy bond pads. The active bond pads are electrically coupled to the first through-vias. The first die is bonded to a second die, and both of the active bond pads and the dummy bond pads are bonded to corresponding bond pads in the second die.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Chih-Chia Hu
  • Patent number: 10861814
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a bump structure, a polymer layer and a metal layer. The bump structure includes a metal pad and a bump electrically connected to the metal pad. The polymer layer extends laterally from a sidewall of the bump. The metal layer is over the bump structure and in physical contact with a side surface of the metal pad.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzung-Hui Lee, Chen-Hua Yu, Chi-Ming Tsai, Hung-Jui Kuo, Ming-Che Ho
  • Patent number: 10854456
    Abstract: Methods for fabricating a transistor and an electro-static discharge (ESD) device are provided. In a method, a first well area doped with a first well ion is formed in a base substrate. A second well area is doped with a second well ion in the base substrate. The second well area includes a first region adjacent to the first well area. A first ion doping region doped with first ions is formed in the first well area and the first region. A type of the first ions is the same as a type of the first well ion and opposite to a type of the second well ion. A gate structure is formed on a part of the first well area and at least a part of the first region.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: December 1, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Yong Li, Cheng Qing Wei
  • Patent number: 10847672
    Abstract: A proximity sensing module with dual transmitters includes a circuit board, a package housing, a sensing assembly and a transmitter unit. The sensing assembly includes a sensor disposed on the circuit board. The transmitter unit is shielded from the sensing assembly through the package housing and includes a first transmitter and a second transmitter both disposed on the circuit board. One of the first transmitter and the second transmitter is closer to the sensing assembly.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: November 24, 2020
    Assignee: LITE-ON SINGAPORE PTE. LTD.
    Inventors: Seng-Yee Chua, Guang-Li Song, Tong-Tee Tan