Patents Examined by Bilkis Jahan
  • Patent number: 11929305
    Abstract: In a method for manufacturing an electrostatic discharge protection circuit, an electrostatic discharge device structure is formed during a front side processing of a semiconductor substrate in a first area. Contact pads are formed on the front side on the electrostatic discharge device structure and in a second area. During back side processing of the semiconductor substrate, a metal connection between the first electrostatic discharge device structure and the second area is formed.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: March 12, 2024
    Assignee: Infineon Technologies AG
    Inventors: Andre Schmenn, Klaus Diefenbeck, Joost Adriaan Willemen
  • Patent number: 11925012
    Abstract: A method for forming a capacitor array structure includes the following steps: providing a substrate, a capacitor contact being exposed on a surface of the substrate, and the substrate including an array region and a peripheral region; forming a bottom supporting layer covering the substrate and the capacitor contact, the bottom supporting layer having a gap therein; forming a filling layer filling the gap and covering the capacitor contact and the surface of the bottom supporting layer, a thickness of the filling layer located at the peripheral region being larger than that of the filling layer located at the array region; forming supporting layers and sacrificial layers alternately stacked in a direction perpendicular to the substrate; forming a capacitor hole; sequentially forming a lower electrode layer on an inner wall of the capacitor hole.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: March 5, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Chaojun Sheng, Wenjia Hu
  • Patent number: 11923449
    Abstract: A manufacturing method for a semiconductor device is provided. The method includes: forming a recess at a top surface of a substrate; forming a channel layer and a barrier layer in order, to conformally cover surfaces of the recess; filling up the recess with a conductive material; removing a top portion of the conductive material, such that a lower portion of the conductive material remained in the recess forms a gate electrode; and forming an insulating structure on the gate electrode. A hetero junction formed at an interface of the channel layer and the barrier layer is external to the substrate, and a two dimensional electron gas or a two dimensional hole gas is induced along the hetero junction external to the substrate.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: March 5, 2024
    Assignee: Winbond Electronics Corp.
    Inventors: Hao-Chuan Chang, Kai Jen
  • Patent number: 11923305
    Abstract: Some embodiments include an apparatus having a structure with a surface which comprises tungsten. The apparatus has titanium-nitride-containing protective material along and directly against the surface. The structure may be a digit line of a memory array. Some embodiments include a method in which an assembly is formed to have a tungsten-containing layer with an exposed tungsten-containing upper surface. Titanium-nitride-containing protective material is formed over and directly against the tungsten-containing upper surface. Additional material is formed over the protective material, and is spaced from the tungsten-containing upper surface by the protective material. The additional material may comprise silicon nitride and/or silicon dioxide.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: March 5, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Luca Fumagalli, Davide Colombo
  • Patent number: 11917819
    Abstract: A three-dimensional semiconductor memory device may include a first stack block including first stacks arranged in a first direction on a substrate, a second stack block including second stacks arranged in the first direction on the substrate, and a separation structure provided on the substrate between the first stack block and the second stack block. The separation structure may include first mold layers and second mold layers, which are stacked in a vertical direction perpendicular to a top surface of the substrate.
    Type: Grant
    Filed: June 28, 2021
    Date of Patent: February 27, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junhyoung Kim, Kwang-Soo Kim, Geunwon Lim, Jisung Cheon
  • Patent number: 11908735
    Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Jen Chang, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
  • Patent number: 11908859
    Abstract: A semiconductor device includes a first to sixth regions, a first gate, a first metal contact and a second metal contact. The second region is disposed opposite to the first region with respect to the first gate. The first metal contact couples the first region to the second region. The fourth region is disposed opposite to the third region with respect to the first gate. The second metal contact is coupling the third region to the fourth region. The fifth region is disposed between the first gate and the second region, and is disconnected from the first metal contact and the second metal contact. The sixth region is disposed between the first gate and the first region, and is disconnected from the first metal contact and the second metal contact.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Feng Chang, Po-Lin Peng, Jam-Wem Lee
  • Patent number: 11908783
    Abstract: Provided is a wiring substrate and its manufacturing method in which a thick wiring layer capable of being applied with a large current and a thin wiring layer capable of being subjected to microfabrication coexist in the same layer. The wiring substrate includes: an insulating film located over a first wiring and having a via; and a second wiring over the insulating film. The second wiring has a stacked structure including a first layer and a second layer covering the first layer. The second layer is in direct contact with the first wiring in the via. A thickness of the second layer in a region overlapping with the first layer is different from a thickness of the second layer in the via.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: February 20, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventor: Naoki Hayashi
  • Patent number: 11908817
    Abstract: A method includes polishing a semiconductor substrate of a first die to reveal first through-vias that extend into the semiconductor substrate, forming a dielectric layer on the semiconductor substrate, and forming a plurality of bond pads in the dielectric layer. The plurality of bond pads include active bond pads and dummy bond pads. The active bond pads are electrically coupled to the first through-vias. The first die is bonded to a second die, and both of the active bond pads and the dummy bond pads are bonded to corresponding bond pads in the second die.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Chih-Chia Hu
  • Patent number: 11898744
    Abstract: A quantum structure thin film includes an excitation layer, a first substrate and a second substrate. The excitation layer includes a plurality of quantum structures which are one of quantum dots and quantum rods, and which are made of one of cesium lead halide and organic ammonium lead halide. The first substrate and the second substrate are respectively disposed on two opposite sides of the excitation layer. One of the first substrate and the second substrate includes an inner layer, a buffer layer, and an outer layer that are sequentially disposed on the excitation layer in such order. Also disclosed herein is a quantum structure light-emitting module including the quantum structure thin film.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: February 13, 2024
    Assignee: SIC TECHNOLOGY CO. LTD
    Inventor: Shien-Tsung Wu
  • Patent number: 11901382
    Abstract: Provided is an imaging element including a photoelectric conversion unit formed by stacking a first electrode, a photoelectric conversion layer and a second electrode. The photoelectric conversion unit further includes a charge storage electrode which is disposed to be spaced apart from the first electrode and disposed opposite to the photoelectric conversion layer via an insulating layer. The photoelectric conversion unit is formed of N number of photoelectric conversion unit segments, and the same applies to the photoelectric conversion layer, the insulating layer and the charge storage electrode. An nth photoelectric conversion unit segment is formed of an nth charge storage electrode segment, an nth insulating layer segment and an nth photoelectric conversion layer segment. As n increases, the nth photoelectric conversion unit segment is located farther from the first electrode. A thickness of the insulating layer segment gradually changes from a first to Nth photoelectric conversion unit segment.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: February 13, 2024
    Assignee: Sony Group Corporation
    Inventors: Akira Furukawa, Yoshihiro Ando, Hideaki Togashi, Fumihiko Koga
  • Patent number: 11894445
    Abstract: Disclosed is a method for producing a semiconductor device, the method including forming a plurality of semiconductor arrangements one above the other, wherein forming each of the plurality of semiconductor arrangements includes forming a semiconductor layer, forming a plurality of trenches in a first surface of the semiconductor layer, and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches. Forming of at least one of the plurality of semiconductor arrangements further includes forming a protective layer covering mesa regions between the plurality of trenches of the respective semiconductor layer, and covering a bottom, the first sidewall and the second sidewall of each of the plurality of trenches that are formed in the respective semiconductor layer.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: February 6, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Daniel Tutuc, Matthias Kuenle, Ingo Muri, Hans Weber
  • Patent number: 11895822
    Abstract: The present disclosure relates to a memory structure and a forming method thereof. The present disclosure can improve the integration density of the memory structure. The memory structure includes: a plurality of vertical transistors, where the vertical transistors include silicon pillars; a plurality of the silicon pillars are arranged in m rows and n columns; the rows extend in a first direction and the columns extend in a second direction; m bit lines extending in the first direction and electrically connected to drains of all the vertical transistors in the same row, where the drains are located below the silicon pillars; and n word lines extending in the second direction, located in the middle of the silicon pillars, and serving as gates of all the vertical transistors in the same column, where the first direction and the second direction form a non-right angle.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: February 6, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yachao Xu
  • Patent number: 11894309
    Abstract: A method of forming semiconductor structure includes attaching backsides of top dies to a front side of a bottom wafer, the bottom wafer comprising a plurality of bottom dies; forming first conductive pillars on the front side of the bottom wafer adjacent to the top dies; forming a first dielectric material on the front side of the bottom wafer around the top dies and around the first conductive pillars; and dicing the bottom wafer to form a plurality of structures, each of the plurality of structures comprising at least one of the top dies and at least one of the bottom dies.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Tzuan-Horng Liu, Ming-Fa Chen, Chao-Wen Shih, Sung-Feng Yeh
  • Patent number: 11887935
    Abstract: A method for manufacturing a semiconductor device includes forming semiconductor devices from a semiconductor wafer and identifying a position of the semiconductor device in the semiconductor wafer, wherein the forming the semiconductor devices includes forming a first repeating pattern including i semiconductor devices each having a unique pattern, forming a second repeating pattern including j semiconductor devices each having a unique pattern, defining semiconductor devices on the semiconductor wafer such that each of the k semiconductor devices has a unique pattern based on the first and second repeating patterns, and grinding a backside of the semiconductor wafer, wherein each unique pattern of the k semiconductor devices is composed of a combination of the unique patterns of the first and second repeating patterns, wherein the position of the semiconductor device is identified based on the unique patterns of the first and second repeating patterns and an angle of a grinding mark.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: January 30, 2024
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takehiro Ueda
  • Patent number: 11881529
    Abstract: A method of fabricating a semiconductor device is provided. First, a semiconductor structure is provided, and the semiconductor structure includes a buried dielectric layer, a first gate structure disposed on a front-side of the buried dielectric layer, and a first source/drain region and a second source/drain region disposed between the buried dielectric layer and the first gate structure. Then, a trench is formed in the buried dielectric layer. Afterwards, a conductive layer is formed on the buried dielectric layer and in the trench. Finally, the conductive layer is patterned.
    Type: Grant
    Filed: September 5, 2022
    Date of Patent: January 23, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Ching-Yang Wen, Li Wang, Kai Cheng
  • Patent number: 11876093
    Abstract: A power device which is formed on a semiconductor substrate includes: plural lateral insulated gate bipolar transistors (LIGBTs) and a forward conductive unit. The plural LIGBTs are connected in parallel to each other. The forward conductive unit is connected in parallel to the plural LIGBTs. The forward conductive unit consists of a PN diode and a Schottky diode connected in parallel to each other. The PN diode and the Schottky diode share a same N-type region, a reverse terminal, an N-type extension region, an field oxide region, a gate, and a P-type well in an epitaxial layer. The N-type region and the P-type well form a PN junction, wherein the PN junction has a staggered comb-teeth interface from top view. A metal line extends on the staggered comb-teeth interface and alternatingly contacts the N-type region and the P-type well.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: January 16, 2024
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Chih-Feng Huang, Lung-Sheng Lin
  • Patent number: 11876095
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.
    Type: Grant
    Filed: July 5, 2021
    Date of Patent: January 16, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
  • Patent number: 11869832
    Abstract: The present disclosure is directed to a leadframe package with a surface mounted semiconductor die coupled to leads of the leadframe package through wire bonding. The leads are partially exposed outside the package and configured to couple to another structure, like a printed circuit board (PCB). The exposed portions, namely outer segments, of the leads include a plating or coating layer of a material that enhances the solder wettability of the leads to the PCB through solder bonding. The enclosed portions, namely inner segments, of the leads do not include the plating layer of the outer segment and, thus, include a different surface material or surface finish.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: January 9, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Paolo Crema
  • Patent number: 11869880
    Abstract: A method of transferring a micro light emitting diode (LED) to a pixel array panel includes transferring the micro LED by spraying using an inkjet method, wherein the micro LED includes an active layer including a first portion emitting light in a first direction and a second portion emitting the light in a second direction different from the first direction.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: January 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungwook Hwang, Junsik Hwang, Sungwoo Hwang