Abstract: A display apparatus is provided. The display apparatus includes a substrate including a plurality of pixels configured to emit light, wherein the amount of emitted light is at a maximum when emitted at an angle of more than 0 degrees. The display apparatus further includes an encapsulation layer covering the plurality of pixels and including a plurality of light collecting structures each having a three-dimensional quadrangular horn shape or a three-dimensional quadrangular truncated-horn shape.

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first conductive clip, where the first terminal of the inductor can be coupled with a contact pad of the first conductive clip. The second terminal of the inductor can be electrically coupled with the leadframe via a second conductive clip, where the second terminal of the inductor can be coupled with a contact pad of the second conductive clip. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.

Abstract: The present disclosure relates to a power module that has a housing with an interior chamber and a plurality of switch modules interconnected to facilitate switching power to a load. Each of the plurality of switch modules comprises at least one transistor and at least one diode mounted within the interior chamber and both the at least one transistor and the at least one diode are majority carrier devices, are formed of a wide bandgap material system, or both. The switching modules may be arranged in virtually any fashion depending on the application. For example, the switching modules may be arranged in a six-pack, full H-bridge, half H-bridge, single switch or the like.

Abstract: Embodiments of the invention include a semiconductor light emitting device capable of emitting first light having a first peak wavelength and a semiconductor wavelength converting element capable of absorbing the first light and emitting second light having a second peak wavelength. The semiconductor wavelength converting element is attached to a support and disposed in a path of light emitted by the semiconductor light emitting device. The semiconductor wavelength converting element is patterned to include at least two first regions of semiconductor wavelength converting material and at least one second region without semiconductor wavelength converting material disposed between the at least two first regions.

Abstract: A method for semiconductor manufacturing includes providing a substrate, forming a patterning layer over the substrate, and patterning the patterning layer to form a hole in the patterning layer. The method also includes applying a first directional etching to two inner sidewalls of the hole to expand the hole along a first direction and applying a second directional etching to another two inner sidewalls of the hole to expand the hole along a second direction that is different from the first direction.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include a first process of causing a stacking fault of a first semiconductor layer to expand. The first semiconductor layer includes silicon carbide and a first element and is provided on a base body including silicon carbide. The first element includes at least one selected from the group consisting of N, P, and As. The method can include a second process of forming a second semiconductor layer on the first semiconductor layer after the first process. The second semiconductor layer includes silicon carbide and the first element. The method can include a third process of forming a third semiconductor layer on the second semiconductor layer. The third semiconductor layer includes silicon carbide and a second element. The second element includes at least one selected from the group consisting of B, Al, and Ga.

Abstract: This document describes a device that is monolithic and capable of emitting quantum light without using previous configurations known in the art that require certain elements which yield certain disadvantages, which may be solved by implementing the device of the invention described herein. In this way the use of a transmitter which controls the state of charge or the wavelength of quantum light emitters independently of current in the device is implemented and does function properly when quantum light emitters are embedded in photonic structures, like microcavities or photonic crystals (PC); this is achieved by stacking semiconductor layers with different composition and doping types. A quantum light emitter circuit, which is a quantum optical circuit comprising at least two of said devices, is also an as aspect of the invention disclosed herein.

Abstract: A semiconductor device fabrication method includes forming first and second spaced apart base regions and source regions in a substrate with a portion of a drift region therebetween. The method further includes forming at least a first trench extending laterally through the base region, the drift region and the source region, the first trench extending vertically partially through the source region. The method also includes forming a first oxide layer over the trenched upper surface, and forming a polysilicon layer over the first oxide layer. The polysilicon layer is patterned to form the gate conductor, and a drain contact is formed on a bottom surface of the semiconductor substrate.

Abstract: An alignment mark structure includes a dielectric layer. A trench is embedded in the dielectric layer. An alignment mark fills up the trench, wherein the alignment mark includes a metal layer covering the trench. A first material layer covers and contacts the metal layer. A second material layer covers and contacts the first material layer. A third material layer covers and contacts the second material layer. The first material layer, the second material layer, and the third material layer independently includes silicon nitride, silicon oxide, tantalum-containing material, aluminum-containing material, titanium-containing material, or a low-k dielectric having a dielectric constant smaller than 2.7, and a reflectance of the first material layer is larger than a reflectance of the second material layer, the reflectance of the second material layer is larger than a reflectance of the third material layer.

Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of first through interlayer vias (TIV), a second redistribution structure, an insulating layer, a supporting layer, and a plurality of conductive patches. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The first TIVs are embedded in the encapsulant. The second redistribution structure is disposed on the die, the first TIVs, and the encapsulant. The first redistribution structure is electrically connected to the second redistribution structure through the first TIVs. The insulating layer is disposed on the first redistribution structure opposite to the die and includes a plurality of air gaps. The supporting layer is over the insulating layer. The conductive patches are over the supporting layer. Locations of the conductive patches correspond to locations of the air gaps of the insulating layer.

Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.

Abstract: An IGBT device comprises a super-junction structure arranged in a drift region and formed by a plurality of N-type pillars and a plurality of P-type pillars which are alternately arrayed. Device cell structures of the IGBT device are formed in an N-type epitaxial layer at the tops of super-junction cells. Each device cell structure comprises a body region, a gate structure and an emitter region. N-type isolation layers having a doping concentration greater than that of the N-type epitaxial layer are formed between the bottom surfaces of the body regions and the top surfaces of the P-type pillars and are used for isolating the body regions from the P-type pillars. The super-junction structure and the N-type isolation layers can increase the current density of the device, decrease the on-state voltage drop of the device and reduce the turn-off loss of the device.

Abstract: An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor.

Abstract: The present invention teaches a TFT array substrate, including a substrate; a first metallic layer disposed on the substrate; a gate insulation layer disposed on the first metallic layer and the substrate, where the gate insulation layer includes a level section above the first metallic layer and a pair of step sections respectively connected to lateral sides of the level section; a second metallic layer disposed on the level section, where an area of the second metallic layer's vertical projection onto the top side of the substrate is smaller than an area of the level section's top side; and a protection layer disposed on the second metallic layer and the gate insulation layer. As the second metallic layer is withdrawn for a distance from the level section's circumference, the protection layer is not required to rise continuously, and the protection layer is less prone to broken film and oxidization.

Abstract: A wafer includes a first face having a first center, and a second face having a second center. The first and second centers are each arranged on a central axis, which passes through the first face and the second face. The first face and the second face adjoin one another at a circumferential edge. An alignment notch is disposed along the circumferential edge, and extends inwardly from the circumferential edge by an alignment notch radial distance. The alignment notch radial distance is less than a wafer radius as measured from the first center to the circumferential edge. A die region includes an array of die arranged in rows and columns and is circumferentially bounded by a die-less region which is devoid of die. A first identification mark including a string of characters is disposed entirely in the die-less region to a first side of the alignment notch.

Abstract: A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.

Abstract: Described herein are conformal films and methods for forming a conformal Group 4, 5, 6, 13 metal or metalloid doped silicon nitride dielectric film. In one aspect, there is provided a method of forming an aluminum silicon nitride film comprising the steps of: providing a substrate in a reactor; introducing into the reactor an at least one metal precursor which reacts on at least a portion of the surface of the substrate to provide a chemisorbed layer; purging the reactor with a purge gas; introducing into the reactor an organoaminosilane precursors to react on at least a portion of the surface of the substrate to provide a chemisorbed layer; introducing a plasma comprising nitrogen and an inert gas into the reactor to react with at least a portion of the chemisorbed layer and provide at least one reactive site wherein the plasma is generated at a power density ranging from about 0.01 to about 1.

Abstract: A method for depositing a film to form an air gap within a semiconductor device is disclosed. An exemplary method comprises pulsing a metal halide precursor onto the substrate and pulsing an oxygen precursor onto a selective deposition surface. The method can be used to form an air gap to, for example, reduce a parasitic resistance of the semiconductor device.

Abstract: A present invention includes the following: a third impurity region having a second conductivity type and disposed in an outer peripheral region that is the outer periphery of a cell arrangement region in which a unit cell is disposed; a field insulating film disposed in the outer peripheral region; an interlayer insulating film; a first main electrode disposed on the interlayer insulating film. The third impurity region includes a fourth impurity region having the second conductivity type, having a higher impurity concentration than the third impurity region. A gate wire and a gate pad are disposed in the outer peripheral region. The fourth impurity region is adjacent to the cell arrangement region, surrounds at least a region below the gate pad, and is electrically connected to the first main electrode.