Abstract: A device includes a dielectric layer, an interlayer metal pad in the dielectric layer, a first capacitor over the interlayer metal pad, and a second capacitor over the dielectric layer. The first capacitor includes a first bottom capacitor electrode over and in contact with the interlayer metal pad, a first top capacitor electrode, and a first inter-electrode dielectric layer between the first bottom capacitor electrode and the first top capacitor electrode. The second capacitor includes a second bottom capacitor electrode over and in contact with the dielectric layer, a second top capacitor electrode, and a second inter-electrode dielectric layer between the second bottom capacitor electrode and the second top capacitor electrode.

Abstract: A display substrate includes: a base substrate including a photosensitive region, the photosensitive region including a plurality of display regions spaced apart and a gap region between the plurality of display regions; a first electrode layer on the base substrate; a light-emitting layer on a side of the first electrode layer away from the base substrate; and a second electrode layer on a side of the light-emitting layer away from the base substrate. Each display region corresponds to at least one first luminescent material region of the light-emitting layer; the gap region corresponds to the plurality of second luminescent material regions of the light-emitting layer; a part of the second electrode layer in the photosensitive region includes a plurality of second electrodes spaced apart, and an orthographic projection of each second electrode on the base substrate overlaps with each display region.

Abstract: A method of forming a fin field effect transistor (FinFET) includes etching a substrate to define a fin comprising a first material. The fin includes a first portion comprising first sidewalls tapered at a first angle and having a first height; and a second portion comprising second sidewalls tapered at a second angle different from the first angle and having a second height. A ratio of the second height to the first height ranges from about 0.2 to about 0.5. The method includes depositing an insulating material over the substrate, wherein the insulating material covers the fin. The method includes recessing the insulating material to expose at least the second portion of the fin. The method further includes forming a gate structure over the fin. The gate structure includes a gate dielectric over the fin and the recessed insulating material; and a conductive material over the gate dielectric.

Abstract: The present disclosure relates to a display device, and more particularly, to a display device including a plurality of pixels on a base layer and a first light-emitting element and a second light-emitting element, which are provided on a first pixel of the pixels. Here, each of the first and second light-emitting elements includes a first surface and a second surface opposite to the first surface, the first surface of the first light-emitting element faces the base layer, and the second surface of the second light-emitting element faces the base layer.

Abstract: A semiconductor device includes: a substrate; a drift region disposed on a principal surface of the substrate; a first well region extending from a second principal surface of the drift region in a direction perpendicular to the second principal surface and having a bottom portion; a second well region being in contact with the bottom portion and disposed at a portion inside the substrate located below the bottom portion; and a source region extending in a perpendicular direction from a region of the second principal surface provided with the first well region, and reaching the second well region. In a direction parallel to the second principal surface and oriented from a source electrode to a drain electrode, a distance of the second well region in contact with a gate insulating film is shorter than a distance of the first well region in contact with the gate insulating film.

Abstract: A process for fabricating an optoelectronic device for emitting infrared radiation, including: i) producing a first stack containing a light source, and a first bonding sublayer made from a metal of interest chosen from gold, titanium and copper, ii) producing a second stack containing a GeSn-based active layer obtained by epitaxy at an epitaxy temperature (Tepi), and a second bonding sublayer made from the metal of interest, iii) determining an assembly temperature (Tc) substantially between an ambient temperature (Tamb) and the epitaxy temperature (Tepi), such that a direct bonding energy per unit area of the metal of interest is higher than or equal to 0.5 J/m2; and iv) joining, by direct bonding, at the assembly temperature (Tc), the stacks.

Abstract: Methods and structures for improving alignment contrast for patterning a metal layer generally includes depositing a metal layer having a plurality of grains, wherein grain boundaries between the grains forms grooves at a surface of the metal layer. The metal layer is subjected to surface treatment to form an oxide or a nitride layer and fill the surface grooves. The metal layer can be patterned using alignment marks in the metal layer and/or underlying layers. Filling the grooves with the oxide or nitride increases alignment contrast relative to patterning the metal layer without the surface treating.

Abstract: A method of manufacturing a semiconductor device, the method including: forming, in a first region of a substrate, an active fin and a sacrificial gate structure intersecting the active fin; forming a first spacer and a second spacer on the substrate to cover the sacrificial gate structure; forming a mask in a second region of the substrate to expose the first region of the substrate; removing the second spacer from the first spacer in the first region of the substrate by using the mask; forming recesses at opposite sides of the sacrificial gate structure by removing portions of the active fin; forming a source and a drain in the recesses; and forming an etch-stop layer to cover both sidewalls of the sacrificial gate structure and a top surfaces of the source and drain.

Abstract: A semiconductor structure includes an electrode element with an upper surface. The upper surface includes at least one convex curved portion.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with slotted active regions and methods of manufacture. The method includes: forming a mandrel on top of a diffusion region comprising a diffusion material; forming a first material over the mandrel and the diffusion region; removing the mandrel to form multiple spacers each having a thickness; depositing a second material over the spacers and the diffusion material; and forming slots in the diffusion region by removing a portion of the second material over the diffusion region and the underlying diffusion material.

Abstract: A light emitting device includes a backplane, an array of light emitting diodes attached to a front side of the backplane, a transparent conductive layer contacting front side surfaces of the light emitting diodes, an optical bonding layer located over a front side surface of the transparent conductive layer, a transparent cover plate located over a front side surface of the optical bonding layer, and a black matrix layer including an array of openings therethrough, and located between the optical bonding layer and the transparent cover plate.

Abstract: A disclosed light-emitting device may provide white light with a cyan gap coinciding with a melanopic sensitivity range and thus having reduced melanopic content. The disclosed light-emitting device may include a light source providing violet or blue light with a peak wavelength under 450 nanometers (nm). The disclosed light-emitting device may include at least one down-converter coupled to and located downstream of the light source and configured with a long-wavelength onset to convert the spectrum of the violet or blue light to generate white light with a spectral power content in a 447-531 nm wavelength range that is less than or equal to 10% of a total spectral power content in a 380-780 nm wavelength range. The disclosed light-emitting device may be incorporated in a light engine system that further includes a control system that controls a drive current to the light-emitting device.

Abstract: A display apparatus includes a substrate including a display region and a non-display region, a blue sub-pixel in the display region of the substrate, an imaginary line extending across the blue sub-pixel, a first sub-unit on a first side of the imaginary line, the first sub-unit including a red sub-pixel, a green sub-pixel, and a white sub-pixel, and a second sub-unit on a second side of the imaginary line, the second sub-unit including a red sub-pixel, a green sub-pixel, and a white sub-pixel, wherein the first sub-unit and the blue sub-pixel constitute a first pixel, and the second sub-unit and the blue sub-pixel constitute a second pixel, and wherein the blue sub-pixel emits light according to a data signal generated based on blue-related data of first pixel data corresponding to the first pixel and blue-related data of second pixel data corresponding to the second pixel.

Abstract: The present invention provides a silicon carbide (SiC) semiconductor device integrating a metal-oxide-semiconductor field-effect transistor (MOSFET) and a bidirectional voltage clamping circuit. An object of protecting a device is achieved by using the simple structure above, effectively preventing device damage that may be caused by a positive overvoltage and a negative overvoltage between a gate and a source.

Abstract: A method includes the following operations: disconnecting at least one of drain regions that are formed on a first active area, of first transistors, from a first voltage; and disconnecting at least one of drain regions that are formed on a second active area, of second transistors coupled to the first transistors from a second voltage. The at least one of drain regions of the second transistors corresponds to the at least one of drain regions of the first transistors.

Abstract: Provided is an imaging element including a photoelectric conversion unit formed by stacking a first electrode, a photoelectric conversion layer and a second electrode. The photoelectric conversion unit further includes a charge storage electrode which is disposed to be spaced apart from the first electrode and disposed opposite to the photoelectric conversion layer via an insulating layer. The photoelectric conversion unit is formed of N number of photoelectric conversion unit segments, and the same applies to the photoelectric conversion layer, the insulating layer and the charge storage electrode. An nth photoelectric conversion unit segment is formed of an nth charge storage electrode segment, an nth insulating layer segment and an nth photoelectric conversion layer segment. As n increases, the nth photoelectric conversion unit segment is located farther from the first electrode. A thickness of the insulating layer segment gradually changes from a first to Nth photoelectric conversion unit segment.

Abstract: An electronics heat exchanger including a fluid flow body having a first panel, a second panel, and at least one fluid flow guide connecting the first panel and the second panel, a plurality of pedestals extending from the second panel, the plurality of pedestals including at least a first pedestal having a first height and a second pedestal having a second height, distinct from the first height, and wherein each of the pedestals is integral with the second panel.

Abstract: A semiconductor device includes a semiconductor layer that has a transistor structure including a p type source region, a p type drain region, an n type body region between the p type source region and the p type drain region, and a gate electrode facing the n type body region and a voltage-regulator diode that is disposed at the semiconductor layer and that has an n type portion connected to the p type source region and a p type portion connected to the gate electrode, in which the transistor structure and the voltage-regulator diode are unified into a single-chip configuration.

Abstract: Provided is a wiring substrate and its manufacturing method in which a thick wiring layer capable of being applied with a large current and a thin wiring layer capable of being subjected to microfabrication coexist in the same layer. The wiring substrate includes: an insulating film located over a first wiring and having a via; and a second wiring over the insulating film. The second wiring has a stacked structure including a first layer and a second layer covering the first layer. The second layer is in direct contact with the first wiring in the via. A thickness of the second layer in a region overlapping with the first layer is different from a thickness of the second layer in the via.

Abstract: Solid-state transducer (“SST”) dies and SST arrays having electrical cross-connections are disclosed herein. An array of SST dies in accordance with a particular embodiment can include a first terminal, a second terminal and a plurality of SST dies coupled between the first and second terminals with at least a pair of the SST dies being coupled in parallel. The plurality of SST dies can individually include a plurality of junctions coupled in series with an interconnection between each individual junction. Additionally, the individual SST dies can have a cross-connection contact coupled to the interconnection. In one embodiment, the array can further include a cross-connection between the cross-connection contacts on the pair of the SST dies.