Abstract: In a particular implementation, a method includes: identifying prospective zones for placement of one or more vertical interconnect access pads (via) in a cell, where each of the prospective zones comprises one or more poly pitches; and assigning a first color for a particular poly pitch of a first identified zone of the identified prospective zones or assigning a first color sequence for one or more sections of the first identified zone.

Abstract: A method of generating an IC layout diagram includes abutting a first row of cells with a second row of cells along a border, the first row including first and second active sheets, the second row including third and fourth active sheets, the active sheets extending along a row direction and having width values. The active sheets are overlapped with first through fourth back-side via regions, the first active sheet width value is greater than the third active sheet width value, a first back-side via region width values is greater than a third back-side via region width value, and a value of a distance from the first active sheet to the border is less than a minimum spacing rule for metal-like defined regions. At least one of abutting the first row with the second row or overlapping the active sheets with the back-side via regions is performed by a processor.

Abstract: A computing system may include a circuit design access engine configured to access a circuit design. The computing system may also include a duplicate section processing engine configured to partition the circuit design into multiple circuit sections and determine, from among the multiple circuit sections, an identical section set based on duplicate criteria. Circuit sections of the identical section set may satisfy the duplicate criteria with respect to one another. The duplicate section processing engine may further be configured to perform an OPC processing operation on a selected circuit section of the identical section set and apply an OPC result of the performed OPC processing operation for other circuit sections of the identical section set instead of or without performing the OPC processing operation on the other circuit sections of the identical section set.

Abstract: Circuit design development using block design containers can include opening, within a development environment generated by an Electronic Design Automation (EDA) system, a top-level block design specifying a circuit design and inserting, within the top-level block design using the EDA system, a block design container. The block design container specifies a source block design used as a sub-design within the top-level block design.

Abstract: A method for extracting information from the display panel, a device, and an electronic device are provided. The method includes obtaining output instructions of auxiliary signs in a design drawing of the display panel, obtaining different types of default auxiliary sign specification parameters, collecting sign parameters of the auxiliary signs in the design drawing of the display panel according to the auxiliary sign specification parameters, and outputting the sign parameters of the auxiliary signs in the design drawing of the display panel.

Abstract: A method of optimizing a recipe for a plasma process includes (a) building a virtual metrology (VM) model that predicts a wafer characteristic resulting from the plasma process based on a plasma parameter and (b) building a control model that describes a relationship between the plasma parameter and a recipe parameter. (c) The wafer characteristic is measured after performing the plasma process according to the recipe. (d) Whether the wafer characteristic is within a predetermined range is determined. (e) The VM model and the control model are calibrated based on the wafer characteristic. (f) The recipe is optimized by updating the plasma parameter based on the wafer characteristic using the VM model and updating the recipe parameter based on the plasma parameter using the control model. (c), (d), (e) and (f) are repeated until the wafer characteristic is within the predetermined range.

Abstract: Aspects of the invention include setting a fill mode for a border region of a layer of a macro of an integrated circuit. The border region has a depth defined by a multiple of the size of a tile used to select an area of the integrated circuit for implementation of a design rule check, and the fill mode indicates a fill percentage value or level of fill to be implemented in the border region of the layer of the macro. A fill of the border region of the layer of the macro is performed based on the fill mode. The integrated circuit is finalized and fabricated based on the performing of the fill and passing the design rule check.

Abstract: A method includes: identifying a first design rule check (DRC) violation in a cluster box on an integrated circuit layout; locating a first target cell at a first original location in the cluster box, the first target cell being connected to the first DRC violation; detecting a first plurality of candidate locations for the first target cell in the cluster box; calculating resource costs associated with the first plurality of candidate locations; determining a first relocation location, among the first plurality of candidate locations, associated with a minimum resource cost for the first target cell; and relocating the first target cell from the first original location to the first relocation location.

Abstract: Ground rule verification (“GRV”) design layouts may be automatically generated based on one or more design macros. The GRV design layout may be tested based on the one or more design macros by violating one or more ground rules using one or more GRV ranges. The testing may include electrical testing of the one or more GRV design layouts based on the one or more design macros. The one or more ground rules may be automatically selected and approved the based upon a degree of violation acceptability.

Abstract: The present application discloses a method for calculating equal lengths of wound differential wires, wherein the method includes: calculating total lengths of a P differential wire and an N differential wire of a to-be-wound-with-equal-lengths target differential-wire pair; according to the total lengths of the P differential wire and the N differential wire, calculating a differential-wire length difference between the P and N differential wires, and determining the one having a lower total length as a target differential wire; acquiring a distance between the P differential wire and the N differential wire, and using the distance as a protruding height; acquiring a preset protruding angle, and calculating the protruding height and the protruding angle according to a first calculating relation, to obtain a length added by one protruding; and according to the differential-wire length difference and the length added by one protruding, calculating a total quantity of protrudings.

Abstract: Various implementations described herein refer to a method. The method may be configured to synthesize standard cells for a physical design having a power supply net with power supply rails. The method may be configured to employ a place-and-route tool so as to define edge-types for each standard cell of the standard cells in the physical design based on the power supply net and the power supply rails that touch at least one edge of each standard cell of the standard cells.

Abstract: A method includes clustering cells in a group of cells into a selected number of clusters, and ranking the clusters based on a list of prioritized features to generate a list of ranked clusters. The method also includes ranking cells in each of one or more ranked clusters in the list of ranked clusters, based on the list of prioritized features, to generate a list of ranked critical cells. The method further includes outputting the list of ranked critical cells for use in adjusting cell layouts based on the ranked critical cells.

Abstract: A cart to store a plurality of mobile computing devices includes a plurality of slots defined by opposed plates. Each of the slots is configured to accept a corresponding mobile computing device. A first slot is defined by first and second plates, and a second slot is defined by the second plate and a third plate. The second plate includes a first transmit coil for wirelessly transmitting power to a first receive coil in a first mobile computing device within the first slot, and to a second receive coil in a second mobile computing device within the second slot.

Abstract: Systems and methods for optimizing data flow in an integrated circuit includes creating a task graph based on transforming an optimized network graph for a neural network application, wherein creating the task graph includes: enumerating a plurality of distinct tasks based on a decomposition of each of a plurality of network operations of the optimized network graph; and allocating a data buffer to each of pairs of dependent tasks of the plurality of distinct tasks based on the decomposition of each of the plurality of network operations of the optimized network graph; encoding a token-informed task scheduler based on a composition of the task graph, wherein the encoding the token-informed task scheduler includes: programming the token-informed task scheduler to cause an execution of the plurality of distinct tasks based on identifying a state of a respective data buffer between each of the pairs of dependent tasks.

Abstract: VLSI layouts of generalized multi-stage and pyramid networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links with spacial locality exploitation. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub-integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. Furthermore the shuffle exchange links are employed between different sub-integrated circuit blocks so that spatially nearer sub-integrated circuit blocks are connected with shorter links compared to the shuffle exchange links between spatially farther sub-integrated circuit blocks. In one embodiment the sub-integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane.

Abstract: The present disclosure relates to a device which charges and cleans a personal wearable device. The device includes a wireless charging circuit disposed within the device, and an ultraviolet light source disposed within the device. Further disclosed is a system which includes a device and a personal wearable device. The device includes a charging unit including wireless charging circuitry, and a cleaning unit including at least one ultraviolet light source; and a personal wearable device.

Abstract: A method of obfuscating a circuit design includes, in part, receiving a netlist of the circuit design, splitting the circuit design into a multitude of partitions, transforming each partitions so as to obfuscate each partition, and stitching the multitude of transformed partitions to form the obfuscated circuit. The netlist may be a register transfer level netlist. The number and the size of partitions may vary. The partitions may be distributed throughout the entirety of the design. The method may further include generating a randomized circuit associated with at least a subset of the partitions, and merging each partition with the partition's associated randomized circuit. The method may further include quantifying the amount of transformation associated with each partition. The method may further include adding a first key to at least one of the obfuscated partitions, and adding a second key to the partition's associated randomized circuit.

Abstract: A semiconductor device including a standard cell is provided. The standard cell includes an active region; a gate structure intersecting the active region; a first conductive structure including: a first power supply line and a second power supply line; and a second conductive structure disposed on the first conductive structure, the second conductive structure including: first power distribution patterns spaced apart from each other a first boundary and electrically connected to the first power supply line, second power distribution patterns spaced apart from each other along a second boundary and electrically connected to the second power supply line, net metal lines disposed between and spaced apart from the first power distribution patterns and the second power distribution patterns, and electrically connected to a first portion of the signal lines, and pin metal lines electrically connected to a second portion of the signal lines.

Abstract: A method includes receiving a layout for fabricating a mask, determining a first target contour corresponding to a first set of process conditions, determining a second target contour corresponding to a second set of process conditions, simulating a first potential modification to the layout under the first set of process conditions to generate a first simulated contour, simulating a second potential modification to the layout under the second set of process conditions to generate a second simulated contour, evaluating costs of the first and second potential modifications based on comparing the first and second simulated contours to the first and second target contours, respectively, and providing the layout and one of the first and second potential modifications having a lower cost for fabricating the mask. The first set of process conditions is different from the second set of process conditions.

Abstract: An IC structure includes a first cell and a first and second rail. The first cell includes a first and second active region and a first, a second and a third gate structure. The first active region having a first dopant type. The second active region having a second dopant type. The first gate structure extending in a second direction, overlapping the first or the second active region. The second gate structure extending in the second direction, and overlapping a first edge of the first or second active region. The third gate structure extending in the second direction, and overlapping at least a second edge of the first or second active region. The first rail extending in the first direction and overlapping a middle portion of the first active region. The second rail extending in the first direction and overlapping a middle portion of the second active region.