Abstract: A rechargeable battery short-circuit early detection device that detects a short-circuit in a rechargeable battery includes one or more processors connected to a current sensor that detects a charging current of the rechargeable battery, wherein the one or more processors are programmed to: if a detected temporal slope of the charging current exceeds a first threshold, determine that there is a possibility that a short circuit has occurred in at least one of the cells; detect anew a temporal slope of the charging current after a prescribed period of time has elapsed since the determination of said possibility; and thereafter, if the anew detected temporal slope of the charging current exceeds a second threshold that is greater than the first threshold, determine that there is a possibility that the short-circuit is progressing, and output a signal indicating said possibility.

Abstract: Using a model executing on a classical processor, a set of classical features is scored. The scored set of classical features is divided into a set of feature groups, a number of classical features in a group determined according to a qubit capability of a quantum processor. Using a model executing on the quantum processor and a group of the scored set of classical features, a set of quantum features is scored. The score of a quantum feature is adjusted according to an accuracy of the quantum data model. The scored set of classical features and the scored set of quantum features are combined according to a measure of differences between the scored set of classical features and the scored set of quantum features. Using the combined set of scored features and a first set of input data of a resource, a valuation of a resource is calculated.

Abstract: A method for predicting yield relating to a process of manufacturing semiconductor devices on a substrate, the method including: obtaining a trained first model which translates modeled parameters into a yield parameter, the modeled parameters including: a) a geometrical parameter associated with one or more selected from: a geometric characteristic, dimension or position of a device element manufactured by the process and b) a trained free parameter; obtaining process parameter data including data regarding a process parameter characterizing the process; converting the process parameter data into values of the geometrical parameter; and predicting the yield parameter using the trained first model and the values of the geometrical parameter.

Abstract: A charging assembly is for charging an electric vehicle. The charging assembly has an electrical socket configured for connecting a charging station to a specific branch an electric vehicle supply installation. The installation has a fuse cabinet and a branch connected to the fuse cabinet. The socket has a data storage medium readable by the charging station. The data storage medium has a data field representing a maximum electrical current that can be drawn from the fuse cabinet by the specific branch, and optionally a data field representing a maximum electrical current that can be drawn by the charging station. The charging station can be coupled to the electrical socket, and is configured for reading the data storage medium including the data fields and for accordingly adapting the way current is drawn from the branch and provided to the electric vehicle.

Abstract: Embodiments of the present application provide a circuit simulation method and a device. The method includes: determining a top-layer structure and a minimum circuit cell layer of a circuit schematics; determining, in a circuit layout, an area and a relative distribution location of each target circuit cell in the minimum circuit cell layer; generating a first circuit structure based on the top-layer structure, each target circuit cell, and the area and the relative distribution location of each target circuit cell in the circuit layout; and adding a parasitic effect circuit to the first circuit structure, generating a target circuit structure corresponding to the circuit schematics, and performing simulation based on the target circuit structure.

Abstract: The present invention provides a method for reasonably adjusting an end-of-discharge voltage of a lithium battery with attenuation of a battery life. The method includes: acquiring an end-of-charge voltage, an end-of-discharge voltage and a rated capacity based on a basic parameter table for a lithium battery, then setting a safety end-of-charge voltage and a safety end-of-discharge voltage to obtain an initial safety discharge capacity, and finally setting a preset discharge capacity of the battery; using an Ampere-hour integration method to estimate a discharged power, taking the preset discharge capacity as a discharge standard, and stopping discharge when the discharged power reaches the preset discharge capacity; and the safety discharge capacity being gradually less than the preset discharge capacity within a battery life cycle, and the battery stopping discharge when the voltage reaches the safety end-of-discharge voltage.

Abstract: A system and method for fixing DRC violations includes receiving a layout pattern having a design rule check (DRC) violation therein, determining that the layout pattern is an inlier based upon a comparison of the layout pattern with a plurality of previously analyzed layout patterns. The comparison may be performed by an anomaly detection algorithm. The system and method may also include selecting a recipe from a pool of recipes previously applied to the plurality of previously analyzed layout patterns for fixing the DRC violation in the layout clip upon determining that the layout pattern is an inlier.

Abstract: The present application provides a design rule check method and apparatus, and a storage medium, which are applied to the field of chip verification. The method includes that: a DRC code file is acquired, multiple segments of DRC codes in the DRC code file are analyzed, the analyzed segments of DRC codes are classified, whether a code conflict exists in the segments of DRC codes is determined, and if the code conflict exists, a code conflict report is generated, the code conflict report being used to indicate a code position of the code conflict. By means of the method, the code error in the DRC code file can be quickly checked and positioned, assisting a tester in modifying a DRM file and the DRC file, so as to improve the execution efficiency of the DRC code, and meanwhile, shorten the time for DRC development.

Abstract: A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first width of at least one first metal interconnect is different from a second width of one of the plurality of second metal interconnects.

Abstract: Systems and methods are provided for generating test patterns. In various embodiments, systems and methods are provided in which machine learning is utilized to generate the test patterns in a manner so that the test patterns conform with design rule check (DRC) specified for a particular semiconductor manufacturing process or for particular types of devices. A test pattern generation system includes test pattern generation circuitry which receives a noise image. The test pattern generation generates a pattern image based on the noise image, and further generates a test pattern based on the pattern image. The test pattern is representative of geometric shapes of an electronic device design layout that is free of design rule check violations.

Abstract: A method for curing antenna violations on an integrated circuit that includes multiple levels includes: obtaining a design of a circuit, the design including a first element connected to first device and a second element connected to one or more second devices, wherein the first and second elements both receive a common signal; determining that an antenna violation exists in on the first element at a first level of the multiple levels; and modifying the design of the circuit to add a connected between the first element and the second element at the first layer or at a layer below the first layer.

Abstract: A mask layout containing a non-Manhattan pattern is received. The received mask layout is processed. An edge of the non-Manhattan pattern is identified. A plurality of two-dimensional kernels is generated based on processed pre-selected mask layout samples. The two-dimensional kernels each have a respective rotational symmetry. The two-dimensional kernels are applied to the edge of the non-Manhattan pattern to obtain a correction field for the non-Manhattan pattern. A thin mask model is applied to the non-Manhattan pattern. The thin mask model contains a binary modeling of the non-Manhattan pattern. A near field of the non-Manhattan pattern is determined by applying the correction field to the non-Manhattan pattern having the thin mask model applied thereon. An optical model is applied to the near field to obtain an aerial image on a wafer. A resist model is applied to the aerial image to obtain a final resist image on the wafer.

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes an area-oriented region and a performance-oriented region, standard cells disposed on each of the area-oriented region and the performance-oriented region, and a routing metal layer on the standard cells. The routing metal layer includes first routing lines on the area-oriented region and second routing lines on the performance-oriented region. The smallest line width of the first routing lines is a first width, the smallest line width of the second routing lines is a second width greater than the first width, a pitch between the first routing lines is a first pitch, and a pitch between the second routing lines is a second pitch greater than the first pitch.

Abstract: The present disclosure relates to software-defined methods and apparatuses for designing a wafer-level switching system, including: determining wafer-level switching system layout constraints; constructing a target wafer-level switching system and determining parameters, and designing a logical topology of a switching network; designing a layout of the switching chiplets on the wafer substrate; respectively designing interface structures of external chiplets and internal chiplets; configuring a switching mode and an enable state of each port of the switching chiplets; ending the process when the target logical topology can be achieved by the wafer-level switching system; otherwise, reconstructing a logical topology of a switching network and mapping it to the substrate.

Abstract: Embodiments of the present invention relate to the field of circuit technology, and disclose a method for correcting a SOC of a battery pack, a battery management system, and a vehicle. The method for correcting an SOC of a battery includes: determining, when a charging process of the battery pack starts, whether an initial SOC value of the battery pack is less than or equal to a preset electricity quantity threshold; when the initial SOC value of the battery pack is less than or equal to the preset electricity quantity threshold, recording state information of the battery pack during the charging process, and generating a differential capacity curve of the battery pack according to the state information; correcting a current SOC value of the battery pack according to the differential capacity curve and a voltage-SOC reference curve of a non-decay zone of the battery pack.

Abstract: Embodiments provide for interactive routing transistor devices of an integrated circuit (IC) design using an interactive routing tool. An example method includes receiving an integrated circuit (IC) design comprising a plurality of transistor devices. The example method further includes receiving a design rule check (DRC) rules set. The example method further includes, responsive to identifying, based at least in part on the DRC rules set, that a first connection input associated with a transistor device of the plurality of transistor devices creates a design rule violation, determining whether a force mode input has been received. The example method further includes, responsive to determining that the force mode input has been received, enabling routing of the first connection input.

Abstract: A method of pruning nets in a circuit design includes, in part, receiving data representative of net layers associated with the circuit design, and accessing a connect database associated with the circuit design. The connect database includes data representative of electrical connections associated with the circuit design. The method further includes, in part, determining whether a marker layer exists in the net layers, and pruning nets that are not connected to the marker layer if the marker layer is determined to exist. The marker layer, which is not stored in the connect database, designates a connection between at least a pair of nets in the circuit design.

Abstract: An electronic system and an operation method thereof are disclosed. A method of an electronic system including a field programmable gate array (FPGA) includes: synthesizing, by processing circuitry, code of a high level language into code of a hardware description language; designing, by the processing circuitry, a circuit of an intellectual property (IP) block included in the field programmable gate array according to the code of the hardware description language; and generating, by the processing circuitry, a database containing reference assembly code corresponding to the code of the high level language and information about a circuit configuration of the intellectual property block.

Abstract: A constraint graph for a candidate routing solution is created; each node in the graph represents a position of an end of a metal shape and each arc in the graph represents a design rule constraint between two of the nodes. A solution graph is computed, for at least a portion of the constraint graph, using a shape processing algorithm. The solution graph is checked for design rule violations to generate one or more violation graphs. A constraint window and a selection of one or more arcs for at least one of the violation graphs are generated. The candidate routing solution is revised, based on one or more violated design rules corresponding to at least one of the selected arcs within the constraint window. Optionally, an integrated circuit is fabricated in accordance with the revised solution.

Abstract: In execution of an equalization process between a plurality of cells connected in series, power supply system is provided. In power supply system, control circuit performs active balancing between a plurality of cells included in each of a plurality of series cell groups, using a plurality of active cell balancing circuits, and performs passive balancing between the plurality of series cell groups. Voltage detection circuit connected to a series cell group being undergoing the passive balancing and consuming power is supplied with power from first power supply circuit. Voltage detection circuit connected to series cell group being undergoing active cell balancing by active cell balancing circuit is supplied with power from second power supply circuit higher in efficiency than first power supply circuit.