Abstract: An electrical storage system comprises a first energy storage system and a second energy storage system having a lower electrical energy density and a higher rated electrical power output capability than the first energy storage system, at least one electrical power sensor configured to sense over a plurality of time intervals, electrical power usage information for a load electrically coupled to the first energy storage system and the second energy storage system, and at least one computer processor programmed to determine based, at least in part, on the sensed electrical power usage information and a power requirement of the load in a current time interval, charging/discharging parameters for each of the first energy storage system and the second energy storage system, and control charging/discharging of each of the first and second energy storage systems in accordance with the determined charging/discharging parameters during the current time interval.

Abstract: Described is an apparatus for extending cycle-life of a battery cell, where the apparatus comprises: a monitor to monitor a rate of degradation of a battery cell overtime; a comparator to compare the rate of degradation with a threshold; and logic to adjust one or more charge parameters of the battery cell when the rate of degradation crosses the threshold. Described is a method which comprises: monitoring a rate of degradation of a battery cell overtime; comparing the rate of degradation with a threshold; and adjusting one or more charge parameters of the battery cell when the rate of degradation crosses the threshold. Described is a machine-readable storage media having machine executable instructions stored thereon that, when executed, causes one or more processors to perform the method described above.

Abstract: A foldable watch charging adapter has a watch charging housing provided with an induction charge surface. The watch charging housing is coupled to a charge end of a charge arm. A joint rotatably couples a pivot end of the charge arm to a joint end of a connector arm; and an electrical connector is provided at a connector end of the connector arm. An angular interconnection orientation of the electrical connector may be adjusted by rotating the connector arm with respect to the charge arm about the joint. Further, a connection interface adapter may be included to increase the range of connection interfaces that may be utilized.

Abstract: Various embodiments provide for routing a net of a circuit design using rule-based routing blockage extension, which may be part of electronic design automation (EDA). In particular, some embodiments route a net of a circuit design by determining a dimension extension value based on a design rule of the circuit design and applying the dimension extension value to at least one existing routing blockage.

Abstract: An inverter current equalization method includes separately comparing a reactive current of a first inverter and a reactive current of a second inverter with a reactive current reference value, to obtain a reactive current difference of the first inverter and a reactive current difference of the second inverter, separately comparing an active current of the first inverter and an active current of the second inverter with an active current reference value, to obtain an active current difference of the first inverter and an active current difference of the second inverter, and adjusting an input voltage amplitude of the first inverter and an input voltage amplitude of the second inverter based on the reactive current difference of the first inverter and the reactive current difference of the second inverter.

Abstract: There is provided a regression test method, an electronic device and a storage medium, and relates to the field of artificial intelligence, such as artificial intelligence chips, cloud computing, intelligent voices, or the like. The method includes: when execution of any regression test is completed, determining a to-be-adjusted test case from test cases according to a current test result; and adjusting a randomization weight corresponding to a data range randomized by the to-be-adjusted test case in a current test.

Abstract: A first set of critical dimension (CD) measurements of resist patterns created by a lithography process and a second set of CD measurements of water patterns created by an etch process may be obtained. A forward etch model and an inverse etch model may be calibrated together by reducing (1) a first prediction error between the second set of CD measurements and a first set of simulated CDs predicted by the forward etch model based on the resist patterns, a second prediction error between the first set of CD measurements and a second set of simulated CDs predicted by the inverse etch model based on the wafer patterns, and a matching error between the forward etch model and the inverse etch model.

Abstract: A battery management system for a plurality of battery modules, the battery management system including, for each battery module among the plurality of battery modules, a respective integrated circuit configured to perform a cell balancing control function of the battery module; and a battery controller in communication with the integrated circuits, the battery controller configured to control the integrated circuits according to a cycle that includes a first mode for sequentially activating cell balancing of the battery modules during a first period and a second mode for stopping the cell balancing of the battery modules during a second period that follows the first period, the battery controller repeating the cycle after the second period, repeating the cycle including changing an order in which the cell balancing of the battery modules is activated in the first mode.

Abstract: Various implementations described herein are related to a method for constructing integrated circuitry and identifying input signal paths, internal signal paths and output signal paths associated with the integrated circuitry. The method may include generating a timing table for slew-load characterization of the input signal paths, the internal signal paths and the output signal paths. The method may include simulating corner points for the timing table, building diagonal points for the timing table based on the simulated corner points, and building remaining points for the timing table based on the simulated corner points and the diagonal points.

Abstract: A system and a method of optimizing an optical proximity correction (OPC) model for a mask pattern of a photo mask is disclosed. A machine learning (ML) based model builder includes an OPC model, measurement data and a random term generator. Random terms are generated in a M-dimensional space by the random term generator. The ML based model builder classifies the random terms to clusters by applying a classifying rule. A representative subset of the random terms is determined among the classified clusters, and the representative subset is added to the OPC model.

Abstract: A method of process technology assessment is provided. The method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (EDA) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.

Abstract: A power receiving device according to the present disclosure includes a power receiving section that receives power from a power feed device with use of a power receiving coil; and a communication section that transmits coil information to the power feed device, the coil information indicating whether or not a coil is provided near the power receiving coil.

Abstract: An electronic device includes: a location measurement circuitry; a rechargeable battery; a memory configured to store instructions; and at least one processor. The at least one processor may be configured to execute the instructions to: monitor a usage pattern of the battery while the electronic device operates in a first power management state; acquire, based on determining that the usage pattern of the battery is different from a reference pattern derived from a model, information on a location in which the battery is estimated to be charged and information on a time at which the battery is estimated to be charged using the model; and switch, partially based on the information on the location and the information on the time, the first power management state to a second power management state based on a second maximum driving frequency lower than the first maximum driving frequency.

Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with real-time modeling. An electronic design may be prepared for an analysis that programmatically sweeps across multiple values of a new parameter for multiple instances in the electronic design. The analysis may be performed on the electronic design at least by adding the new parameter to the analysis engine and by sweeping the new parameter across the multiple values to generate an analysis result. The electronic design may then be updated based at least in part upon the analysis result.

Abstract: Embodiments disclosed herein include a semiconductor manufacturing tool with a hybrid model and methods of using the hybrid model for processing wafers and/or developing process recipes. In an embodiment, a method for developing a semiconductor manufacturing process recipe comprises selecting one or more device outcomes, and querying a hybrid model to obtain a process recipe recommendation suitable for obtaining the device outcomes. In an embodiment, the hybrid process model comprises a statistical model and a physical model. In an embodiment, the method may further comprise executing a design of experiment (DoE) on a set of wafers to validate the process recipe recommended by the hybrid process model.

Abstract: A routing process applied to design integrated circuits uses keep-through regions. Keep-through regions specify areas which metal shapes may overlap but where metal shapes may not have line ends. The keep-through regions are generated based on end-of-line rules applicable to routing of the design. These keep-through regions are then used in determining the layout of interconnects for the design.

Abstract: A method of reducing a power consumption of a wireless device according to one embodiment includes performing, by the wireless device, a calibration of wireless communication circuitry of the wireless device in response to establishing a wireless communication connection with a wireless access point, determining, by the wireless device, a number of disconnections between the wireless device and the wireless access point over a predefined period of time, and increasing, by the wireless device, a sleep interval of the wireless communication circuitry of the wireless device in response to determining the number of disconnections between the wireless device and the wireless access point over the predefined period of time is less than a threshold number of disconnections.

Abstract: The present invention is a system for optimizing the shipping of wall panels, comprising: analyzing a building model, wherein a set of wall panels are isolated; processing a first set of data associated each of the set of wall panels, wherein the first set of data is related to members of the wall panel and the interface between these members; grouping a first group of the set of wall panels into a bundle, wherein the first group of wall panels is based on the processed first set of data; analyzing the bundle relative to the volume of a shipping vessel, wherein it is determined if the shipping vessel can container the vessel; manipulating, by at least one processor the bundle of wall panels based on limitations of the shipping vessel; and generating a graphical representation of the bundle and the position of the bundle within the shipping vessel.

Abstract: Disclosed are method(s), system(s), and article(s) of manufacture for implementing an approach to facilitate traceability and tamper detection of electronic designs. This approach allows for tracing and tamper detection at any stage of design and manufacturing, such as during layout generation, post-design, post-mask, and post manufacturing of the electronic designs.

Abstract: A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first via connects the first metal interconnect to the pin, and the at least one first metal interconnect is perpendicular to the pin.