Abstract: To increase the efficiency of an electronic design automation (EDA) process, for a putative integrated circuit design for which computerized routing is to be carried out within an EDA program, run a sweep line algorithm selectively on active metal shapes in said putative design for different layers, to determine a total number of said active metal shapes, and compute a memory requirement for computerized routing on said active shapes based on said total number of said active shapes. For said putative design, compute a memory requirement for computerized routing on inactive metal shapes based on a total number of said inactive shapes; partition said putative design into a plurality of partitions, based on said memory requirement for computerized routing on said active and inactive shapes, such that an available system memory is not exceeded. Separately run a routing job on each of said plurality of partitions.

Abstract: A method and system disclosed for validating technology file design rules, including obtaining a technology file with design rules that are to be validated. An input test case library is obtained with design rule cell-views for each corresponding design rules. The design rule cell-view includes a first set of failed test cases. An output data is generated by using Design Rule Driven (DRD) tool, to test the design rules based on the design rule cell-views. The test output data provides a second set of failed test cases associated with the corresponding design rule. A validation result is determined for each of the plurality of design rules based on the first set of failed test cases and the second set of failed test cases associated with the design rule. Finally, a validation report is generated including the validation result for each design rules.

Abstract: A multi-threaded imperative programming language includes a language construct defining a function call. A circuit implementation for the construct includes a first pipeline, a second pipeline, and a third pipeline. The first hardware pipeline outputs variables to a first queue and outputs parameters for the function to a second queue. The second hardware pipeline obtains the function parameters from the second queue, performs the function, and stores the results of the function in a third queue. The third hardware pipeline retrieves the results generated by the second pipeline from the second queue and retrieves the variables from the first queue. The third hardware pipeline performs hardware operations specified by the source code using the variables and the results of the function. A single instance of the circuit implementation can be utilized to implement calls to the same function made from multiple locations within source code.

Abstract: An integrated circuit design technique utilizes a data structure describing the connections, interconnect routing information of the connections, and bandwidth requirements of the connections in an integrated circuit device to generate an interconnect flow graph having nodes, and edges connecting the nodes. The edges connecting the nodes can reflect the bandwidth requirements of the connections. The interconnect flow graph can be used to optimize and verify the integrated circuit design.

Abstract: Computer-implemented systems and methods for improving construction of a mask layout block, for eliminating electromigration and self-heat violations during construction of a mask layout block, and for maintaining process design rules and layout connectivity during construction of a mask layout block are provided. At least one selected polygon is analyzed and a selected position of the selected polygon determined. The systems and methods obtain one or more electromigration rules or self-heat rules associated with the selected polygon. An information window with the one or more electromigration or self-heat rules and a violation marker associated with the selected position of the selected polygon are provided. The system determines if the selected position of the selected polygon or a length or width of the selected polygon violates an electromigration rule or self-heat rule.

Abstract: An IC structure includes a first cell and a first and second rail. The first cell includes a first and second active region and a first, a second and a third gate structure. The first active region having a first dopant type. The second active region having a second dopant type. The first gate structure extending in a second direction, overlapping the first or the second active region. The second gate structure extending in the second direction, and overlapping a first edge of the first or second active region. The third gate structure extending in the second direction, and overlapping at least a second edge of the first or second active region. The first rail extending in the first direction and overlapping a middle portion of the first active region. The second rail extending in the first direction and overlapping a middle portion of the second active region.

Abstract: To determine a three-dimensional layout of electrical connections of an electric component, a processor executes a path optimization routine to determine three-dimensional routes for a plurality of electrical connections of the electric component. A conflict management is performed to generate conflict-free three-dimensional routes for the plurality of electrical connections.

Abstract: The independent claims of this patent signify a concise description of embodiments. Roughly described, a design team prioritizes polygons of a circuit design layout. This information is then encoded into a layout database that is passed to the manufacturing team for correction further processing toward tape-out. The priorities may be used by an engineer to disposition errors found in the layout. For example, a failure may be waived. In another embodiment, the priorities are used during hotspot fixing, a process where failed features are corrected. In hotspot fixing, the priority can be used to make correction tradeoffs in favor of the highest priority features. Priorities are set during the correction to favor fidelity of the higher priority features over the lower priority features. Each embodiment reduces cost, and in some cases, improve final device performance. This Abstract is not intended to limit the scope of the claims.

Abstract: A method of adapting the charging of an accessory device includes transmitting a first transmission signal at a first transmission amplitude, measuring a receiving load of the first transmission signal, and if the charging device does not receive a response signal to the first transmission signal, transmitting a second transmission signal at a second transmission amplitude that is different from the first transmission amplitude.

Abstract: The technology relates generally to a distributed battery cell charging circuit that allows for battery cells to be positioned in different locations. The distributed battery charging circuit may include a first charging circuit including at least one battery cell, a second charging circuit including at least one battery cell, and a controller configured to control the charging of the at least one battery cell in the first charging circuit independently of controlling the charging of the at least one battery cell in the second charging circuit.

Abstract: A computing system may include a metal stack tuning engine and a tuned metal stack application engine. The metal stack tuning engine may be configured to access an obscured metal stack definition specified for an integrated circuit (IC) manufacture process and tune selected metal stack parameters of the obscured metal stack definition to obtain a tuned metal stack definition. The metal stack tuning engine may do so by generating sampled metal stack definitions, constructing sampled layout geometries from the sampled metal stack definitions, computing parasitic capacitance value sets for the sampled layout geometries, and determining tuned values for the selected metal stack parameters through a curve fitting process. The tuned metal stack application engine may be configured to use the tuned metal stack definition to perform a parasitic capacitance extraction process for an input IC design.

Abstract: Various embodiments provide for routing a circuit design using routing congestion based on fractional via cost, via density, or both in view of one or more design rules. For instance, some embodiments model via cost based on one or more design rules to determine routing congestion, where routing demand (e.g., routing capacity occupied by) of a via is fractional to the amount of the track blocked by the via. Additionally, some embodiments apply via density modeling based on one or more design rules to determine a routing demand of a via for routing congestion.

Abstract: Aspects described herein relate to physical verification of a design of an integrated circuit to be manufactured on a semiconductor die. One example method involves inserting a virtual partition cell in a parent cell of a layout of a design of an integrated circuit. A child cell of the parent cell has a first portion that overlaps the virtual partition cell and a second portion that is outside of the virtual partition cell. The method also includes creating, by one or more processors, a hierarchy of cells having the child cell and the virtual partition cell descending from the parent cell, wherein the child cell has multiple instances in the hierarchy of cells, and performing a design rule check runset on the parent cell based on the hierarchy.

Abstract: A device for inductively charging an electronic accessory includes a first portion, a second portion, and a spacer. The first portion includes a first transmission coil in a first plane where the first transmission coil is configured to generate a first magnetic field, and the second portion includes a first transmission coil in a second plane where the second transmission coil is configured to generate a second magnetic field. The spacer is positioned between the first transmission coil and the second transmission coil and between the first plane and the second plane. The spacer material magnetically insulates the second transmission coil from the first magnetic field.

Abstract: A circuit design in a hierarchical description is analyzed. The analysis comprises identifying electrical properties of circuit blocks in the circuit design. Circuit components of the circuit design are associated with geometric elements of a layout design. Then instances of each of the circuit blocks are classified into groups of instances based on the electrical properties. Rule checking is performed on one or more groups in the groups of instances for each of the circuit blocks by analyzing geometric elements associate with components of one instance for each of the one or more groups.

Abstract: A method includes providing a first design layout including cells; updating a first cell in the plurality of cells using optical proximity correction to provide a first updated cell and a data set; training a model based on a layout-dependent parameter of a second design layout; and updating a second cell based on the data set and the model to provide a second updated cell. The model includes an input layer, a hidden layer and an output layer. Training the model includes obtaining converged values of nodes of the hidden layer. Obtaining converged values of nodes of the hidden layer includes providing information on edge segments before and after lithography enhancement to the input layer and the output layer, respectively, until values of nodes of the hidden layer attains convergence in terms of a cost function.

Abstract: Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.

Abstract: In an embodiment, a method includes: receiving data representative of an electrical circuit including an arrangement of devices, inputs, outputs, and power sources; determining a minimum number of segments based on the received data; grouping the devices into N segments based on common features shared between two or more of the devices, where N is equal to the minimum number of segments; and generating discrete portions of the grouped devices to form a physical layout representative of a physical manifestation of the electrical circuit, such that when the discrete portions are integrated together they form a physical manifestation of the electrical circuit.

Abstract: Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes parameter settings for the design tool. The design tool executes multiple implementation flows using different sets of strategies to generate alternative implementations. One implementation of the alternative implementations nearest to satisfying a timing requirement is selected.

Abstract: An approach is disclosed herein for balancing layer densities in using an automated process. The approach disclosed herein operates on a region-by-region and layer-by-layer basis to perform parameterized layer balancing. In some embodiments, the process comprises determining densities of respective layers in respective regions, evaluating each layer and region to determine whether operations need to be taken to balance those layers in the corresponding regions, determining what those actions should be, and then implementing those actions. Additionally, in some embodiments, the process may operate in different orders and may be associated with a looping flow until a layout being processed has been balanced.