Abstract: Provided is a layout design method including designing a preliminary layout including a source/drain contact pattern of an integrated circuit device, designing a first layout including a cut pattern for cutting the source/drain contact pattern, designing a second layout configured by excluding a pattern overlapping the pattern of the first layout from the preliminary layout, and correcting the preliminary layout by reflecting an etch skew based on at least one parameter of the second layout.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a patterned photoresist layer over a substrate and removing the patterned photoresist layer using a photoresist stripping composition that is free of dimethyl sulfoxide. The photoresist stripping composition includes an organic alkaline compound including at least one of a primary amine, secondary amine, a tertiary amine or a quaternary ammonium hydroxide or a salt thereof, an organic solvent selected from the group consisting of a glycol ether, a glycol acetate, a glycol, a pyrrolidone and mixtures thereof, and a polymer solubilizer.

Abstract: A method of selective metal removal via gradient oxidation for a gap-fill includes performing process cycles, each process cycle including placing a wafer having a semiconductor structure thereon into a first processing station, the semiconductor structure including a dielectric layer patterned with a feature formed therein and a seed layer formed on sidewalls and a bottom surface of the feature and a top surface of the dielectric layer, performing a reduction process on the wafer in the first processing station, performing a gradient oxidation process on the wafer in the second processing station, performing a gradient etch process on the wafer in the third processing station, and performing the gradient etch process on the wafer in the fourth processing station, wherein the first, second, third, and fourth processing stations are located in an interior volume of a processing chamber.

Abstract: An ion energy for plasma processing of a dielectric substrate is determined by exposing the dielectric substrate to a plasma discharge and applying a pulsed voltage waveform. This waveform includes a sequence of pulses, each having a higher voltage interval and a lower voltage interval having a voltage slope. First pulses of the sequence having differing voltage slopes are generated and applied to the dielectric substrate. For each first pulse, the voltage slope and a corresponding output current are determined. For each first pulse, at least one coefficient of a mathematical relation between the voltage slope and the corresponding output current based solely on the voltage slope and the output current determined for one or more of the first pulses is determined. A test function is applied and an optimal voltage slope value corresponding to the at least one coefficient making the test function true is selected.

Abstract: A plasma etching system generates a plasma above a wafer in a plasma etching chamber. The wafer is surrounded by a focus ring. The plasma etching system straightens a plasma sheath above the focus ring by generating a supplemental electric field above the focus ring.

Abstract: A composition for selectively etching a layer including an aluminum compound in the presence of a layer of a low-k material and/or a layer including copper and/or cobalt, and a corresponding process, are described. Further described is a process for the manufacture of a semiconductor device, including the step of selectively etching at least one layer including an aluminum compound in the presence of a layer of a low-k material and/or a layer including copper and/or cobalt by contacting the at least one layer including an aluminum compound with the described composition.

Abstract: A plasma processing apparatus or method that improves the yield of wafer processing, including a sample stand on which the wafer is mounted; plural heaters which are arranged in three or more regions in the radial direction including a circular region concentrically arranged around the center and ring-like regions surrounding the outer periphery on plural radii in the radial direction from the center toward the outer peripheral side, and which include one arranged in each of plural arc-like regions divided in the circumferential direction around the center of at least one of the ring-like regions; plural temperature sensors arranged in the radial direction and the number of which is smaller than that of heaters; and a control unit which adjusts the output of each of the plural heaters according to the output from the temperature sensor so that the temperature of the sample stand becomes closer to a target value.

Abstract: According to one embodiment, a pattern forming method includes forming an organic film on a processing target material, the organic film comprising a convex part and a remaining film part adjacent to the convex part and thinner than the convex part. The method further includes irradiating the organic film with an electron beam to decrease a dry etching rate of the organic film. The method further includes removing the remaining film part by dry etching of the organic film. The method further includes forming a pattern on the processing target material by dry etching using the organic film from which the remaining film part has been removed as a mask.

Abstract: The present invention relates to the technical field of conductivity measurement electrode preparation, and specifically discloses a method for manufacturing a high-precision marine conductivity measurement electrode based on screen printing. The method of the present invention can realize the preparation of a conductivity measurement electrode with high precision, short preparation time and less drop-out of the electrode, thereby meeting the requirements of the current marine observation network for the high-volume and high-precision application of the conductivity sensor.

Abstract: Various embodiments herein relate to apparatuses and methods for distortion of pulses for wafer biasing. In some embodiments, a method is provided, the method comprising: causing a distorted pulse to be applied to an electrode of a pedestal such that the distorted pulse at least partially compensates for attenuation between the pedestal and the substrate, and such that a waveform resulting from the distorted pulse, when imparted to the substrate, is substantially square.

Abstract: A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one rheology modifier. The slurry includes at least one liquid carrier, at least one abrasives and at least one oxidizer. The rheology modifier is dispensed in the slurry. The polishing method includes using the slurry composition with the rheology modifier to polish a conductive layer.

Abstract: A plasma processing method includes: (a) mounting a substrate including a first mask layer, which is a removal target, formed on a first layer with a metal-containing layer that is included therein to be partially exposed, on a stage disposed inside a processing container of the plasma processing apparatus; (b) supplying a process gas containing one or more of fluorocarbon gas and hydrofluorocarbon gas into the processing container; (c) supplying a first radio-frequency power that forms a plasma from the process gas into the processing container; (d) supplying a second radio-frequency power having a frequency lower than a frequency of the first radio-frequency power to the stage after a predetermined time is elapsed from stop of the first radio-frequency power; and (e) repeating (c) and (d).

Abstract: Alignment aid structures and the method of formation of these structures on an interposer comprised of a planar waveguide layer and a base structure, facilitate the alignment of the optical axes of optical and optoelectrical devices formed from and mounted to the interposer. Alignment aids formed from a common hard mask on the planar waveguide layer of the interposer structure include vertical and lateral alignment structures and fiducials. Optical losses for signals propagating in interposer-based photonic integrated circuits are reduced with effective alignment structures and methods.

Abstract: Methods and systems for thinning a device wafer to tens of micron, micron, or sub-micron thicknesses are disclosed. Device wafers are thinned by using a two-step grinding process and a chemical mechanical polish (CMP) process. One or more first grinding parameters associated with the first grinding process are determined, received, and/or adjusted before and/or during the performance of the first grinding process. One or more second grinding parameters associated with the second grinding process are determined, received and/or adjusted before and/or during the performance of the second grinding process. One or more polishing parameters associated with the CMP process are determined and/or adjusted before and/or during the performance of the CMP process.

Abstract: A method of processing a substrate includes receiving a substrate including a photoresist film including exposed and unexposed portions, etching parts of the unexposed portions of the photoresist film with a developing gas in a process chamber to leave a residual part of the unexposed portions, and purging the developing gas from the process chamber with a purging gas. After purging the developing gas, the residual part of the unexposed portions is etched with the developing gas. The substrate is etched using exposed portions of the photoresist film as a mask.

Abstract: A method of producing a printed circuit board includes providing a base substrate that is a film or plate, has first and second substrate sides and consists partly of an electrically non-conducting organic polymer material, where the first substrate side is covered with a capping metal layer, and regionally removing the capping metal layer, wherein regionally removing the capping metal layer includes applying a mask layer to the capping metal layer, regionally removing the mask layer by a laser so that the first substrate side is divided into at least one first subregion, in which the first substrate side is covered only with the capping metal layer, and into at least one second subregion, in which the first substrate side is covered with the capping metal layer and by the mask layer, and removing the capping metal layer in the at least one first subregion by an etching solution.

Abstract: There is provided a method for manufacturing a structure, including: applying a first etching to a surface of a member, at least the surface being composed of Group III nitride; and applying a second etching to the surface to which the first etching has been applied, wherein in applying the first etching, a flat portion and a protruding portion are formed, the flat portion being newly appeared on the surface by etching, and the protruding portion being raised with respect to the flat portion, which is caused by being less likely to be etched than the flat portion, and in applying the second etching, the protruding portion is lowered by etching the protruding portion.

Abstract: A method for performing an etch process on a substrate includes applying a bias signal and a source signal to an electrode of a plasma processing system. The bias signal and the source signal are pulsed RF signals that together define a repeated pulsed RF cycle, wherein each pulsed RF cycle sequentially includes a first state, a second state, a third state, and a fourth state. The power level of the bias signal in the first state is greater than in the third state, which is greater than in the second state, which is greater than in the fourth state. The power level of the source signal in the first state is greater than in the third state, which is greater than in the second state, which is greater than in the fourth state.

Abstract: The present disclosure provides improved wet etch processes and methods for etching noble metals. More specifically, the present disclosure provides various embodiments of wet etch processes and methods that utilize new etch chemistries for etching noble metals, such as ruthenium (Ru), gold (Au), platinum (Pt) and iridium (Ir), in a wet etch process. In general, the disclosed embodiments expose a noble metal surface to a first etch solution to chemically modify the noble metal surface and form a noble metal salt passivation layer, which can then be selectively dissolved in a second etch solution to etch the noble metal surface.

Abstract: An object of the present invention is to provide a treatment liquid having excellent resist film removal performance and excellent residue removal performance. Another object of the present invention is to provide a treatment method. The treatment liquid of an embodiment of the present invention is a treatment liquid containing an alkali compound and a hydroxycarboxylic acid, in which abrasive particles are not substantially contained, and a content mass ratio of a content of the hydroxycarboxylic acid to a content of the alkali compound is 0.001 and 1.0.