Patents Examined by Binh X Tran
  • Patent number: 12290900
    Abstract: Methods and systems for thinning a device wafer to tens of micron, micron, or sub-micron thicknesses are disclosed. Device wafers are thinned by using a two-step grinding process and a chemical mechanical polish (CMP) process. One or more first grinding parameters associated with the first grinding process are determined, received, and/or adjusted before and/or during the performance of the first grinding process. One or more second grinding parameters associated with the second grinding process are determined, received and/or adjusted before and/or during the performance of the second grinding process. One or more polishing parameters associated with the CMP process are determined and/or adjusted before and/or during the performance of the CMP process.
    Type: Grant
    Filed: March 27, 2023
    Date of Patent: May 6, 2025
    Assignee: Qorvo US, Inc.
    Inventors: Krishna Chetry, Ganesan Radhakrishnan
  • Patent number: 12289837
    Abstract: A method of producing a printed circuit board includes providing a base substrate that is a film or plate, has first and second substrate sides and consists partly of an electrically non-conducting organic polymer material, where the first substrate side is covered with a capping metal layer, and regionally removing the capping metal layer, wherein regionally removing the capping metal layer includes applying a mask layer to the capping metal layer, regionally removing the mask layer by a laser so that the first substrate side is divided into at least one first subregion, in which the first substrate side is covered only with the capping metal layer, and into at least one second subregion, in which the first substrate side is covered with the capping metal layer and by the mask layer, and removing the capping metal layer in the at least one first subregion by an etching solution.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: April 29, 2025
    Assignee: Gebr. Schmid GmbH
    Inventors: Christian Buchner, Jürgen Haungs, Christian Schmid
  • Patent number: 12287578
    Abstract: A method of processing a substrate includes receiving a substrate including a photoresist film including exposed and unexposed portions, etching parts of the unexposed portions of the photoresist film with a developing gas in a process chamber to leave a residual part of the unexposed portions, and purging the developing gas from the process chamber with a purging gas. After purging the developing gas, the residual part of the unexposed portions is etched with the developing gas. The substrate is etched using exposed portions of the photoresist film as a mask.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: April 29, 2025
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hamed Hajibabaeinajafabadi, Akiteru Ko, Yu-Hao Tsai, Sergey Voronin
  • Patent number: 12283487
    Abstract: There is provided a method for manufacturing a structure, including: applying a first etching to a surface of a member, at least the surface being composed of Group III nitride; and applying a second etching to the surface to which the first etching has been applied, wherein in applying the first etching, a flat portion and a protruding portion are formed, the flat portion being newly appeared on the surface by etching, and the protruding portion being raised with respect to the flat portion, which is caused by being less likely to be etched than the flat portion, and in applying the second etching, the protruding portion is lowered by etching the protruding portion.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: April 22, 2025
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Fumimasa Horikiri, Noboru Fukuhara
  • Patent number: 12276915
    Abstract: An object of the present invention is to provide a treatment liquid having excellent resist film removal performance and excellent residue removal performance. Another object of the present invention is to provide a treatment method. The treatment liquid of an embodiment of the present invention is a treatment liquid containing an alkali compound and a hydroxycarboxylic acid, in which abrasive particles are not substantially contained, and a content mass ratio of a content of the hydroxycarboxylic acid to a content of the alkali compound is 0.001 and 1.0.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: April 15, 2025
    Assignee: FUJIFILM Corporation
    Inventor: Tetsuya Kamimura
  • Patent number: 12278112
    Abstract: A method for performing an etch process on a substrate includes applying a bias signal and a source signal to an electrode of a plasma processing system. The bias signal and the source signal are pulsed RF signals that together define a repeated pulsed RF cycle, wherein each pulsed RF cycle sequentially includes a first state, a second state, a third state, and a fourth state. The power level of the bias signal in the first state is greater than in the third state, which is greater than in the second state, which is greater than in the fourth state. The power level of the source signal in the first state is greater than in the third state, which is greater than in the second state, which is greater than in the fourth state.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: April 15, 2025
    Assignee: Lam Research Corporation
    Inventors: Aniruddha Joi, Nikhil Dole, Merrett Wong, Eric Hudson, Jay Sheth
  • Patent number: 12276033
    Abstract: The present disclosure provides improved wet etch processes and methods for etching noble metals. More specifically, the present disclosure provides various embodiments of wet etch processes and methods that utilize new etch chemistries for etching noble metals, such as ruthenium (Ru), gold (Au), platinum (Pt) and iridium (Ir), in a wet etch process. In general, the disclosed embodiments expose a noble metal surface to a first etch solution to chemically modify the noble metal surface and form a noble metal salt passivation layer, which can then be selectively dissolved in a second etch solution to etch the noble metal surface.
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: April 15, 2025
    Assignee: Tokyo Electron Limited
    Inventor: Paul Abel
  • Patent number: 12272526
    Abstract: A substrate processing method includes: (a) providing a substrate including an etching target film and a mask formed on the etching target film and having an opening; (b) forming a first layer containing a nitrogen atom and a hydrogen atom by using a first processing gas, on a side wall of a recess that is formed in the etching target film corresponding to the opening; (c) after (b), modifying the first layer into a second layer by using a second processing gas containing a halogen-containing gas; and (d) after (c), etching the recess by using a third processing gas.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: April 8, 2025
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tsukasa Hirayama, Taku Gohira
  • Patent number: 12269969
    Abstract: The invention provides a chemical-mechanical polishing composition comprising (a) an abrasive comprising ceria particles, (b) a cationic polymer selected from a cationic homopolymer, a cationic copolymer comprising at least one cationic monomer and at least one nonionic monomer, and a combination thereof, (c) a quaternary ammonium salt or a quaternary phosphonium salt, and (d) water, wherein the polishing composition has a pH of about 5 to about 8. The invention also provides a method of chemically-mechanically polishing a substrate, especially a substrate comprising silicon oxide, silicon nitride and/or polysilicon by contacting the substrate with the inventive chemical-mechanical polishing composition.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: April 8, 2025
    Assignee: CMC MATERIALS LLC
    Inventors: Benjamin Petro, Juyeon Chang, Brittany Johnson
  • Patent number: 12259656
    Abstract: A structured membrane fabrication method begins with a membrane wafer on a substrate and at least one thin-film on the membrane wafer such that portions of the membrane wafer are exposed. The exposed portions of the membrane wafer and each thin-film are covered with an acetone-inert protectant. Portions of the protectant are etched through to the membrane wafer while each thin-film remains fully covered by the protectant. A handle is coupled to the protectant with a wax that dissolves in acetone. Portions of the substrate are then removed to define and expose a contiguous region of the membrane wafer adjacent to each thin-film and the portions of the protectant so-etched. The wax is exposed to acetone so that it dissolves. The contiguous region of the membrane wafer is then etched through at the portions of the protectant so-etched. The protectant is then removed.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: March 25, 2025
    Assignee: United States of America as represented by the Administrator of NASA
    Inventors: Elissa Williams, Kevin Denis, Hsiang-Yu Liu
  • Patent number: 12261055
    Abstract: The method includes receiving a semiconductor device having a first surface and a second surface. The first surface is a top surface including a conductive material exposed thereon; and the second surface is an embedded surface including the conductive material and a dielectric material. The method also includes selecting a first polishing slurry to achieve a first polishing rate of the conductive material in the first polishing slurry and a second polishing rate of the dielectric material in the first polishing slurry. The method further includes selecting a second polishing slurry to achieve a third polishing rate of the conductive material in the second polishing slurry and a fourth polishing rate of the dielectric material in the second polishing slurry. The method additionally includes polishing the first surface with the first polishing slurry until the second surface is exposed; and polishing the second surface with the second polishing slurry.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: March 25, 2025
    Assignee: TAIWAN SSEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: An-Hsuan Lee, Chun-Hung Liao, Chen-Hao Wu, Shen-Nan Lee, Teng-Chun Tsai, Huang-Lin Chao
  • Patent number: 12261044
    Abstract: Various embodiments herein relate to methods, apparatus, and systems that utilize a multi-layer hardmask in the context of patterning a semiconductor substrate using extreme ultraviolet photoresist. The multi-layer hardmask includes (1) an upper layer that includes a metal-containing material such as a metal oxide, a metal nitride, or a metal oxynitride, and (2) a lower layer that includes an inorganic dielectric silicon-containing material. Together, these layers of the multi-layer hardmask provide excellent etch selectivity and reduce formation of defects such as microbridges and line breaks. Certain embodiments relate to deposition of the multi-layer hardmask. Other embodiments relate to etching of the multi-layer hardmask. Some embodiments involve both deposition and etching of the multi-layer hardmask.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: March 25, 2025
    Assignees: Lam Research Corporation, International Business Machines Corporation
    Inventors: Bhaskar Nagabhirava, Phillip Friddle, Ekimini Anuja De Silva, Jennifer Church, Dominik Metzler, Nelson Felix
  • Patent number: 12249514
    Abstract: Fabricating a semiconductor substrate by (a) vertical etching a feature having sidewalls and a depth into one or more layers formed on the semiconductor substrate and (b) depositing an amorphous carbon liner onto the sidewalls of the feature. Steps (a) and optionally (b) are iterated until the vertical etch feature has reached a desired depth. With each iteration of (a), the feature is vertical etched deeper into the one or more layers, while the amorphous carbon liner resists lateral etching of the sidewalls of the feature. With each optional iteration of (b), the deposited amorphous carbon liner on the sidewalls of the feature is replenished.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: March 11, 2025
    Assignee: Lam Research Corporation
    Inventors: Jon Henri, Karthik S. Colinjivadi, Francis Sloan Roberts, Kapu Sirish Reddy, Samantha Siamhwa Tan, Shih-Ked Lee, Eric Hudson, Todd Shroeder, Jialing Yang, Huifeng Zheng
  • Patent number: 12237175
    Abstract: Methods of patterning vias and trenches using a polymerization protective liner after forming a lower patterned mask layer used for etching trenches on a semiconductor substrate prior to forming an upper patterned mask layer used for etching vias are provided. Methods involve forming a polymerization protective liner either nonconformally or conformally using silicon tetrachloride and methane polymerization. Polymerization protective liners may be sacrificial.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: February 25, 2025
    Assignees: Lam Research Corporation, International Business Machines Corporation
    Inventors: Bhaskar Nagabhirava, Phillip Friddle, Michael Goss, Yann Mignot, Dominik Metzler
  • Patent number: 12226873
    Abstract: A method for processing a silicon wafer, the method including cutting an ingot to form a wafer, extracting from measured shape data a cross-sectional profile, the cross-sectional profile passing through the center of the wafer and being aligned with a cutting direction of an ingot, interpolating the shape data with a fixed and pre-determined step size, fitting a first second-degree polynomial to the cross-sectional profile, determining a residual profile by subtracting the polynomial from the cross-sectional profile, fitting a second second-degree polynomial to the residual profile using a sliding window of pre-determined width to determine a position, height, and curvature of each peak and valley of the residual profile, determining a waviness parameter based on the position, height, and curvature of each peak and valley of the residual profile, and further processing the wafer based on the waviness parameter and a predetermined waviness threshold.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: February 18, 2025
    Assignee: SILTRONIC CORPORATION
    Inventors: Andrei Istratov, Tom Wu, Katharina Zahnweh
  • Patent number: 12217968
    Abstract: A method for etching a surface including obtaining a substrate comprising a material; reacting a surface of a substrate with a reactant, comprising a gas or a plasma, to form a reactive layer on the substrate, the reactive layer comprising a chemical compound including the reactant and the material; and wet etching or dissolving the reactive layer with a liquid wet etchant of solvent that selectively etches or dissolves the reactive layer but not the substrate.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: February 4, 2025
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventor: Harold Frank Greer
  • Patent number: 12215417
    Abstract: A predetermined process is performed on two target substrates using a substrate processing device that includes two processing parts for performing a substrate process on each of the two target substrates, a gas supply mechanism for separately supplying gases to the two processing parts, and a common exhaust mechanism for collectively exhausting the gases inside the two processing parts. A first mode is executed in which an HF gas and an NH3 gas are supplied to one of the two processing parts, and the HF gas is not supplied to the other of the two processing parts. Subsequently, a second mode is executed in which the HF gas and the NH3 gas are supplied to the two processing parts under the same gas conditions. In the first mode, a pressure difference is prevented from occurring between the two processing parts.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: February 4, 2025
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Satoshi Toda, Tetsuro Takahashi
  • Patent number: 12205844
    Abstract: A method for processing a semiconductor wafer is provided. The method includes placing a first semiconductor wafer on a wafer chuck in a process chamber. The method further includes adjusting a distance between a gas dispenser positioned above the wafer chuck and an upper edge ring surrounding the wafer chuck. The method also includes producing a plasma for processing the first semiconductor wafer by exciting a gas dispenser from the gas dispenser after the adjustment. In addition, the method includes removing the first semiconductor wafer from the process chamber.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huang-Shao Ko, Jui-Fu Hsieh, Chih-Teng Liao, Chih-Ching Cheng
  • Patent number: 12201392
    Abstract: A method of reprocessing a surgical instrument includes flowing a flow of irrigation fluid through an accessory drive device operably coupled to the surgical instrument, the accessory drive device comprising inflatable bladders, and the flow of irrigation fluid causing inflation of the bladders. The method further includes converting inflation of the bladders to motion of an input drive member of the surgical instrument; converting the motion of the input drive member to motion of an actuation element of the surgical instrument; converting the motion of the actuation element to motion of a distal component of the surgical instrument; and irrigating the surgical instrument with the flow of irrigation fluid.
    Type: Grant
    Filed: June 22, 2023
    Date of Patent: January 21, 2025
    Assignee: INTUITIVE SURGICAL OPERATIONS, INC.
    Inventor: Timothy Allen Limon
  • Patent number: 12203166
    Abstract: An apparatus and method for cleaning or etching a molybdenum film or a molybdenum nitride film from an interior of a reaction chamber in a reaction system are disclosed. A remote plasma unit is utilized to activate a halide precursor mixed with an inert gas source to form a radical gas. The radical gas reacts with the molybdenum film or the molybdenum nitride film to form a by-product that is removed from the interior of the reaction chamber by a purge gas.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: January 21, 2025
    Assignee: ASM IP Holding B.V.
    Inventors: Amit Mishra, Bhushan Zope, Shankar Swaminathan, Theodorus G. M. Oosterlaken