Abstract: A semiconductor device includes; a semiconductor substrate including a chip area and a scribe lane area, a low-k layer on the semiconductor substrate, an interlayer insulating layer on the low-k layer, a trench area in the scribe lane area, a gap-fill insulating layer in the trench area and vertically extending from the semiconductor substrate through the low-k layer and the interlayer insulating layer to expose an upper surface of the gap-fill insulating layer through the interlayer insulating layer, and a first metal liner covering a side surface of the gap-fill insulating layer and disposed between the gap-fill insulating layer and the low-k layer and between the gap-fill insulating layer and the interlayer insulating layer.

Abstract: A method for forming a chip package structure is provided. The method includes forming a first molding layer surrounding a first chip structure. The method includes disposing a second chip structure over the first chip structure and the first molding layer. The method includes forming a second molding layer surrounding the second chip structure and over the first chip structure and the first molding layer. The method includes forming a third molding layer surrounding the first molding layer and the second molding layer. The method includes disposing a third chip structure over the second chip structure, the second molding layer and the third molding layer. The method includes forming a fourth molding layer surrounding the third chip structure and over the second chip structure, the second molding layer, and the third molding layer.

Abstract: A semiconductor device is an IGBT of a trench-gate structure and has a storage region directly beneath a p?-type base region. The semiconductor device has gate trenches and dummy trenches as trenches configuring the trench-gate structure. An interval (mesa width) at which the trenches are disposed is in a range of 0.7 ?m to 2 ?m. In each of the gate trenches, a gate electrode of a gate potential is provided via a first gate insulating film. In each of the dummy trenches, a dummy gate electrode of an emitter potential is provided via a second gate insulating film. A total number of the gate electrode is in a range of 60% to 84% of a total number of the dummy electrodes.

Abstract: The invention relates to various aspects of a ?-LED or a ?-LED array for augmented reality or lighting applications, in particular in the automotive field. The ?-LED is characterized by particularly small dimensions in the range of a few ?m.

Abstract: A display device includes: a first base layer; a circuit element layer on the first base layer; a pixel definition layer on the circuit element layer and comprising a plurality of light-emitting openings which are spaced apart from each other and define a plurality of light-emitting regions; a second base layer spaced apart from and facing the first base layer; a light-shielding layer on the second base layer and comprising a plurality of openings respectively overlapping the light-emitting regions, wherein on a plane of the first base layer, shapes of first to third openings along one direction among the openings are different from each other.

Abstract: An electronic apparatus includes: an electronic panel comprising a display unit comprising a plurality of pixels and a sensing unit comprising a plurality of sensing electrodes; and an electronic module overlapping with the electronic panel when viewed in a plan view, the sensing unit comprising: a base substrate comprising a hole area overlapping with the electronic module, an active area overlapping with the sensing electrodes, and a peripheral area adjacent to the active area; a connection line in the hole area and connected to a portion of the sensing electrodes; and a conductive light blocking pattern in the hole area and spaced apart from the connection line and the sensing electrodes.

Abstract: Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (Vt). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vt within the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.

Abstract: A monolithic semiconductor device includes: a substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer; a first transistor disposed on the substrate and including the first nitride semiconductor layer and the second nitride semiconductor layer, the first transistor being of a high-electron-mobility transistor (HEMT) type for power amplification; and a first bias circuit disposed on the substrate and including a second transistor of the HEMT type disposed outside a propagation path of a radio-frequency signal inputted to the first transistor, the first bias circuit applying bias voltage to a gate of the first transistor.

Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, organic light-emitting elements, a data line, and an electrode line. The organic light-emitting element includes a first electrode, a light-emitting layer and a second electrode sequentially stacked; the data line is located between the base substrate and the organic light-emitting element; the electrode line is on the same layer as the data line and located in a region outside a light-emitting region of the organic light-emitting element. The display substrate further includes at least one connection portion, which is in the region outside the light-emitting region and is configured to connect the electrode line and the first electrode, the connection portion is spaced apart from the second electrode, and the light-emitting layer covers the second electrode and the at least one connection portion.

Abstract: An array structure of capacitors are provided. The array structure of capacitors includes a substrate and a first connection pad, a second connection pad, a first capacitive structure and a second capacitive structure that are disposed on the substrate. The first capacitive structure is disposed outside the second capacitive structure and adjacent to an edge of the substrate. The bottom surface of the first capacitive structure towards the substrate and the top surface of the first connection pad are disposed at intervals.

Abstract: A method includes receiving a workpiece having a first stack of semiconductor layers in a first region and a second stack of semiconductor layers in a second region; forming a first gate dielectric layer surrounding each layer of the first stack and a second gate dielectric layer surrounding each layer of the second stack; forming a first dipole layer surrounding the first gate dielectric layer and merging between vertically adjacent portions of the first gate dielectric layer, and a second dipole layer surrounding the second gate dielectric layer and merging between vertically adjacent portions of the second gate dielectric layer; removing the first dipole layer; after the removing of the first dipole layer, conducting a first annealing on the workpiece; removing a remaining portion of the second dipole layer; and forming a gate electrode layer in the first region and the second region.

Abstract: A light emitting display panel and a light emitting display apparatus including the same, in which a cathode is connected to an auxiliary cathode electrode through an undercut region provided under a planarization layer, are provided. The light emitting display panel includes a substrate, an auxiliary cathode electrode provided in the substrate, a passivation layer covering the auxiliary cathode electrode, an anode provided on the passivation layer, a bank surrounding an outer portion of the anode, a light emitting layer provided on the anode, and a cathode provided on the light emitting layer, the cathode is connected to the auxiliary cathode electrode through a connection electrode exposed at an undercut region passing through the bank and the passivation layer.

Abstract: Provided is a semiconductor device. The semiconductor device includes a floating gate disposed on a substrate; a memory gate disposed on the floating gate; a first spacer disposed sidewalls of the floating gate and the memory gate, and an upper surface of the substrate; a second spacer disposed on the first spacer; a select high-k film disposed on a first portion of a sidewall of the first spacer between the substrate and the second spacer; and a select gate disposed on a second portion of the sidewall of the first spacer between the substrate and the second spacer. A width of a portion of the first spacer is reduced as a distance to the substrate decreases, and the portion of the first spacer is disposed between the substrate and the second spacer.

Abstract: For small, high-resolution, light-emitting diode (LED) displays, such as for a near-eye display in an artificial-reality headset, LEDs are spaced closely together. A backplane can be used to drive an array of LEDs in an LED display. A plurality of interconnects electrically couple the backplane with the array of LEDs. The backplane can have a different coefficient of thermal expansion (CTE) than the array of LEDs. During bonding of the backplane to the array of LEDs, CTE mismatch can cause misalignment of bonding sites. The higher the bonding temperature, the greater the misalignment of bonding sites. Lower temperature bonding, using materials with lower melting or bonding temperatures, can be used to mitigate misalignment during bonding so that interconnects can be more closely spaced, which can allow LEDs to be more closely spaced, to enable a higher-resolution display.

Abstract: A method of forming a semiconductor device. The method includes forming a first well of a first-type in a substrate of a second-type, forming a first active zone of the first-type in a second well of the second-type on the substrate, and forming a second active zone of the second-type in the first-type well. The method also includes forming a first pick-up region of the first-type located in the first well, and forming a second pick-up region of the second-type located in the second well. Each of the first active zone and the second active zone extends in a first direction. The first pick-up region and the second pick-up region are separated from each other, by the first active zone and the second active zone, along a direction that is different from the first direction.

Abstract: A floating-node memory device includes a metal-oxide-semiconductor (MOS) transistor including a first polysilicon gate, a source region, and a drain region in a first well region, a tunneling device including a second polysilicon gate in a second well region, and a metal-insulator-metal (MIM) capacitor including a conductive top plate and a bottom plate formed in a metal interconnect layer. The floating-node device includes a floating-node comprising the first polysilicon gate, the second polysilicon gate, and the conductive top plate of the MIM capacitor coupled together, a control node at the bottom plate of the MIM capacitor, an erase node in the second well region, a source node at the source region of the MOS transistor, and a drain node at the drain region of the MOS transistor.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.

Abstract: An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

Abstract: An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

Abstract: A mounting board includes a base portion and a frame portion. The base portion includes a first upper surface including a first mounting region. The frame portion includes a second upper surface including a second mounting region and an inner wall surface intersecting with the second upper surface. The inner wall surface of the frame portion includes a first portion connecting with the second upper surface, and a second portion located opposite to the first portion with the first mounting region interposed therebetween. In the second portion, a first film that absorbs light and having a reflectance lower than a reflectance of the inner wall surface of the frame portion is located.