Abstract: A semiconductor device includes a substrate, a first active fin on the substrate, the first active fin including a first side surface and a second side surface opposing the first side surface, a second active fin on the substrate, the second active fin including a third side surface facing the second side surface and a fourth side surface opposing the third side surface of the second active fin, a first isolation layer on the first side surface of the first active fin, a second isolation layer between the second side surface of the first active fin and the third side surface of the second active fin, a third isolation layer on the fourth side surface of the second active fin and a merged source/drain on the first and second active fins.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a first principal surface on one side and a second principal surface on the other side, the semiconductor layer in which a device formation region and an outer region outside the device formation region are set, a channel region of a second conductivity type formed in a surface layer portion of the first principal surface of the semiconductor layer in the device formation region, an emitter region of a first conductivity type formed in a surface layer portion of the channel region, a gate electrode formed at the first principal surface of the semiconductor layer in the device formation region, the gate electrode facing the channel region across a gate insulating film, a collector region of a second conductivity type formed in a surface layer portion of the second principal surface of the semiconductor layer in the device formation region, an inner cathode region of a first conductivity type formed in the surface layer po

Abstract: Disclosed are a display panel and a display device. The display panel includes a substrate and multiple organic light-emitting units located in the display region on a first side of the substrate, where an area of at least one of organic light-emitting units in the second display region is smaller than an area of each of organic light-emitting units with a same light-emitting color in the first display region, and/or, density of the organic light-emitting units in the first display region is greater than density of the organic light-emitting units in the second display region. The second display region includes at least one quantum dot light-emitting unit, which does not overlap the organic light-emitting units; and each of the at least one quantum dot light-emitting unit emits light of a same color as at least one of the organic light-emitting units located in the second display region.

Abstract: A resistive random access memory (RRAM) device is provided. The RRAM device includes a gate structure on a substrate, and a source region and a drain region disposed on opposite sides of the gate structure on the substrate. The source region includes a semiconductor bulk, and the drain region includes a plurality of semiconductor fins adjacent to the semiconductor bulk, wherein the semiconductor fins are separated from each other by an isolation layer. The RRAM device further includes a plurality of RRAM units, wherein each of the RRAM units electrically contacts one of the semiconductor fins.

Abstract: A detection panel, a manufacturing method thereof and a photo detection device are provided. The detection panel includes a plurality of detection pixel units in an array, the detection pixel unit includes a reflective structure on a base substrate, a detection circuit and a photoelectric conversion structure on the reflective structure; the photoelectric conversion structure includes a first electrode, a photodiode and a second electrode stacked sequentially, and the first electrode is electrically connected with the detection circuit, and the first electrode is an optically transparent electrode, and an orthographic projection of the reflective structure on the base substrate at least covers an orthographic projection of the photodiode on the base substrate.

Abstract: Methods and precursors for depositing silicon nitride films by atomic layer deposition (ALD) are provided. In some embodiments the silicon precursors comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%).

Abstract: Crystalline material, phototransistor, and methods of fabrication thereof. The crystalline material comprising a plurality of stacked two-dimensional black phosphorous carbide layers.

Abstract: A hybrid particle according to the present invention includes an inorganic core particle, an electron transport layer covering a surface of the inorganic core particle, and a light absorption layer covering the electron transport layer. The light absorption layer contains a compound having an organic-inorganic hybrid perovskite crystal structure or a metal complex. The compound or the metal complex is grown in a crystalline form on a surface of the electron transport layer.

Abstract: A semiconductor device includes a plurality of first wires formed in a first layer, a plurality of second wires formed to intersect the plurality of first wires in a second layer stacked on the first layer, a plurality of first vias formed at intersections of the plurality of first wires and the plurality of second wires, and an inductor formed in a third layer stacked on the first layer and the second layer.

Abstract: An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

Abstract: A resistor element encompasses a first resistive layer, a first protection strip implemented by a tandem connection of p-n junctions, an interlayer insulating film covering the first resistive layer and the first protection strip, a first external electrode on the interlayer insulating film, being connected to a terminal of the first resistive layer and a terminal of the first protection strip, and a second external electrode on the interlayer insulating film, being connected to another terminal of the first resistive layer and another terminal of the first protection strip.

Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, an opaque support (e.g., a ring-shaped solder mask) disposed on the sensor chip, and a light permeable layer disposed on the opaque support. The sensor chip includes a sensing region. The opaque support surrounds the sensing region, and inner lateral sides of the opaque support form a light-scattering loop wall. The light permeable layer, the light-scattering loop wall of the opaque support, and the sensor chip jointly define an enclosed space therein. When light passes through the light permeable layer and impinges onto the light-scattering loop wall at an incident angle, the light-scattering loop wall scatters the light into multiple rays at angles different from the incident angle.

Abstract: The present disclosure relates to an electroluminescent lighting device having high aperture ratio. The present disclosure provides an electroluminescent light device comprising: a substrate including an emission area and a non-emission area surrounding the emission area; a power line disposed in the emission area and defining an open area; a buffer layer covering the power line; an emission element disposed in the open area on the buffer layer; a link electrode overlapping the power line on the buffer layer, and having a first end connected to the emission element and a second end connected to the power line; a passivation layer deposited within a width of the power line covering the link electrode; an emission layer covering the emission area; and a cathode layer covering the emission area on the emission layer.

Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

Abstract: The present invention discloses a semiconductor structure of an image sensor, an associated chip and an electronic apparatus. The semiconductor structure includes a semiconductor substrate, and a plurality of pixel groups disposed on the bottom of the semiconductor substrate. Each of the pixel groups includes: a first pixel and a second pixel located in the same row and being adjacent to each other, and a third pixel and a fourth pixel located in another row and being adjacent to each other, wherein the first pixel and the third pixel are disposed diagonally. Each of the pixels includes four sub-pixels, and the four sub-pixels of each pixel share a floating diffusion region and the floating diffusion region is surrounded by photodetectors of the four sub-pixels.

Abstract: An embodiment of the present disclosure provides an array substrate and a display panel. The array substrate includes a base substrate, organic electroluminescence components arranged on the base substrate in an array, and a photoelectric conversion component corresponding to each of the organic electroluminescence components. A luminescent spectrum of each organic electroluminescence component comprises a first waveband and a second waveband. The first waveband is determined by an emission peak of the luminescent spectrum, and is used to determine brightness and tone purity of light emitted by the organic electroluminescence component. The photoelectric conversion component is at least used to convert light of the second waveband emitted by a corresponding organic electroluminescence component into electric energy.

Abstract: The present disclosure provides a method that includes providing an integrated circuit (IC) substrate having various devices and an interconnection structure that couples the devices to an integrated circuit; forming a first passivation layer on the IC substrate; forming a redistribution layer on the first passivation layer, the redistribution layer being electrically connected to the interconnection structure; forming a second passivation layer on the redistribution layer and the first passivation layer; forming a polyimide layer on the second passivation layer; patterning the polyimide layer, resulting in a polyimide opening in the polyimide layer; and etching the second passivation layer through the polyimide opening using the polyimide layer as an etch mask.

Abstract: An integrated circuit (IC) device includes a line structure including a conductive line formed on a substrate and an insulation capping pattern that covers the conductive line; an insulation spacer covering a sidewall of the line structure; a conductive plug spaced apart from the conductive line in a first horizontal direction with the insulation spacer between the conductive plug and the conductive line; a conductive landing pad arranged on the conductive plug to vertically overlap the conductive plug; and a capping layer including a first portion between the conductive landing pad and the insulation capping pattern, wherein the first portion of the capping layer has a shape in which a width in the first horizontal direction gradually increases as a distance from the substrate increases between the conductive landing pad and the insulation capping pattern.

Abstract: A method of manufacturing a curved-surface detector includes: slimming a sensor substrate having photoelectric devices arranged therein to a predetermined thickness; seating the sensor substrate slimmed to the predetermined thickness on a jig curved so as to have a curved-surface shape such that the sensor substrate is curved so as to have a curved-surface shape; and joining a flexible scintillator substrate configured to emit light when being struck by radiation to an upper surface of the sensor substrate such that curvature of the sensor substrate curved so as to have a curved-surface shape by the jig is maintained.

Abstract: A method includes forming a trench in a low-K dielectric layer, where the trench exposes an underlying contact area of a substrate. A first tantalum nitride (TaN) layer is conformally deposited within the trench, where the first TaN layer is deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD). A tantalum (Ta) layer is deposited on the first TaN layer conformally within the trench, where the Ta layer is deposited using physical vapor deposition (PVD). An electroplating process is performed to deposit a conductive layer over the Ta layer. A via is formed over the conductive layer, where forming the via includes depositing a second TaN layer within the via and in contact with the conductive layer.