Abstract: A method includes receiving a workpiece having a first stack of semiconductor layers in a first region and a second stack of semiconductor layers in a second region; forming a first gate dielectric layer surrounding each layer of the first stack and a second gate dielectric layer surrounding each layer of the second stack; forming a first dipole layer surrounding the first gate dielectric layer and merging between vertically adjacent portions of the first gate dielectric layer, and a second dipole layer surrounding the second gate dielectric layer and merging between vertically adjacent portions of the second gate dielectric layer; removing the first dipole layer; after the removing of the first dipole layer, conducting a first annealing on the workpiece; removing a remaining portion of the second dipole layer; and forming a gate electrode layer in the first region and the second region.

Abstract: A light emitting display panel and a light emitting display apparatus including the same, in which a cathode is connected to an auxiliary cathode electrode through an undercut region provided under a planarization layer, are provided. The light emitting display panel includes a substrate, an auxiliary cathode electrode provided in the substrate, a passivation layer covering the auxiliary cathode electrode, an anode provided on the passivation layer, a bank surrounding an outer portion of the anode, a light emitting layer provided on the anode, and a cathode provided on the light emitting layer, the cathode is connected to the auxiliary cathode electrode through a connection electrode exposed at an undercut region passing through the bank and the passivation layer.

Abstract: Provided is a semiconductor device. The semiconductor device includes a floating gate disposed on a substrate; a memory gate disposed on the floating gate; a first spacer disposed sidewalls of the floating gate and the memory gate, and an upper surface of the substrate; a second spacer disposed on the first spacer; a select high-k film disposed on a first portion of a sidewall of the first spacer between the substrate and the second spacer; and a select gate disposed on a second portion of the sidewall of the first spacer between the substrate and the second spacer. A width of a portion of the first spacer is reduced as a distance to the substrate decreases, and the portion of the first spacer is disposed between the substrate and the second spacer.

Abstract: For small, high-resolution, light-emitting diode (LED) displays, such as for a near-eye display in an artificial-reality headset, LEDs are spaced closely together. A backplane can be used to drive an array of LEDs in an LED display. A plurality of interconnects electrically couple the backplane with the array of LEDs. The backplane can have a different coefficient of thermal expansion (CTE) than the array of LEDs. During bonding of the backplane to the array of LEDs, CTE mismatch can cause misalignment of bonding sites. The higher the bonding temperature, the greater the misalignment of bonding sites. Lower temperature bonding, using materials with lower melting or bonding temperatures, can be used to mitigate misalignment during bonding so that interconnects can be more closely spaced, which can allow LEDs to be more closely spaced, to enable a higher-resolution display.

Abstract: A method of forming a semiconductor device. The method includes forming a first well of a first-type in a substrate of a second-type, forming a first active zone of the first-type in a second well of the second-type on the substrate, and forming a second active zone of the second-type in the first-type well. The method also includes forming a first pick-up region of the first-type located in the first well, and forming a second pick-up region of the second-type located in the second well. Each of the first active zone and the second active zone extends in a first direction. The first pick-up region and the second pick-up region are separated from each other, by the first active zone and the second active zone, along a direction that is different from the first direction.

Abstract: A floating-node memory device includes a metal-oxide-semiconductor (MOS) transistor including a first polysilicon gate, a source region, and a drain region in a first well region, a tunneling device including a second polysilicon gate in a second well region, and a metal-insulator-metal (MIM) capacitor including a conductive top plate and a bottom plate formed in a metal interconnect layer. The floating-node device includes a floating-node comprising the first polysilicon gate, the second polysilicon gate, and the conductive top plate of the MIM capacitor coupled together, a control node at the bottom plate of the MIM capacitor, an erase node in the second well region, a source node at the source region of the MOS transistor, and a drain node at the drain region of the MOS transistor.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.

Abstract: An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

Abstract: An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

Abstract: A mounting board includes a base portion and a frame portion. The base portion includes a first upper surface including a first mounting region. The frame portion includes a second upper surface including a second mounting region and an inner wall surface intersecting with the second upper surface. The inner wall surface of the frame portion includes a first portion connecting with the second upper surface, and a second portion located opposite to the first portion with the first mounting region interposed therebetween. In the second portion, a first film that absorbs light and having a reflectance lower than a reflectance of the inner wall surface of the frame portion is located.

Abstract: The disclosure provides a light detection substrate, a manufacturing method thereof and a light detection apparatus. The light detection substrate includes a plurality of light detection units, each of the light detection units includes a first electrode, a second electrode and a photoelectric conversion layer, a spacer region exists between orthographic projections of the first electrode and the second electrode on a substrate, the photoelectric conversion layer is provided with at least one opening, and an orthographic projection of the at least one opening on the substrate is located in the spacer region.

Abstract: A method for manufacturing a magnetic random access memory array incudes forming a source region within a surface of a substrate, forming an array of three-dimensional (3D) structures over the substrate, each 3D structure being separated from an adjacent 3D structure by a cavity region, depositing a channel material on a surface of at least one sidewall of each 3D structure, depositing a gate dielectric material over the channel material on the surface of the at least one sidewall of each 3D structure, forming a first isolation region in each cavity region between adjacent 3D structures over the substrate, and forming a first gate region over the first isolation region in each cavity region.

Abstract: There is provided a semiconductor device including a first electrode including a first plate portion, the first plate portion including a first surface and a second surface facing the first surface, a plurality of semiconductor chips provided above the second surface, and a second electrode including a second plate portion provided above the semiconductor chips, the second plate portion including a third surface facing the second surface and a fourth surface facing the third surface, the second plate portion including a plurality of protrusion portions provided between the semiconductor chips and the third surface, the protrusion portions being connected to the third surface, each of the protrusion portions including a top surface including the same shape as a shape of each of the semiconductor chips in a plane parallel to the second surface, the second plate portion including a second outer diameter larger than a first diameter of a smallest circle circumscribing the protrusion portions provided on an outerm

Abstract: A photoelectric conversion device includes a semiconductor substrate, a photoelectric conversion unit, an amplification transistor, and an insulating isolation portion. The photoelectric conversion unit is disposed inside the semiconductor substrate. The amplification transistor is configured to output a signal from the photoelectric conversion unit. The insulating isolation portion, disposed between the photoelectric conversion unit and the amplification transistor to surround the amplification transistor in a plan view, is configured to penetrate through the semiconductor substrate. A first well in which the amplification transistor is disposed is connected to a source or a drain of the amplification transistor.

Abstract: The present invention discloses a light sensing unit of a light sensing device including a light sensing element and a switching element. The light sensing element includes a gate, a semiconductor layer, a gate insulating layer, a source, and a drain. The gate and the semiconductor layer are disposed on a substrate, the gate insulating layer separates the gate from the semiconductor layer, and the source and the drain are connected to the semiconductor layer respectively. At least one of the source and the drain are formed of a light-transmissive conductive layer. The semiconductor layer is disposed between one of the source and the drain and the gate, and when viewed along a normal direction of the substrate, the gate overlaps the one of the source and the drain, and the gate does not overlap another one of the source and the drain.

Abstract: A light emitting element includes: an n-side semiconductor layer made of a nitride semiconductor; a p-side semiconductor layer made of a nitride semiconductor; and an active layer disposed between the n-side semiconductor and the p-side semiconductor layer and having a multi-quantum well structure in which a plurality of nitride semiconductor well layers and a plurality of nitride semiconductor barrier layers are alternately stacked, wherein the light emitting element includes, between at least one of the plurality of well layers and the barrier layer disposed adjacent thereto on the p-side semiconductor side: a first layer and a second layer disposed successively from the well layer side.

Abstract: An organic molecular memory of embodiments includes: a first electrode; a second electrode; an organic molecular layer provided between the first electrode and the second electrode, extending in a first direction from the first electrode toward the second electrode, and containing a first molecule and a second molecule provided between the first molecule and the second electrode; and a third electrode facing the second molecule.

Abstract: This application provides a display, an electronic device, and a display fabrication method.

Abstract: A method of manufacturing a chip scale light-emitting diode package is provided. The method of manufacturing chip scale light-emitting diode package includes: manufacturing a lens molding sheet including intaglios on one surface thereof; forming a lens layer having lens portions on one surface thereof and a flat surface on a surface opposite thereto by applying a light-transmitting resin to the intaglios; forming an adhesive layer on the flat surface of the lens layer; arranging light-emitting diode chips, each having a first surface and a second surface opposite to the first surface, on the adhesive layer in such a way that the light-emitting diode chips correspond to the lens portions and the second surface is attached to the adhesive layer, wherein a first electrode pad and a second electrode pad are formed on the first surface; and manufacturing a chip array sheet by forming a molding part on the adhesive layer to cover outer surfaces of the light-emitting diode chips.

Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.