Patents Examined by Bitew A Dinke
  • Patent number: 11460835
    Abstract: Some embodiments of the present BOP control systems include a system controller configured to actuate a first BOP function by communicating one or more commands to one or more nodes of a functional pathway selected from one or more available functional pathways associated with the first BOP function, each node comprising an actuatable component configured to actuate in response to a command received from the system controller, each node having one or more sensors configured to capture a first data set corresponding to actuation of the component and a processor configured to analyze the first data set to determine a useful life remaining of the component and/or compare the first data set to a second data set corresponding to a simulation of actuation of the component.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: October 4, 2022
    Assignee: TRANSOCEAN INNOVATION LABS LTD.
    Inventors: John Matthew Dalton, Luis Pereira
  • Patent number: 11450762
    Abstract: A semiconductor device is an IGBT of a trench-gate structure and has a storage region directly beneath a p?-type base region. The semiconductor device has gate trenches and dummy trenches as trenches configuring the trench-gate structure. An interval (mesa width) at which the trenches are disposed is in a range of 0.7 ?m to 2 ?m. In each of the gate trenches, a gate electrode of a gate potential is provided via a first gate insulating film. In each of the dummy trenches, a dummy gate electrode of an emitter potential is provided via a second gate insulating film. A total number of the gate electrode is in a range of 60% to 84% of a total number of the dummy electrodes.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: September 20, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tohru Shirakawa
  • Patent number: 11424290
    Abstract: According to one embodiment, a variable resistance element includes a first electrode, a second electrode, and a variable resistance layer and a tellurium-containing compound layer disposed between the first electrode and the second electrode. The tellurium-containing compound layer contains tellurium, oxygen, and at least one element selected from tin, copper, and bismuth. In some examples, the tellurium-containing compound layer can function as a switching layer in a memory cell structure.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: August 23, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Hiroki Kawai, Daisuke Watanabe, Toshihiko Nagase
  • Patent number: 11417854
    Abstract: A plurality of light-emitting devices (10) include a plurality of light-emitting devices (10a), a plurality of light-emitting devices (10b), and a plurality of light-emitting devices (10c). The plurality of light-emitting devices (10) are aligned on a reflecting member (20). Six light-emitting devices (10c) are aligned in a straight line along one direction. Four light-emitting devices (10b) are aligned surrounding a region facing one ends of the six light-emitting devices (10c). Each of four light-emitting devices (10a) are aligned with each of the four light-emitting devices (10b) outside the four light-emitting devices (10b).
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: August 16, 2022
    Assignee: PIONEER CORPORATION
    Inventors: Takeru Okada, Chihiro Harada, Ayako Yoshida, Takashi Chuman
  • Patent number: 11417829
    Abstract: A three dimensional magnetic random access memory array that includes a sourceline formed on a substrate and a magnetic memory element pillar that includes a plurality of magnetic memory element pillars formed over the substrate. The three dimensional magnetic random access memory array also includes a transistor formed between the magnetic memory element pillar, the transistor being functional to electrically connect the sourceline and magnetic memory element pillar. A plurality of magnetic memory element pillars may be formed over the substrate with a transistor between each memory element pillar to selectively connect or disconnect each of the magnetic memory element pillars. The transistor can include an epitaxial semiconductor structure having a gate dielectric formed at a side of the epitaxial semiconductor and a gate material formed on the gat dielectric such that the gate dielectric material is between the gate material and the semiconductor material.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: August 16, 2022
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Kuk-Hwan Kim, Dafna Beery, Amitay Levi, Andrew J. Walker
  • Patent number: 11404577
    Abstract: A method includes forming a dielectric cap over a semiconductor substrate; forming a dummy gate structure over the dielectric cap; forming gate spacers on opposite sidewalls of the dummy gate structure and on a top surface of the dielectric cap; removing the dummy gate structure to form a gate trench between the gate spacers and exposing the dielectric cap; and performing an ion implantation to form a doped region in the semiconductor substrate through the dielectric cap.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Tai-Yuan Wang
  • Patent number: 11404443
    Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: August 2, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taejoong Song, Ha-Young Kim, Jung-Ho Do, Sanghoon Baek, Jinyoung Lim, Kwangok Jeong
  • Patent number: 11398512
    Abstract: A photo-sensing device includes a semiconductor substrate, a photosensitive device, a dielectric layer and a light pipe. The photosensitive device is in the semiconductor substrate. The dielectric layer is over the semiconductor substrate. The light pipe is over the photosensitive device and embedded in the dielectric layer. The light pipe includes a curved and convex light-incident surface.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: July 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chia-Chan Chen
  • Patent number: 11393857
    Abstract: An image sensor (32) includes a plurality of pixel sensing portion (320) that are arranged in columns and rows. Each of the pixel sensing portions (320) includes a thin film transistor (11), and a photodetection diode (13) including n-type (16), intrinsic (15), and p-type semiconductor layers (14). The intrinsic semiconductor layer (15) of the photodetection diode (13) of each of the pixel sensing portions (320) has a crystallinity gradient that varies from an amorphous silicon structure to a microcrystalline silicon structure along a first direction (L1) extending from the p-type semiconductor layer (14) toward the n-type semiconductor layer (16). An image sensing-enabled display apparatus (3) and a method of making the image sensor (32) are also disclosed.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: July 19, 2022
    Assignee: SHANGHAI HARVEST INTELLIGENCE TECHNOLOGY CO., LTD.
    Inventors: Hong-Yih Tseng, Jiandong Huang
  • Patent number: 11387392
    Abstract: A light-emitting device includes: a semiconductor stacked body comprising a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer stacked in this order; a first insulating film that covers the active layer and the second conductive semiconductor layer; a first conductive layer that continuously surrounds a lateral surface of the first conductive semiconductor layer that is exposed from the first insulating film; a second insulating film that covers the first conductive layer, the active layer, and the second conductive semiconductor layer and that has a hole disposed above the second conductive semiconductor layer; and a second conductive layer that continuously covers, via the second insulating film, an end portion of the first conductive layer located in proximity to an end portion of the second conductive semiconductor layer, wherein the second conductive layer is connected to an upper surface of the second conductive semiconductor layer through the hole.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 12, 2022
    Assignee: NICHIA CORPORATION
    Inventor: Yukitoshi Marutani
  • Patent number: 11373926
    Abstract: The load force bolster assembly includes a metallic stiffener. A carrier associated with a CPU (Central Processing Unit) is located upon the load force bolster assembly and positioned upon the electrical connector. A heat sink is located upon both the carrier and the load force bolster assembly wherein a torsioned wire of the bolster assembly provides a downward force upon an up-and-down movable stud which is secured to a screw of the heat sink so as to downwardly push the heat sink, thus enhancing the normal forces among the heat sink, the CPU and the contacts of the electrical connector. To efficiently hold the torsioned wire in position around a bottom corner of the stiffener, a retention groove is formed around the top portion of the restricting pole, and a pressing ring is downwardly snapped into the retention groove so as to restrain the torsioned wire in position.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: June 28, 2022
    Assignees: FOXCONN (KUNSHAN) COMPUTER CONNECTOR CO., LTD., FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventor: Albert Harvey Terhune, IV
  • Patent number: 11366401
    Abstract: Techniques, systems, and devices are disclosed for implementing a photoconductive device performing bulk conduction. In one exemplary aspect, a photoconductive device is disclosed. The device includes a light source configured to emit light; a crystalline material positioned to receive the light from the light source, wherein the crystalline material is doped with a dopant that forms a mid-gap state within a bandgap of the crystalline material to control a recombination time of the crystalline material; a first electrode coupled to the crystalline material to provide a first electrical contact for the crystalline material, and a second electrode coupled to the crystalline material to provide a second electrical contact for the crystalline material, wherein the first and the second electrodes are configured to establish an electric field across the crystalline material, and the crystalline material is configured to exhibit a substantially linear transconductance in response to receiving the light.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: June 21, 2022
    Assignees: LAWRENCE LIVERMORE NATIONAL SECURITY, LLC, OPCONDYS, INC.
    Inventors: Stephen Sampayan, Paulius Vytautas Grivickas, Kristin Cortella Sampayan
  • Patent number: 11362273
    Abstract: An electronic device includes a semiconductor memory. A method for fabricating the electronic device includes forming a first memory cell extending vertically from a surface of substrate and having a first upper portion that protrudes laterally, forming a second memory cell extending vertically from the surface of the substrate and having a second upper portion that protrudes laterally towards the first upper portion, and forming a liner layer over the first and second memory cells, the liner layer having a first portion disposed over the first upper portion and a second portion disposed over the second upper portion, the first and second portions of the liner layer contacting each other.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: June 14, 2022
    Assignee: SK hynix Inc.
    Inventors: Hyo-June Kim, Hyun-Seok Kang, Chi-Ho Kim, Jae-Geun Oh
  • Patent number: 11355708
    Abstract: The present disclosure relates to the field of manufacturing displays, and provides a method for manufacturing a display substrate, a method for manufacturing a mask plate, and a display device. The method for manufacturing a display substrate comprises: providing a first substrate; providing a mask plate opposite to the first substrate, the mask plate comprising one or more light-transmissive regions, and an electrically conductive material is provided on a surface of the mask plate facing the first substrate; and irradiating a surface of the mask plate facing away from the first substrate with light rays, such that the electrically conductive material is transferred to a surface of the first substrate facing the mask plate, thereby forming an electrically conductive layer having one or more electrically conductive portions, wherein a projection of each of the one or more electrically conductive portions on the mask plate coincides with a respective light-transmissive region.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: June 7, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Shengji Yang, Xue Dong, Xiaochuan Chen, Hui Wang
  • Patent number: 11355538
    Abstract: The present disclosure provides an image sensor panel (ISP) and a method for fabricating the image sensor panel (ISP). In one aspect, the method includes forming a well in an assembly, forming a bottom electrode in the well, forming a photosensitive layer in the well, and forming a top electrode over the photosensitive layer.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: June 7, 2022
    Assignee: Bidirectional Display, Inc.
    Inventors: Hsuanyeh Chang, Zachary Michael Thomas
  • Patent number: 11349052
    Abstract: For small, high-resolution, light-emitting diode (LED) displays, such as for a near-eye display in an artificial-reality headset, LEDs are spaced closely together. A backplane can be used to drive an array of LEDs in an LED display. A plurality of interconnects electrically couple the backplane with the array of LEDs. The backplane can have a different coefficient of thermal expansion (CTE) than the array of LEDs. During bonding of the backplane to the array of LEDs, CTE mismatch can cause misalignment of bonding sites. The higher the bonding temperature, the greater the misalignment of bonding sites. Lower temperature bonding, using materials with lower melting or bonding temperatures, can be used to mitigate misalignment during bonding so that interconnects can be more closely spaced, which can allow LEDs to be more closely spaced, to enable a higher-resolution display.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: May 31, 2022
    Assignee: Facebook Technologies, LLC
    Inventors: Daniel Henry Morris, John Goward, Chloe Astrid Marie Fabien, Michael Grundmann
  • Patent number: 11342323
    Abstract: A semiconductor die with high-voltage tolerant electrical overstress circuit architecture is disclosed. One embodiment of the semiconductor die includes a signal pad, a ground pad, a core circuit electrically connected to the signal pad, and a stacked thyristor protection device. The stacked thyristor includes a first thyristor and a resistive thyristor electrically connected in a stack between the signal pad and the ground pad, which enhances the holding voltage of the circuit relatively to an implementation with only the thyristor. Further, the resistive thyristor includes a PNP bipolar transistor and a NPN bipolar transistor that are cross-coupled, and an electrical connection between a collector of the PNP bipolar transistor and a collector of the NPN bipolar transistor. This allows the resistive thyristor to exhibit both thyristor characteristics and resistive characteristics based on a level of current flow.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: May 24, 2022
    Assignee: Analog Devices, Inc.
    Inventors: Javier A. Salcedo, Linfeng He
  • Patent number: 11335868
    Abstract: A flexible substrate, as well as a method of preparing the same, and a display panel are disclosed. The flexible substrate includes: a base substrate; a first light-emitting element and an optical filter disposed on the base substrate. The optical filter is configured to receive the first light beam emitted by the first light-emitting element and filter the first light beam to obtain a second light beam, and configured to enable physical properties of the second light beam to be modulated by a bending degree of the flexible substrate at a position where the optical filter is located.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: May 17, 2022
    Assignees: CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jianbo Fu, Dan Tang, Hailong Wu, Yi Dan, Dalong Mao, Haipeng Zhu, Yan Zhou, Yanlin Han
  • Patent number: 11335750
    Abstract: The present invention provides an organic light-emitting diode (OLED) display panel and an OLED display device. The OLED display panel comprises a light transmission area and a display area surrounding a periphery of the light transmission area; a concave groove is disposed in the OLED display panel corresponding to the light transmission area, and the concave groove penetrates through at least an encapsulation layer, a light emitting function layer and a part of a thin film transistor (TFT) structure layer; and at least a part of a touch function layer extends from the display area toward the concave groove and covers the concave groove.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: May 17, 2022
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Jiangjiang Jin
  • Patent number: 11322638
    Abstract: Various embodiments of a monolithic avalanche photodiode (APD) are described, which may be fabricated on a silicon-on-insulator substrate. The monolithic APD includes an optical waveguide that guides an incident light to an active region of the APD. An optical coupler is integrally formed with the optical waveguide to capture the incident light. The monolithic APD also includes an optical reflector to reflect a portion of the incident light that is not readily captured by the optical coupler back to the optical coupler for further capturing. The active region includes an absorption layer for converting the incident light into a photocurrent, an epitaxial structure for amplifying the photocurrent by avalanche multiplication, as well as a pair of electrical conductors for conducting the amplified photocurrent.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 3, 2022
    Inventors: Mengyuan Huang, Tzung-I Su, Te-huang Chiu, Zuoxi Li, Ching-yin Hong, Dong Pan