Patents Examined by Bradley Smith
  • Patent number: 11562899
    Abstract: A method for transferring a thin layer onto a destination substrate having a face with an adhesive layer includes formation of a polymer material interface layer on a second face of a thin layer, opposite a first face on which an adhesive is present. The method also includes assembly by gluing the interface layer and the adhesive layer and separation of the thin layer relative to a temporary support.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: January 24, 2023
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Pierre Montmeat, Frank Fournel
  • Patent number: 11559915
    Abstract: Method and calculating unit for curve sawing of a block in a cutting direction with at least a first circular saw blade. The method comprises determining a radius of the curve sawing, by measuring the curvature of the block in the direction of cutting; calculating a vertical inclination angle of the first circular saw blade in a vertical plane relative to the cutting direction in the block, based on the determined radius of the curve sawing; inclining the first circular saw blade with the calculated vertical inclination angle; and sawing the block in the cutting direction with the inclined first circular saw blade along the determined radius of the curve sawing.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: January 24, 2023
    Assignee: USNR AB
    Inventor: Mats Ekevad
  • Patent number: 11557594
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of creating at least one trench in a substrate; depositing a conductive material to partially fill the trench; and forming an insulative piece in the trench and extending into the conductive material.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: January 17, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Wei Huang
  • Patent number: 11557580
    Abstract: A mass transfer method includes providing a transfer unit and a semiconductor carrying unit connected therewith, removing an element supporting structure of the semiconductor carrying unit from micro semiconductor elements of the semiconductor carrying unit, partially removing the photosensitive layer to form connecting structures, connecting a package substrate with electrodes of the micro semiconductor elements, breaking the connecting structures to separate the micro semiconductor elements from the transfer substrate. A mass transfer device is also disclosed.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: January 17, 2023
    Assignee: Xiamen Sanan Optoelectronics Technology Co., Ltd.
    Inventors: Zhibai Zhong, Chia-En Lee, Jinjian Zheng, Jiansen Zheng, Chen-Ke Hsu, Junyong Kang
  • Patent number: 11557513
    Abstract: A method for fabricating a semiconductor device includes forming a first wiring layer, the first wiring layer including a first metal wiring and a first interlayer insulating film wrapping the first metal wiring on a substrate, forming a first via layer, the first via layer including a first via that is in electrical connection with the first metal wiring, and a second interlayer insulating film wrapping the first via on the first wiring layer, and forming a second wiring layer, the second wiring layer including a second metal wiring that is in electrical connection with the first via, and a third interlayer insulating film wrapping the second metal wiring on the first via layer, wherein the third interlayer insulating film contains deuterium and is formed through chemical vapor deposition using a first gas containing deuterium and a second gas containing hydrogen.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: January 17, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon Keun Kim, Jae Wha Park, Jun Kwan Kim, Hyo Jeong Moon, Seung Jong Park, Seul Gi Bae
  • Patent number: 11557570
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer on a substrate, an N-type doped semiconductor layer on the sacrificial layer, and a dielectric stack on the N-type doped semiconductor layer are subsequently formed. A channel structure extending vertically through the dielectric stack and the N-type doped semiconductor layer is formed. The dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the N-type doped semiconductor layer. The substrate and the sacrificial layer are removed to expose an end of the channel structure. Part of the channel structure abutting the N-type doped semiconductor layer is replaced with a semiconductor plug.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: January 17, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Kun Zhang, Wenxi Zhou, Zhiliang Xia, Zongliang Huo
  • Patent number: 11552214
    Abstract: A lift-off method includes a relocation substrate joining step of joining a relocation substrate to a surface of an optical device layer of an optical device wafer with a joining member interposed therebetween, thereby forming a composite substrate, a buffer layer breaking step of applying a pulsed laser beam having a wavelength transmittable through an epitaxy substrate and absorbable by a buffer layer to the buffer layer from a reverse side of the epitaxy substrate of the optical device wafer of the composite substrate, thereby breaking the buffer layer, and an optical device layer relocating step of peeling off the epitaxy substrate from the optical device layer, thereby relocating the optical device layer to the relocation substrate. In the buffer layer breaking step, irradiating conditions of the pulsed la-ser beam are changed for respective ring-shaped areas of the buffer layer, and the pulsed laser beam is applied to the optical device wafer under the changed irradiating conditions.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: January 10, 2023
    Assignee: DISCO CORPORATION
    Inventors: Tasuku Koyanagi, Junya Mimura
  • Patent number: 11545402
    Abstract: A semiconductor wafer according to the present embodiment is a semiconductor wafer having a first face. A plurality of chip structures are provided on a plurality of chip regions of the first face. A test structure is provided on dicing regions between adjacent ones of the chip regions. The chip structures each comprise first integrated circuits provided on the semiconductor wafer, and a first stacked body provided above the first integrated circuits and including a plurality of first layers and a plurality of second layers different from the first layers alternately stacked. The test structure comprises second integrated circuits provided on the semiconductor wafer, and a second stacked body provided above the second integrated circuits and including the first layers and the second layers alternately stacked.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: January 3, 2023
    Assignee: Kioxia Corporation
    Inventors: Hiromitsu Harashima, Yasushi Kameda
  • Patent number: 11545464
    Abstract: Embodiments described herein provide techniques for testing a semiconductor package by using a diode to couple a test pad to a contact pad. In one scenario, a package comprises a die stack comprising one or more dies and a molding compound encapsulating the die stack. In this package, a substrate is over the molding compound. Also, a test pad and a contact pad are on a surface of the substrate. The contact pad is coupled to the die stack. A diode couples the test pad to the contact pad. In one example, the test pad is coupled to a P side of the diode's P-N junction and the contact pad is coupled to an N side of the diode's P-N junction. In operation, current can flow from the test pad through the contact pad (and the die stack), but current cannot flow from the contact pad through the test pad.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 3, 2023
    Assignee: Intel Corporation
    Inventors: Yi Xu, Hyoung Il Kim, Florence Pon
  • Patent number: 11535931
    Abstract: There is provided a technique that includes executing a process recipe for processing a substrate; and executing a correction recipe for checking a characteristic value of a supply valve installed at a process gas supply line, wherein the act of executing the correction recipe comprises: supplying an inert gas into the process gas supply line for a certain period of time in a state where an adjusting valve that is installed at an exhaust portion of a process furnace and adjusts an internal pressure of the process furnace is fully opened; detecting a pressure value in a supply pipe provided with the supply valve while supplying the inert gas into the process gas supply line in the state where the adjusting valve is fully opened; and calculating the characteristic value of the supply valve based on the detected pressure value.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: December 27, 2022
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Masaya Nishida, Nobuhito Shima, Akihiro Sato, Yosuke Kuwata, Kenichi Maeda
  • Patent number: 11538681
    Abstract: An epitaxy substrate and a method of manufacturing the same are provided. The epitaxy substrate includes a silicon substrate and a silicon carbide layer. The silicon substrate has a first surface and a second surface opposite to each other, and the first surface is an epitaxy surface. The silicon carbide layer is located in the silicon substrate, and a distance between the silicon carbide layer and the first surface is between 100 angstroms (?) and 500 angstroms.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: December 27, 2022
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Ying-Ru Shih, Chih-Yuan Chuang, Chun-I Fan, Wen-Ching Hsu
  • Patent number: 11532540
    Abstract: A method includes forming a buffer dielectric layer over a carrier, and forming a first dielectric layer and a first redistribution line over the buffer dielectric layer. The first redistribution line is in the first dielectric layer. The method further includes performing a planarization on the first dielectric layer to level a top surface of the first dielectric layer, forming a metal post over and electrically coupling to the first redistribution line, and encapsulating the metal post in an encapsulating material. The encapsulating material contacts a top surface of the planarized top surface of the first dielectric layer.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo, Chen-Hua Yu
  • Patent number: 11532589
    Abstract: In one embodiment, a semiconductor wafer includes a first substrate, a first insulator provided on the first substrate, and a plurality of first pads provided in the first insulator. The wafer further includes a second insulator provided on the first insulator, a plurality of second pads provided on the first pads in the second insulator, a stacked film alternately including a plurality of first insulating layers and a plurality of second insulating layers provided in the second insulator, and a second substrate provided on the second insulator. Furthermore, the first insulator and the second insulator are connected to each other between an edge face of the first insulator and an edge face of the second insulator, and the second insulator intervenes between the first insulator and the stacked film at the edge faces of the first and second insulators.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: December 20, 2022
    Assignee: Kioxia Corporation
    Inventors: Jun Iijima, Hiroshi Nakaki
  • Patent number: 11532576
    Abstract: A manufacturing method of a semiconductor package includes the following steps. Semiconductor chips are disposed on a carrier. The semiconductor chips are grouped in a plurality of package units. The semiconductor chips are encapsulated in an encapsulant to form a reconstructed wafer. A redistribution structure is formed on the encapsulant. The redistribution structure electrically connects the semiconductor chips within a same package unit of the plurality of package units. The individual package units are separated by cutting through the reconstructed wafer along scribe line regions. In the reconstructed wafer, the plurality of package units are arranged so as to balance the number of scribe line regions extending across opposite halves of the reconstructed wafer in a first direction with respect to the number of scribe line regions extending across opposite halves of the reconstructed wafer in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Yi-Che Chiang
  • Patent number: 11527688
    Abstract: An electronic device is provided in the present disclosure. The electronic device includes a substrate and a light emitting diode. The light emitting diode is bonded to the substrate through a solder alloy. The solder alloy includes tin and a metal element M, and the metal element M is one of the indium and bismuth. The atomic percentage of tin in the sum of tin and the metal element M ranges from 60% to 90% in the solder alloy.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: December 13, 2022
    Assignee: InnoLux Corporation
    Inventors: Ming-Chang Lin, Tzu-Min Yan
  • Patent number: 11524383
    Abstract: An end of polishing of a wafer is determined for each of wafers at a high accuracy. A wafer processing method includes: a first process of acquiring an initial state of a processing target surface of a wafer; a second process of forming a coating film on the wafer after the first process; a third process of polishing the processing target surface of the wafer by a polishing member based on initial polishing conditions in a state where the polishing member is in contact with the processing target surface of the wafer; a fourth process of acquiring a processed state of the processing target surface of the wafer after the third process; and a fifth process of determining an end of polishing, an insufficiency in polishing, or an excess in polishing based on the initial state and the processed state.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: December 13, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Minoru Kubota, Hideharu Kyouda
  • Patent number: 11521902
    Abstract: Vertical field-effect transistor (VFET) devices and methods of forming the devices are provided. The methods may include forming a channel region including a first channel region and a second channel region, forming a first cavity in the substrate, forming a first bottom source/drain in the first cavity, forming a second cavity in the substrate, and forming a second bottom source/drain in the second cavity. The first cavity may expose a lower surface of the first channel region, and the second cavity may expose a lower surface of the second channel region. The method may also include after forming the first bottom source/drain and the second bottom source/drain, removing a portion of the channel region between the first channel region and the second channel region to separate the first channel region from the second channel region.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: December 6, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sa Hwan Hong, Yong Hee Park, Kang Ill Seo
  • Patent number: 11521959
    Abstract: A method includes bonding a first device die to a second device die, encapsulating the first device die in a first encapsulant, performing a backside grinding process on the second device die to reveal through-vias in the second device die, and forming first electrical connectors on the second device die to form a package. The package includes the first device die and the second device die. The method further includes encapsulating the first package in a second encapsulant, and forming an interconnect structure overlapping the first package and the second encapsulant. The interconnect structure comprises second electrical connectors.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: December 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua Yu, Hung-Yi Kuo, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Yuan Yu, Ming Hung Tseng
  • Patent number: 11515288
    Abstract: A method includes providing a die having a contact pad on a top surface and forming a conductive protective layer over the die and covering the contact pad. A molding compound is formed over the die and the conductive protective layer. The conductive protective layer is exposed using a laser drilling process. A redistribution layer (RDL) is formed over the die. The RDL is electrically connected to the contact pad through the conductive protective layer.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Chuan Chang, Tsei-Chung Fu, Jing-Cheng Lin
  • Patent number: 11515444
    Abstract: Disclosed are a micro light emitting diode substrate, a manufacturing method thereof, and a display device. At first step, providing a first growth substrate having a first growth surface which is provided with a first color micro light emitting diode unit; at second step, providing a receiving substrate having a receiving surface on which a plurality of receiving pads are arranged at intervals; at third step, fitting the first growth substrate to the receiving substrate such that each first color micro light emitting diode unit at a transfer position is fitted to one receiving pad; at fourth step, fixing the first color micro light emitting diode unit to the receiving surface through the receiving pad; at fifth step, peeling off the first color micro light emitting diode unit from the first growth substrate, to obtain the receiving substrate on which the first color micro light emitting diode unit is fixed.
    Type: Grant
    Filed: December 29, 2018
    Date of Patent: November 29, 2022
    Assignee: ELEC-TECH PHOTOELECTRIC TECHNOLOGY (DALIAN) CO., LTD.
    Inventors: Yongchang Sang, Shunli Chen, Minghai Zhao