Abstract: A method of processing a stacked wafer including a first wafer and a second wafer stacked on a face side of the first wafer, includes positioning a focused spot of a laser beam inside the second wafer inwardly of two sides defining projected dicing lines, and applying the laser beam to the second wafer from an upper surface of the second wafer, thereby forming at least two strips of modified layers inside the second wafer along the projected dicing lines. A tape is affixed to the upper surface of the second wafer, and a projected dicing line is exposed by peeling off the tape from the upper surface of the second wafer to remove residuals of the second wafer that correspond to the projected dicing lines, thereby exposing the projected dicing lines on the face side of the first wafer.

Abstract: A method for preparing a germanium substrate for epitaxial growth of a germanium layer, having the steps of: A.) providing a germanium substrate having a processing side and a rear side opposite the processing side and electrochemical etching at least the processing side with at least the following etching steps: A.0) passivation of the processing side, which is polarized as a cathode, A.1) etching the processing side, the processing side being alternately polarized in an anode pulse as an anode and in a cathode pulse as a cathode, A.2) passivation of the processing side, the processing side being polarized as a cathode; A.3) etching the processing side, the processing side being alternately polarized in an anode pulse as an anode and in a cathode pulse as a cathode; B.) reorganizing the processing side, the germanium substrate being heated to greater than 500° C. A germanium substrate structure is also provided.

Abstract: A method for fabricating light emitting diode (LED) dice includes the steps of: providing a substrate [30], and forming a plurality of die sized semiconductor structures [32] on the substrate [30]. The method also includes the steps of providing a receiving plate [42] having an elastomeric polymer layer [44], placing the substrate [30] and the receiving plate [42] in close proximity with a gap [101] therebetween, and performing a laser lift-off (LLO) process by directing a uniform laser beam through the substrate [30] to the semiconductor layer [50] at an interface with the substrate [30] to lift off the semiconductor structures [32] through the gap [101] onto the elastomeric polymer layer [44]. During the laser lift-off (LLO) process the elastomeric polymer layer [44] functions as a shock absorber to reduce momentum transfer, and as an adhesive surface to hold the semiconductor structures [32] in place on the receiving plate [42].

Abstract: Exemplary semiconductor structures may include a silicon-containing substrate. The structures may include a layer of a metal nitride overlying the silicon-containing substrate. The layer of the metal nitride may include a plurality of features. The structures may include a gallium nitride structure overlying the layer of the metal nitride.

Abstract: Semiconductor devices and methods are provided. In an embodiment, a semiconductor device includes first nanostructures directly over a first portion of a substrate and second nanostructures directly over a second portion of the substrate, n-type source/drain features coupled to the first nanostructures and p-type source/drain features coupled to the second nanostructures, and an isolation structure disposed between the first portion of the substrate and the second portion of the substrate. The isolation structure includes a first smiling region in direct contact with the first portion of the substrate and having a first height. The isolation structure also includes a second smiling region in direct contact with the second portion of the substrate and having a second height, the first height is greater than the second height.

Abstract: Disclosed herein are example layouts and layout generation techniques for fault-tolerant quantum computers. Example embodiments comprise methods for performing a layout reduction technique for fault-tolerant quantum computing. In certain embodiments, a layout of an arbitrary quantum circuit is reduced to a layout of exponents of a multiple qubit Pauli matrix and measurements of a multiple qubit Pauli matrix. In certain embodiments, qubits are marked as one of a data, interface, or ancilla qubit for a 2D nearest neighbor graph of qubit connectivity, and an ancilla-path is provided from a respective data qubit to a respective interface qubit.

Abstract: An integrated circuit package includes a base substrate with at least one electronic chip mounted on a face of the base substrate. The electronic chip is configured to have hot spots in operation emitting heat in a heat volume space. A coating encapsulates the at least one electronic chip. The coating has a bottom face mounted on the face of the base substrate and a profiled top face. A portion of the profile top face is configured to locally reduce a volume of a region of the coating. The portion is located at least in part in the heat volume space. A heat sink is mounted on the profiled top face of the coating using a mounting layer.

Abstract: Depositing a seed layer after formation of the MD in order to reduce or prevent epitaxial growth of the seed layer toward the MD. For example, the seed layer may be deposited using CVD and conformal dry etching. In some implementations, the seed layer may be formed of ruthenium (Ru), molybdenum (Mo), or tungsten (W). Accordingly, the seed layer helps reduce or prevent seam formation in the VG, which reduces resistance of the VG by allowing for bottom-up metal growth. Additionally, current leakage from the VG to the MD is reduced or even prevented. As a result, device performance and efficiency are increased and breakdown voltage of the gate structure is also increased. Additionally, because electrical shorts are less likely, yield is increased, which conserves power, raw materials, and processing resources that otherwise would have been consumed during manufacture.

Abstract: A package structure and a method for fabricating the same are provided. The package structure includes a substrate, a semiconductor package and an adhesive body. The substrate has a first board surface and a second board surface. The semiconductor package has an upper surface and a lower surface, is disposed on the first board surface and electrically connected to the substrate through pins, and has a first vertical projection on the first board surface. An adhesive groove is disposed on the first board surface and is located in at least one portion of the first vertical projection and a periphery of the first vertical projection. The adhesive body is disposed in the adhesive groove, and protrudes to contact the lower surface, so as to fix the semiconductor package. The adhesive groove does not overlap with the pins, and the adhesive body does not contact the pins.

Abstract: A method includes: oxidizing a target N+-type gallium oxide substrate to obtain a first N?-type gallium oxide drift layer formed on an upper surface of the target N+-type gallium oxide substrate and a second N?-type gallium oxide drift layer formed on a lower surface of the target N+-type gallium oxide substrate; preparing a first anode electrode on an upper surface of the first N?-type gallium oxide drift layer and a second anode electrode on a lower surface of the second N?-type gallium oxide drift layer; cutting the target N+-type gallium oxide substrate, to obtain a first N+-type gallium oxide substrate and a second N+-type gallium oxide substrate; and preparing a first cathode electrode on a lower surface of the first N+-type gallium oxide substrate and a second cathode electrode on an upper surface of the second N+-type gallium oxide substrate, to obtain two Schottky diodes.

Abstract: This application is directed to a light-emitting diode epitaxial wafer, a growth method therefor, and a light-emitting diode chip. The growth method comprises: placing a sapphire substrate into a reaction chamber; introducing a reaction gas into the reaction chamber; forming GaN crystal nuclei containing In atoms on the sapphire substrate; growing at least one composite layer on the GaN crystal nuclei, the GaN crystal nuclei growing to form a buffer layer, each composite layer comprising an InGaN sublayer and a GaN sublayer; and successively growing an N-type GaN layer, an active layer and a P-type GaN layer on the buffer layer to form an epitaxial wafer, the active layer comprising alternately stacked InGaN quantum wells and GaN quantum barriers. Large and stable GaN crystal nuclei are formed to effectively counteract stress generated by lattice mismatch between the sapphire substrate and a GaN-based material.

Abstract: A method for manufacturing a light-emitting element includes: preparing a semiconductor structure body that includes: an n-side layer, a p-side layer, and an active layer positioned between the n-side layer and the p-side layer, where the n-side layer includes a plurality of first regions arranged in a first direction in a top view, the first regions exposed from the active layer and the p-side layer; forming a first insulating film on the p-side layer, between the first regions; forming a second insulating film to continuously cover the first regions, the p-side layer, and the first insulating film; forming an n-side opening in the second insulating film by removing the second insulating film on the first regions and on the first insulating film; and forming an n-side electrode in the n-side opening, the n-side electrode contacting the first regions and the first insulating film.

Abstract: A method of metal gapfill including depositing a metal layer on a dielectric layer present on a field and/or in an opening of a feature via plasma enhanced atomic layer deposition utilizing a metal halide precursor and a plasma comprising hydrogen and a noble gas; and depositing a metal gapfill material on the field and in the opening directly over the metal layer, wherein the metal gapfill material completely fills the opening.

Abstract: A method comprises the steps of providing a semiconductor wafer comprising a substrate layer; forming a first alignment mark and a second alignment mark; forming a plurality of super junction buffer regions; forming additional two or more epitaxial layers; forming additional one or more alignment marks; forming a top layer; thinning the wafer; forming a first plurality of regions and a second plurality of regions; and applying a singulation process. Devices made by the method have reduced misalignment, between a top portion and a bottom portion of an interface within the devices, for less than 0.5 micron.

Abstract: The present application provides a display panel and a display device. The display panel comprises a substrate, a dam, a first metal partition structure, a common layer and a cathode. The side surface of the first metal partition structure close to a hole area is provided with a recessed first undercut structure, so as not only to prevent water vapor from laterally invading a display area via the common layer, but also to avoid electrochemical corrosion due to a conductive path formed by the charged cathode overlapping the first metal partition structure.

Abstract: A method of manufacturing a semiconductor light-emitting element includes: forming an active layer of an AlGaN-based semiconductor material on an n-type semiconductor layer of an n-type AlGaN-based semiconductor material; forming a p-type semiconductor layer on the active layer; removing a portion of the p-type semiconductor layer and the active layer by dry etching to expose an upper surface of the n-type semiconductor layer; treating the upper surface of the n-type semiconductor layer with a plasma in an atmosphere including an N2 gas and an NH3 gas; and forming a n-side contact electrode on the upper surface of the n-type semiconductor layer treated with the plasma.

Abstract: A semiconductor wafer has a first pad electrode and a plurality of second pad electrodes formed on an upper surface thereof. A first opening and a plurality of second openings are formed in an insulating film covering the first pad electrode and the plurality of second pad electrodes. The first pad electrode is electrically connected to a first redistribution wiring in the first opening, and the plurality of second pad electrodes are electrically connected to a second redistribution wiring in the plurality of second openings. The first redistribution wiring has a narrow region and a wide region, a first columnar electrode is formed on the wide region, and a second columnar electrode is formed on the first columnar electrode. A third redistribution wiring is formed on the second redistribution wiring, and a plurality of third columnar electrodes are formed on the third redistribution wiring.

Abstract: A light-emitting element includes: a light emitting layer formed of an i-type layered nitride semiconductor; a first semiconductor layer that is disposed on one surface of the light emitting layer, and is formed of a p-type layered nitride semiconductor or p-type diamond; and a second semiconductor layer that is disposed on the other surface of the light emitting layer, and is formed of an n-type layered nitride semiconductor.

Abstract: A method and apparatus for tungsten gap-fill in semiconductor devices are provided. The method includes performing a gradient oxidation process to oxidize exposed portions of a liner layer, wherein the gradient oxidation process preferentially oxidizes an overhang portion of the liner layer, which obstructs or blocks top openings of one or more features formed within a field region of a substrate. The method further includes performing an etchback process to remove or reduce the oxidized overhang portion of the liner layer, exposing the liner layer to a chemical vapor transport (CVT) process to remove metal oxide remaining from the gradient oxidation process and the etchback process, and performing a tungsten gap-fill process to fill or partially fill the one or more features.

Abstract: An improved silicon carbide (SiC) super junction (SJ) MOSFET having at least two buried P-shield (BPS) regions facing each other for gate oxide electric-field and saturation current reductions is disclosed. The two BPS regions are spaced apart from a body region and formed either adjoining sidewalls or below a bottom of a P column region. Moreover, a saturation current pitching (SCP) structure formed in a Junction Field Effect Transistor (JFET) region sandwiched between the two BPS regions limits saturation current of the device in a forward conduction stage for the short-circuit capability improvement.