Patents Examined by Brandon Bowers
  • Patent number: 10430544
    Abstract: A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kn+1 graph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: October 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nien-Yu Tsai, Chin-Chang Hsu, Wen-Ju Preet Yang, Hsien-Hsin Sean Lee
  • Patent number: 10402528
    Abstract: A method of generating electronic circuit layout data can include electronically providing data representing a first standard cell layout including a first scaling enhanced circuit layout in an electronic storage medium. The first scaling enhanced circuit layout included in the first standard cell layout can be electronically defined using a marker layer. The first scaling enhanced circuit layout can be electronically swapped for a second scaling enhanced circuit layout to electronically generate data representing a second standard cell layout in the electronic storage medium. The data representing the second standard cell layout can be electronically verified.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chul-Hong Park, Su-Hyeon Kim, Sharma Deepak
  • Patent number: 10394981
    Abstract: A programmable integrated circuit includes rows of circuit blocks and up and down driving vertical interconnect resources. Each of the up and down driving vertical interconnect resources comprises a programmable signal path coupled to at least two of the rows of circuit blocks. A defect in any one of the up driving vertical interconnect resources in the programmable integrated circuit causes circuit blocks in a different set of the rows to store incorrect values compared to defects in the up driving vertical interconnect resources that originate in different ones of the rows of circuit blocks. A defect in any one of the down driving vertical interconnect resources in the programmable integrated circuit causes circuit blocks in a different set of the rows to store incorrect values compared to defects in the down driving vertical interconnect resources that originate in different ones of the rows of circuit blocks.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: August 27, 2019
    Assignee: Altera Corporation
    Inventors: Kalyana Kantipudi, Neil Da Cunha
  • Patent number: 10387605
    Abstract: A system and method for managing and composing verification engines and simultaneously applying such compositions to verify properties with design constraints allocates computing resources to verification engines based upon properties to be checked and optionally a user-specified budget. The verification engines are run in order to verify a received register transfer level (RTL) design description of a circuit according to user-specified assertions and constraints received by the system. The particular verification engines to be run are selected from a database of such engines and a run order is designated in sequential, parallel and distributed flows.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: August 20, 2019
    Assignee: Synopsys, Inc.
    Inventors: Maher Mneimneh, Scott Cotton, Mohamed Shaker Sarwary, Fahim Rahim, Sudeep Mondal, Paras Mal Jain
  • Patent number: 10372863
    Abstract: A system for dynamic circuit board design, preferably including a library of modular circuits and a merge tool. A method for merging modular circuitry into a unified electronics module, preferably including: receiving a circuit board layout, the circuit board layout preferably including a set of modular circuits arranged on a virtual carrier board; converting the circuit board layout into a virtual circuit representation; applying transformations to the virtual circuit representation; and generating a unified circuit board design based on the transformed virtual circuit representation.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: August 6, 2019
    Assignee: Arch Systems Inc.
    Inventors: Timothy Matthew Burke, Christopher Ling
  • Patent number: 10372857
    Abstract: One example includes a machine-readable storage medium encoded with instructions. The instructions are executable by a processor of a system to cause the system to receive at least one target electrical characteristic indicating a target impedance of a passive printed circuit board (PCB) structure. The passive PCB structure is a component of a serial communication channel. The instructions are executable by the processor to cause the system to divide the passive PCB structure into a plurality of elements. Each element has an input and an output. The instructions are executable by the processor to cause the system to determine at least one parameter of each element such that an image impedance of the input and the output of each element equals the target impedance.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: August 6, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Benjamin Toby, Karl J. Bois
  • Patent number: 10366200
    Abstract: A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes generating a first layout of the integrated circuit based on design criteria, generating a standard cell layout of the integrated circuit, generating a via color layout of the integrated circuit based on the first layout and the standard cell layout and performing a color check on the via color layout based on design rules. The first layout having a first set of vias arranged in first rows and first columns. The standard cell layout having standard cells and a second set of vias arranged in the standard cells. The via color layout having a third set of vias. The third set of vias including a portion of the second set of vias and corresponding locations, and color of corresponding sub-set of vias.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng Lin, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shih-Wei Peng, Wei-Chen Chien
  • Patent number: 10340712
    Abstract: One embodiment of the invention is an apparatus for determining the initiation of a charging process for a secure charging apparatus. The apparatus has circuitry for authorising a user, circuitry for confirming connection of a device, and circuitry for confirming charging of the device.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: July 2, 2019
    Assignee: CHARGEBOX LTD
    Inventors: Ian Timothy Hobson, Jonathan John Cheese, Jonathan Anthony Hogg
  • Patent number: 10325849
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip has a plurality of gate structures arranged over a substrate. A plurality of first MOL (middle-of-line) structures are arranged at a first pitch over the substrate at locations interleaved between the plurality of gate structures. The plurality of first MOL structures connect active regions within the substrate to an overlying metal interconnect layer. A plurality of second MOL structures are arranged at a second pitch over the plurality of gate structures at locations interleaved between the plurality of first MOL structures. The plurality of second MOL structures connect the plurality of gate structures to the metal interconnect layer. The second pitch is different than the first pitch. The different pitches avoid misalignment errors between the plurality of gate structures and the metal interconnect layer.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Liang-Yao Lee, Tsung-Chieh Tsai, Juing-Yi Wu, Chun-Yi Lee
  • Patent number: 10325054
    Abstract: Methods and apparatuses are described for sharing inductive invariants while performing formal verification of a circuit design. Specifically, some embodiments assume at least an inductive invariant for a property to be true while proving another property. According to one definition, an inductive invariant of a property is an inductive assertion such that all states that satisfy the inductive assertion also satisfy the property. According to one definition, an inductive assertion describes a set of states that includes all legal initial states of the circuit design and that is closed under a transition relation that models the circuit design.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: June 18, 2019
    Assignee: Synopsys, Inc.
    Inventors: Himanshu Jain, Per M. Bjesse, Carl P. Pixley
  • Patent number: 10325055
    Abstract: This application discloses a computing system configured to determine a timing window for reception of a signal propagated through a victim channel in a circuit design, generate an aggressor window bump for each noise bump capable of being induced on the victim channel by one or more aggressor channels, determine a delta delay corresponding to the timing window for the signal propagated through the victim channel based, at least in part, on one or more of the aggressor window bump, and utilize the delta delay corresponding to the timing window for the signal to determine whether the victim channel operates within a timing constraint associated with the circuit design.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: June 18, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Dhananjay Kumar Griyage, Mohan Rangan Govindaraj
  • Patent number: 10318684
    Abstract: Systems and techniques for clock tree optimization are described. An electronic design automation (EDA) tool can receive a graph that represents a circuit design, wherein a set of trees in the graph can correspond to a set of clock trees in the circuit design. For each tree in the set of trees, a set of leaf node pairs can be determined. Next, for each leaf node pair, a flow can be created in the graph between the two leaf nodes in the leaf node pair. Aggregate flows can be determined for edges in the graph based on the flows. A set of edges based on the aggregate flows can be identified, and then circuitry corresponding to the set of edges can be identified. Next, the identified circuitry in the circuit design can be optimized.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: June 11, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Zuo Dai, Aiqun Cao
  • Patent number: 10310386
    Abstract: Methods of reducing a pattern displacement error, contrast loss, best focus shift, and/or tilt of a Bossung curve of a portion of a design layout used in a lithographic process for imaging that portion onto a substrate using a lithographic apparatus. The methods include adjusting an illumination source of the lithographic apparatus, placing one or more assist features onto, or adjusting a position and/or shape of one or more existing assist features in, the portion. Adjusting the illumination source and/or the one or more assist features may be by an optimization algorithm.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: June 4, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Duan-Fu Stephen Hsu, Feng-Liang Liu
  • Patent number: 10296695
    Abstract: Methods and systems for implementing track pattern for electronic designs are disclosed. The method identifies a first track in a design and viable implementing options for the first track. When adding a second track to the track pattern, the method determines whether the second track corresponds to the viable implementing options for the track. The second track is inserted to the track pattern and situated immediately adjacent to the first track if the second track is determined to correspond to a viable implementing option for the first track. One or more intermediate tracks may be inserted immediately adjacent to the first track before inserting the second track to produce a legal track pattern. Tracks may be removed from a track pattern. One or more intermediate tracks may be inserted into the space occupied by a track being removed to ensure track pattern's compliance with design rules after the track removal.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: May 21, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yinnie Lee, Jeffrey Markham, Roland Ruehl, Karun Sharma
  • Patent number: 10296692
    Abstract: A method of metrology target design is described. The method includes providing a range or a plurality of values for design parameter of a metrology target and by a processor, selecting, by solving for and/or sampling within the range or the plurality of values for the design parameters, a plurality of metrology target designs having one or more design parameters meeting a constraint for a design parameter of the metrology target.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: May 21, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Guangqing Chen, Justin Ghan, David Harold Whysong
  • Patent number: 10275553
    Abstract: A method for simulating a power consumption associated with a circuit. Once a netlist describing the circuit and an input stimulus for the netlist are obtained, the netlist is partitioned into multiple circuit blocks. Circuit logic models (CLMs) implemented in a hardware description language (HDL) are then obtained for the multiple circuit blocks and a logic netlist is generated from the multiple CLMs. A power vector for a CLM corresponding to a circuit block is calculated using a logic simulator inputting the logic netlist and the input stimulus. Further, a power consumption value is calculated for the circuit block using a circuit simulator and the power vector. The power consumption associated with the circuit is calculated based on the power consumption values for various circuit blocks.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: April 30, 2019
    Assignee: Oracle International Corporation
    Inventors: Krishnan Sundaresan, Aravind Oommen, Mohd Jamil Mohd, Hemanga Lal Das, Pranjal Srivastava
  • Patent number: 10268791
    Abstract: A method is disclosed that includes the operation below. Vertices in a conflict graph are sorted into a first clique and a second clique, in which the conflict graph corresponds to a layout of a circuit. A first vertex of the vertices is merged with a second vertex of the vertices, to generate a reduced graph, in which the first clique excludes the second vertex, and the second clique excludes the first vertex. A first color pattern of a plurality of color patterns is assigned to a first pattern, corresponding to the first vertex, and a second pattern, corresponding to the second vertex, in the layout according to the reduced graph.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Hung Lin, Chung-Hsing Wang, Chin-Chou Liu, Chi-Wei Hu
  • Patent number: 10262096
    Abstract: Systems and methods are disclosed herein to provide improved placement of components in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD. The method also includes determining a layout comprising positions of components of the PLD configured to perform the operations. The method also includes performing a timing analysis on the layout. The method also includes selectively adjusting the positions of the components using the timing analysis. Related systems and non-transitory machine-readable mediums are also provided.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: April 16, 2019
    Assignee: Lattice Semiconductor Corporation
    Inventors: Yinan Shen, Jun Zhao
  • Patent number: 10255403
    Abstract: A view definition analyzer maps a plurality of timing views for a circuit design into compatibility groups having shared operating conditions of their respective process corners. An ETM generator then extracts an extracted timing model from a block of the circuit design for each compatibility group, containing timing arcs representing each combination of interface path in the circuit block and timing view in the compatibility group, where at least one timing arc in the ETM is a merged version of multiple timing arcs for an interface path across multiple timing views in the compatibility group. Timing arcs are merged when each timing characteristic in a first timing arc matches, within a tolerance threshold, a corresponding timing characteristic in a second timing arc. The ETM may then be used to model any timing view in the compatibility group. The ETM generator thus produces a minimal set of extracted timing models.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: April 9, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sneh Saurabh, Naresh Kumar
  • Patent number: 10242149
    Abstract: A method, system, and computer program product for enhancing integrated circuit noise performance. The method is for arranging target wires in a target region, the method including: for each wire in the target wires, obtaining a signal jump interval with respect to each of the other wires in the target wires, wherein the signal jump interval of one wire with respect to a further wire is a time interval between occurrence of signal jump on the one wire and occurrence of signal jump on the further wire; calculating a corresponding time influence factor based on the signal jump interval, wherein the time influence factor is a decreasing function of the signal jump interval; and arranging the target wires in the target region based on the time influence factor. Coupling noise between wires may be reduced according to the technical solution of an embodiment of the present invention.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Xia Li, Suo Ming Pu, Xiao Feng Tang, Bo Yu