Abstract: An on-chip voltage delivery method for a system includes multiple processor cores operating at multiple voltage levels. Distributed on-chip DC-DC converters as voltage regulators may deliver point of load current to the different units of a processor core operating at the same voltage level. Distributed timing sensors calibrated to generate digitized clock edge location. A power management unit may take input from the timing sensors, processes it through a particle swarm optimizer and generates digitized voltage identification code as reference to the distributed voltage regulators. The particle swarm optimizer may provide disparate voltage levels feasible for a given frequency of operation of the processor core with a provision to operate at multiple frequencies. The run-time assignment of the voltage through the particle swarm optimizer may negate the effects of transistor aging, process, temperature, and power supply noise induced variation in the load circuits, voltage regulators and sensors.

Abstract: A method of warpage-aware floorplanning for heterogeneous integration structure is proposed, which is executed by a computer, the method comprising using the computer to perform the following: performing a performing a layout partitioning to divide a layout into a plurality of grids; performing an initial floorplanning by assigning first geometric relations between a plurality of dies such that an effective material of each grid of the plurality of grids is determined; performing a global floorplanning to change the first geometric relations between the plurality of dies to second geometric relations to optimize warpage effect of the heterogeneous integration structure; and performing a detailed floorplanning to determine die order of placement based on material differences between the plurality of dies and an interposer.

Abstract: A simulation of an electronic device may use a distribution of atomistic defects to provide more accurate results. An input mesh may be received representing a physical structure of the electronic device. This input mesh may be transformed into a polyhedral mesh to facilitate the simulation. A distribution of defects may then be generated and distributed throughout the polyhedral mesh. When performing each time step of the simulation, the effects of these defects may be attributed to individual cells in the polyhedral mesh and incorporated into the simulation equations for each volume. For example, charge and power contributions from the defects may be incorporated into the simulation equations to more accurately model the performance of the device.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first contact and a second contact disposed over a substrate. A center of a first upper surface of the first contact is laterally separated from a center of a second upper surface of the second contact by a first distance. A first interconnect contacts the first upper surface and a second interconnect contacts the second upper surface. A center of a first lower surface of the first interconnect is laterally separated from a center of a second lower surface of the second interconnect by a second distance that is greater than the first distance.

Abstract: The disclosure provides a system to simulate a simulated noise on the power zone block of a substrate. The system comprises a signal trace and a signal generating circuit. The signal trace is disposed adjacent to the power zone block. The signal generating circuit is electrically coupled to the signal trace, configured to transmit an alternating current signal over the signal trace. The alternating current signal transmitted over the signal trace is configured to induce a simulated noise on the power zone block, and a waveform of the simulated noise is determined by a frequency of the alternating current signal.

Abstract: Aspects of the present disclosure address systems and methods for zigzag detection and handling for integrated circuit designs. Data describing an integrated circuit is accessed. The integrated circuit design comprises a connection path between two or more pins of a net determined based on an initial routing of the net. A zigzag is detected in the connection path based on a local turn density constraint that specifies a ratio of a number of turns to a pathlength that corresponds to zigzagging in the net. In response to detecting the zigzag in the connection path, the zigzag is removed from the connection path by rerouting the net using a routing constraint that defines a maximum number of turns in the connection path.

Abstract: Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.

Abstract: Electric vehicle charging management methods and systems with flexible adjustment of charging schedule are provided. A server executes an energy management scheme to determine a target power parameter value for a charging operation of each electric vehicle charging station, and perform the charging operations accordingly for respective electric vehicles. A specific charging demand of a specific electric vehicle charging station or a specific electric vehicle is received, wherein the specific charging demand includes at least a demand time. In response to the specific charging demand, the target power parameter value corresponding to the charging operation of the specific electric vehicle charging station is adjusted, wherein the power of the specific electric vehicle at the time of demand will be higher than a predetermined power value.

Abstract: Methods and systems for generation of shape data for a set of electronic designs include inputting a set of shape data, where the set of shape data represents a set of shapes for a device fabrication process. A convolutional neural network is used on the set of shape data to determine a set of generated shape data, where the convolutional neural network comprises a generator trained with a set of pre-determined discriminators. The set of generated shape data comprises a scanning electron microscope (SEM) image.

Abstract: Systems, methods, and instructions of computer-readable media may include obtaining, at a client machine, a user-selected configuration parameter for an orbit simulation; sending, from the client machine to a remote system, via a network connection, a first set of configuration parameters for the orbit simulation, wherein the first set of configuration parameters comprise the user-selected configuration parameter; receiving, at the client device from the remove device, via the network connection, a stream of orbital data comprising points along an orbit, wherein the points along the orbit are determined by the remote system based on the first set of configuration parameters; and presenting, at a display, a dynamic rendering of the orbit simulation, wherein the orbit simulation is based on the stream of orbital data.

Abstract: A method for dynamically generating or interacting with an electromagnetic field includes providing a spatial array of conductive segments, a switching device operable on each of the conductive segments to either allow or block transmission of an electrical signal and a control device operable on the switching device. A sequence of the conductive segments are connected to form a conductive path where each segments intersects with at least two different ones of the conductive segments at a node. The switching device operates to connect a selected first one of the conductive segments with a selected second one of the conductive segments to form the sequence according to a logic signal from the control device. Power is supplied to the conductive path to produce an electromagnetic field which depends at least in part on the spatial arrangement of the connected sequence of the conductive segments.

Abstract: A monitoring device includes a receiving unit receiving effective power output value and reactive power output value from inverter devices, a setting unit setting effective power target value and reactive power output value for each inverter device, a first calculation unit calculating voltage phase command value for each inverter device, a second calculation unit calculating a voltage amplitude command value for each inverter device, a transmitting unit transmitting the voltage phase command value and voltage amplitude command value to relevant inverter devices, a distribution rate calculating unit calculating a distribution rate for each inverter device, and a total value calculating unit calculating effective power total value and reactive power total value for the inverter devices.

Abstract: A method includes: extracting a first current profile model corresponding to a System on Chip (SOC) at a first design stage of the SOC; determining that a first design data of an Integrated Voltage Regulator (IVR) and the SOC pass a first co-simulation based on the extracted first current profile model; extracting a second current profile model corresponding to the SOC at a second design stage of the SOC, the second design stage being subsequent to the first design stage; refining the first design data of the IVR to generate a second design data of the IVR; determining that the second design data of the IVR and the SOC pass a second co-simulation based on the extracted second current profile model.

Abstract: A method for cell swapping is provided. A location for swapping a first cell is determined. One or more legal positions for cell placement are determined at the location. A plurality of cells is determined for of the plurality of legal positions. A second cell from the plurality of cells is determined based on timing information associated with each of the plurality. The first cell is swapped with the second cell.

Abstract: A pattern layout design method includes performing optical proximity correction (OPC) for a mask layout, thereby creating a corrected layout. Creation of the corrected layout includes creating a first corrected layout through grid snapping for an oblique edge of a mask layout designed on a grid layout, and performing optical proximity correction (OPC) for the first corrected layout, thereby creating a second corrected layout. Creation of the first corrected layout includes creating a first divisional point for the oblique edge or a residual edge, and shifting the first divisional point to one of four reference points adjacent to the first divisional point, thereby creating a first varied divisional point.

Abstract: Embodiments of the present disclosure relate to a system, a software application, and a method of a lithography process to update one or more of a mask pattern, maskless lithography device parameters, lithography process parameters utilizing a file readable by each of the components of a lithography environment. The file readable by each of the components of a lithography environment stores and shares textual data and facilitates communication between of the components of a lithography environment such that the mask pattern corresponds to a pattern to be written is updated, the maskless lithography device of the lithography environment is calibrated, and process parameters of the lithography process are corrected for accurate writing of the mask pattern on successive substrates.

Abstract: According to an embodiment, a cart gate for storage of carts that have a power reception device includes a pair of guides spaced from each other in a cart-width direction. The guides extend along a forward cart direction. A power transmission device is mounted on a portion of one of the guides. The power transmission device is configured to provide power, in a non-contact manner, to a power reception device on a cart that is between the pair of guides and at a predetermined cart storage position along the forward cart direction. The minimum distance between the guides in the cart-width direction is greater than a width of the cart, but the difference between the minimum distance and the width of the cart is less than or equal to a power transmitting range of the power transmission device.

Abstract: A system generates a mask for a circuit design while enforcing symmetry and consistency across random areas of the mask. The system builds a mask solutions database mapping circuit patterns to mask patterns. The system uses the mask solutions database to replace circuit patterns of the circuit design with mask patterns. The system identifies properties in circuit patterns of the circuit design and enforces the same property in the corresponding mask patterns. Examples of properties enforced include symmetry within circuit patterns and similarity across circuit patterns. The system combines mask patterns in different regions of the circuit and resolves conflicts that occur when there are multiple masks within a region.

Abstract: An estimation device includes: an acquisition unit that acquires a voltage, a current, and a temperature of a lead-acid battery; a first deriving unit that derives a first SOC and a second SOC that are SOCs of a start point and an end point of an estimation period; a second deriving unit that derives a total amount of an overcharge amount in the estimation period; a third deriving unit that derives an actual measurement error based on a difference between the first SOC and the second SOC and the total amount of the overcharge amount; a first specification unit that specifies an estimation error based on the first SOC, the second SOC, and the temperature, and a relationship between the first SOC, the second SOC, and the temperature of the lead-acid battery, and the estimation error; a second specification unit that specifies an abnormality degree of the actual measurement error based on the derived actual measurement error and the specified estimation error; and an estimation unit that estimates generation of

Abstract: A method for determining process window limiting patterns based on aberration sensitivity associated with a patterning apparatus. The method includes obtaining (i) a first set of kernels and a second set of kernels associated with an aberration wavefront of the patterning apparatus and (ii) a design layout to be printed on a substrate via the patterning apparatus; and determining, via a process simulation using the design layout, the first set of kernels, and the second set of kernels, an aberration sensitivity map associated with the aberration wavefront, the aberration sensitivity map indicating how sensitive one or more portions of the design layout are to an individual aberrations and an interaction between different aberrations; determining, based on the aberration sensitivity map, the process window limiting pattern associated with the design layout having relatively high sensitivity compared to other portions of the design layout.