Abstract: Systems and methods for integrated circuit (IC) analysis using a multi-level data hierarchy implemented on a distributed compute and data infrastructure are described. An IC design may be represented using a set of storage areas, where each storage area may be stored in a contiguous block of storage and may correspond to a portion of the IC design. An analysis application may be executed on the IC design, where a subset of the set of storage areas that is used by the analysis application may be retrieved on-demand.

Abstract: A system and method for the automatic placement of superconducting devices determines an arrangement of a series of Josephson junctions between a start point and an end point of an inductive wiring run on a superconducting circuit layout having a plurality of discrete Josephson junction placement sites by determining costs of placing each Josephson junction of the series of Josephson junctions at the plurality of discrete Josephson junction placement sites between the start point and the end point of the inductive wiring run based at least on a comparison of a target inductance value to inductances of wires connecting to the Josephson junction and selecting sites from the plurality of discrete Josephson junction placement sites to place each Josephson junction corresponding to the arrangement of the series of Josephson junctions with the least determined cost for the inductive wiring run.

Abstract: Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA).

Abstract: Systems and methods for performing depth-dependent oxidation modeling and depth-dependent etch modeling in a virtual fabrication environment are discussed. More particularly, a virtual fabrication environment models, as part of a process sequence, oxidant dispersion in a depth-dependent manner and simulates the subsequent oxidation reaction based on the determined oxidant thickness along an air/silicon interface. Further the virtual fabrication environment performs depth-dependent etch modeling as part of a process sequence to determine etchant concentration and simulate the etching of material along an air/material interface.

Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

Abstract: Embodiments disclosed herein describe switching logic in board-level interconnects and in the system-level interconnects that may provide bitwise dynamic routing and switching between corresponding board-level and system-level components. At board-level, a switching ASIC may receive input data through a backplane from an emulation ASIC in a first logic board and route any bit of the input data to any of the emulation ASIC in a second logic board. At system-level, a switching logic board containing a set of switching ASICs may be associated with a logic cluster and may dynamically route data bits from the emulation ASICs in the logic cluster to emulation ASICs to other logic clusters of the emulation system and/or target systems. Additionally, the switching logic board may dynamically route bits from the other logic clusters to the associated logic cluster.

Abstract: The present disclosure relates to systems and methods for floorplanning using machine learning techniques. Embodiments may include receiving an electronic design and analyzing the electronic design using a reinforcement learning agent. Embodiments may further include recommending a first action wherein the first action includes at least one of a place agent action, a via agent action, or a route agent action. Embodiments may also include updating the electronic design based upon, at least in part, the first action to generate an updated electronic design. Embodiments may further include analyzing the updated electronic design using the reinforcement learning agent and recommending a second action wherein the second action includes at least one of a place agent action, a via agent action, or a route agent action. Embodiments may also include updating the updated electronic design based upon the second action to generate a second updated electronic design.

Abstract: Systems and methods are provided for a turnkey modular printed circuit board enclosure that is generated using a template generator. The template generator accepts a user input comprising an enclosure parameter, based on which a manufacturing file may be generated. The manufacturing file may be provided to a fabricator for fabricating the enclosure or the manufacturing file may be modified in a printed circuit board design environment to incorporate a printed circuit board into the enclosure. The printed circuit board may be a separate printed circuit board that is inserted into the enclosure or it may be embedded in a face of the enclosure.

Abstract: The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and performing a deadlock check on the electronic circuit design using a using a linear temporal logic property and a proof engine. Embodiments may further include analyzing a counterexample associated with the electronic circuit design for a loop escape condition, wherein analyzing includes proving a cover trace of a liveness obligation. If the loop escape condition is reachable from the counterexample, embodiments may include extracting one or more events associated with the loop escape condition and adding a waiver constraint to the deadlock check to force a no deadlock outcome.

Abstract: Systems and methods are provided for using an integrated circuit design tool to analyze timing requirements of a circuit design for an integrated circuit. A slack is calculated for a timing path in the circuit design that fails to satisfy a timing constraint. The slack is decomposed into multiple categories of delays in the timing path. The categories of delays for the slack may include intrinsic margin, clock skew, logic delay, and fabric interconnect delay. The logic delay may include local interconnect delay and logic circuit delay. The fabric interconnect delay may include delays in interconnect elements that are used to make connections between larger blocks of the logic circuits. Different optimization strategies are provided to solve the timing constraint failure for each of the different categories of slack breakdown. Slack profiles of the entire design in each of the four categories of slack are also provided.

Abstract: A system and method for generating simulation-friendly compact physical models for passive structures is disclosed. The method includes generating an impedance map specifying impedances at a plurality of frequencies corresponding to one or more port-pairs of a circuit component using a processor to extract a plurality of impedance values between the one or more port-pairs based on a first value for each parameter of a plurality of parameters of the circuit component. The method includes generating a second circuit representation model based on updating the plurality of impedance values between the one or more port-pairs based on a second value for one or more parameters of the plurality of parameters of the circuit component, and updating the second circuit representation model by tuning the updated plurality of impedance values of the between the one or more port-pairs based on a predetermined use context of the circuit component in a circuit.

Abstract: Methods and systems for performing fault injection testing on an integrated circuit hardware design.

Abstract: An injection device is disclosed herein. The injection device is utilized to inject a liquid onto a test area of a semiconductor element. The injection device includes a base, a reservoir, a first testing pipe, a cleaning pipe and a liquid-draining pipe. The reservoir set on the base is provided with at least one connecting port and a dropping port, wherein the dropping port is against the test area of the semiconductor element. The first testing pipe, the cleaning pipe and the liquid-draining pipe are connected to at least one connecting port, wherein a first liquid is injected from the first testing pipe into the reservoir, and wherein the a cleaning liquid is injected from the cleaning pipe into the reservoir to clean the reservoir and the test area. The dropping port is utilized to drain off the first testing liquid and the cleaning liquid in the reservoir. A semiconductor testing system utilizing the injection device and its testing method are also provided herein.

Abstract: The present disclosure provides an electronic device, a method for generating a package drawing, and a computer readable storage medium. The electronic device includes a display device and a processor, the processor is configured to obtain a type of the element and size parameters corresponding to the element input by a user; determine a size and a position of each of pads corresponding to the element according to the type of the element and the size parameters corresponding to the element, and draw the pads; determine coordinates of endpoints of an entity layer corresponding to the element, and draw the entity layer; determine coordinates of endpoints of a height layer corresponding to the element, and draw the height layer; and determine coordinates of endpoints of a screen layer corresponding to the element, and draw the screen layer.

Abstract: A system and methods are disclosed that generate a physical roadmap for the connectivity of a network, such as a network-on-chip (NoC). The roadmap includes a set of possible positions for placement of edges and nodes, which are known to be an acceptable and good position for placement of these network elements, that honors the constraints of the network. These known positions are made available to the system for synthesis of the network and generating the connectivity and placement based on the physical roadmap.

Abstract: A method for determining an electrical model of a string of photovoltaic modules from a characteristic I(V) of the string includes detecting a first linear zone and a second linear zone of the characteristic I(V); initialising the parameters of a non-by-pass electrical model corresponding to a first operating condition, called a non-by-pass condition; optimising the parameters of the non-by-pass electrical model from a reference characteristic I(Vref) equal to I(V), determining the parameters of the electrical model corresponding to a second operating condition, called a by-pass condition, in order to obtain a by-pass electrical model from the characteristic determining, from the characteristic I(V) the best model among the non-by-pass model and the by-pass model.

Abstract: A programmable device includes a functional module, a pre-allocation manager, a first connection line, and a second connection line, wherein the pre-allocation managers are connected by the first connection lines, and the pre-allocation managers are connected to the functional modules by the second connection lines; the first connection lines are used for data transmission between the pre-allocation mangers, and a transmission direction is determined according to the configuration; the second connection lines are used for data transmission between the pre-allocation managers and the functional modules; the pre-allocation mangers are used for data transmission between the first connection lines and for data transmission between the first connection lines and the functional modules. The first connection lines are configured as connection line segments for transmission in both directions, and a wiring structure is designed in a direction and shape meeting wiring requirements.

Abstract: Disclosed are a heating method for a rechargeable battery, a control unit and a heating circuit. The heating method comprises: determining a frequency value of a pulse current for heating the rechargeable battery in response to a heating command of the rechargeable battery; determining a current value of the pulse current according to the frequency value and an acquired state parameter of the rechargeable battery; judging whether the current value satisfies a preset heating demand; if the current value satisfies the heating demand, generating the pulse current under control according to the frequency value; if the current value does not satisfy the heating demand, re-determining the frequency value and the current value of the pulse current. The embodiments of the present disclosure further provide a control unit and a heating circuit.

Abstract: A method, a computer system, and a computer program product for scan chain wirelength optimization is provided. Embodiments of the present invention may include obtaining root nodes details from the root nodes. Embodiments of the present invention may include optimizing a connectivity of the root nodes. Embodiments of the present invention may include identifying a best start node and a best end node for each of the root nodes. Embodiments of the present invention may include optimizing child nodes in each of the root nodes. Embodiments of the present invention may include determining that a wirelength of a full tour is shorter or longer than a nearest neighbor. Embodiments of the present invention may include applying or skipping a solution.

Abstract: The present disclosure provides a photomask and a method of forming a photomask, in which the photomask may obtain an optimized uniformity via a simplified process flow. The photomask includes a plurality of stair-like patterns parallel disposed with each other, wherein each of the stair-like patterns includes a plurality of first right angles at one side and a plurality of second right angle at another side opposite to the side, and each of the first right angles and each of the second right angles are not in a same vertical axis.