Abstract: A MIM capacitor includes a bottom electrode, a middle electrode disposed over the bottom electrode, a top electrode disposed over the middle electrode, a first dielectric layer sandwiched between the bottom electrode and the middle electrode, and a second dielectric layer sandwiched between the middle electrode and the top electrode. A surface of the bottom electrode and a surface of the top electrode respectively comprise a Ra value lower than 0.35 nm and a Rq value lower than 0.4 nm.

Abstract: An image sensor comprises a semiconductor material having a front side and a back side opposite the front side; a dielectric layer disposed on the front side of the semiconductor material; a poly layer disposed on the dielectric layer; an interlayer dielectric material covering both the poly layer and the dielectric layer; an inter-metal layer disposed on the interlayer dielectric material, wherein a metal interconnect is disposed in the inter-metal layer; and a contact pad trench extending from the back side of the semiconductor material into the semiconductor material, wherein the contact pad trench comprises a contact pad disposed in the contact pad trench, wherein the contact pad and the metal interconnect are coupled with a plurality of contact plugs; and at least an air gap isolates the contact pad and side walls of the contact pad trench.

Abstract: A method of forming a vertical fin field effect transistor having a consistent channel width, including forming one or more vertical fin(s) on the substrate, wherein the one or more vertical fin(s) have a tapered profile, oxidizing the one or more vertical fin(s) to form an oxide by consuming at least a portion of the vertical fin material, and removing the oxide from the one or more vertical fin(s), wherein the one or more vertical fin(s) include a tapered upper portion, a tapered lower portion and a straight channel portion there between.

Abstract: Embodiments of the invention are directed to a method and resulting structures for forming optically readable chip identification (CID) codes using dummy controlled collapse chip connection (C4) bumps. In a non-limiting embodiment of the invention, a product chip is formed on a wafer. A chip location identifier including a plurality of controlled collapse chip connection (C4) bumps is formed on a surface of the product chip. The chip location identifier encodes a unique location of the product chip on the wafer prior to dicing. The plurality of C4 bumps are arranged into one or more optically readable alphanumeric characters.

Abstract: In accordance with various embodiments of the disclosed subject matter, a display panel, a fabricating method thereof, and a related display apparatus are provided. In some embodiments, the display panel comprises: a base substrate comprising a display region and a peripheral region, wherein the peripheral region surrounds the display region; a light emitting device in the display region; a buffer layer on the peripheral region; and a first sealing layer on the buffer layer and the light emitting device.

Abstract: A power semiconductor device includes a plurality of power chips sealed in a package to control power and an IC sealed in the package to control each of the power chips. The IC is disposed at the center part of the package in the plan view. The plurality of power chips are disposed so as to surround the IC in the plan view.

Abstract: A semiconductor device includes a high voltage NMOS transistor formation region defined by an element isolation insulating film, a CMOS transistor formation region defined by an element isolation insulating film, and a substrate contact portion. The substrate contact portion is formed in a region of a semiconductor substrate that is positioned between the high voltage NMOS transistor formation region and the element isolation insulating film so as to reach from the main surface side to a position deeper than the bottom of the element isolation insulating film. The substrate contact portion is in contact with the semiconductor substrate from a depth over a depth.

Abstract: FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.

Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes a peripheral circuit gate pattern on a first substrate, an impurity region in the first substrate and spaced apart from the peripheral circuit gate pattern, a cell array structure on the peripheral circuit gate pattern, a second substrate between the peripheral circuit gate pattern and the cell array structure, and a via that is in contact with the impurity region and disposed between the first substrate and the second substrate. The via electrically connects the first and second substrates to each other.

Abstract: A display device includes a display area and a non-display area. The non-display area includes a sealing area which includes a sealing material. The display area includes a thin film transistor structure, a pixel electrode on and connected to the thin film transistor structure, and a pixel defining layer overlapping an edge of the pixel electrode. A first functional layer is on substrate on which the pixel defining layer is formed and does not overlap the sealing area. A light emitting layer is on the first functional layer and overlaps the pixel electrode, and a common electrode on the light emitting layer.

Abstract: An integrated circuit chip includes an interconnection stack with a cavity formed therein. The cavity extends through one or more interconnection levels of the stack. A material at least partially fills the cavity. The fill material has a selectivity to polishing and/or to etching different by more than 10% from a selectivity to polishing and/or to etching of a material forming an insulator of the interconnection stack.

Abstract: A semiconductor package device includes a first die, an adhesive layer, and an encapsulant layer. The first die comprises a first electrode at a first surface of the first die and a second electrode at a second surface of the first die opposite to the first surface of the first die. The adhesive layer is disposed on the first surface of the first die. The encapsulant layer encapsulates the first die and the adhesive layer, wherein substantially an entire surface of the second electrode is exposed from the encapsulant layer.

Abstract: A vertical transistor device and a method for fabricating the same are provided. The vertical transistor device includes a semiconductor substrate, first sources/drains and second sources/drains. The semiconductor substrate includes a bottom portion and fin portions located on the bottom portion. Each of the fin portions includes an upper portion and a lower portion. The lower portion is located between the bottom portion of the semiconductor substrate and the upper portion, in which the lower portion includes recesses. The first sources/drains are disposed on terminals of the upper portions of the fin portions. The second sources/drains are disposed on the recesses of the lower portions of the fin portions, in which the sources/drains are not merged with each other. In the method for fabricating the vertical transistor device, the lower portions of the fin portions are patterned to form the recesses on the lower portions of the fin portions.

Abstract: A semiconductor package is described which meets a plurality of predetermined electrical, mechanical, chemical and/or environmental requirements. The semiconductor package includes a semiconductor die embedded in or covered by a molded plastic body, the molded plastic body satisfying only a subset of the plurality of predetermined electrical, mechanical, chemical and/or environmental requirements. The semiconductor package further includes a plurality of terminals protruding from the molded plastic body and electrically connected to the semiconductor die, and a coating applied to at least part of the molded plastic body and/or part of the plurality of terminals. The coating satisfies each predetermined electrical, mechanical, chemical and/or environmental requirement not satisfied by the molded plastic body.

Abstract: A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.

Abstract: A deformable closed-loop multi-layered microelectronic device is provided. A top layer, a bottom layer and a middle layer of the microelectronic device each have at least a first section and a second section pivotable with respect to each other. A pivot is provided to a terminal end of the first section of the middle layer, for allowing the first section to rotate about the pivot. The pivot is vertically sandwiched between and connected to a terminal end of the first section of the top layer and a terminal end of the first section of the bottom layer. The first sections of the bottom layer and the top layer are pivotable in a substantially synchronized manner to deform the bottom layer and the top layer in a substantially synchronized manner.

Abstract: What is disclosed is a pixel array architecture for displays being based on a matrix of subpixels arranged in a rectilinear matrix oriented at an angle relative to a horizontal direction of the display, exhibiting a reduced pixel pitch for the subpixels.

Abstract: In a method for manufacturing a semiconductor device, a first raised structure is formed on a surface of a substrate. The first raised structure includes a top surface and a side surface adjoining the top surface. The side surface includes an upper portion, a middle portion, and a lower portion. A deposition operation is performed with a precursor to form a first film on the top surface, the upper portion and the lower portion of the side surface, and the surface of the substrate. Performing the deposition operation includes controlling a saturated vapor pressure of the precursor. A re-deposition operation is performed on the first film and the first raised structure, so as to form a film structure. A thickness of the film structure on the middle portion of the side surface is smaller than a thickness of the film structure on the top surface.

Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.

Abstract: A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.