Abstract: A semiconductor memory device includes a stacked structure including conductive layers and insulating layers alternately stacked, a strained channel layer passing through the stacked structure, a stressor layer contacting the strained channel layer and applying stress to the strained channel layer, and a core layer formed in the stressor layer.

Abstract: A semiconductor device includes a substrate having an upper surface, a plurality of active fins on the substrate, a gate electrode crossing the plurality of active fins, and at each side of the gate electrode, a source/drain region on the plurality of active fins. The source/drain region may include a plurality of first regions extending from the active fins, and a second region between each of the plurality of first regions. The second region may have a second germanium concentration greater than the first germanium concentration. The source/drain region may be connected to a contact plug, and may have a top surface that has a wave shaped, or curved surface. The top surface may have a larger surface area than a top surface of the contact plug.

Abstract: A device includes: a gate line on an active region of a substrate, a pair of source/drain regions in the active region on both sides of the gate line, a contact plug on at least one source/drain region out of the pair of source/drain regions; and a multilayer-structured insulating spacer between the gate line and the contact plug. The multilayer-structured insulating spacer may include an oxide layer, a first carbon-containing insulating layer covering a first surface of the oxide layer adjacent to the gate line, and a second carbon-containing insulating layer covering a second surface of the oxide layer, opposite to the first surface of the oxide layer, adjacent to the contact plug.

Abstract: All-printed paper-based substrate memory devices are described. In an embodiment, a paper-based memory device is prepared by coating one or more areas of a paper substrate with a conductor material such as a carbon paste, to form a first electrode of a memory, depositing a layer of insulator material, such as titanium dioxide, over one or more areas of the conductor material, and depositing a layer of metal over one or more areas of the insulator material to form a second electrode of the memory. In an embodiment, the device can further include diodes printed between the insulator material and the second electrode, and the first electrode and the second electrodes can be formed as a crossbar structure to provide a WORM memory. The various layers and the diodes can be printed onto the paper substrate by, for example, an ink jet printer.

Abstract: A lead frame structure of a light emitting diode includes a ceramic bed, a metal layer and a plastic seat. The metal layer has a first metal circuit area, a second metal circuit area, a gap dividing the first metal circuit area and the second metal circuit area, and a metal ring surrounding the first metal circuit area, the second metal circuit area and the gap. The plastic seat has a hollow function area. The first metal circuit area, the second metal circuit area and a part of the metal ring expose the function area to make the metal (circuit) layer of the function area has no gap to avoid excess glue. This can efficiently accomplish to increase intensity, quality and reliability of the packaged products.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a first die including a signal pad region and a power pad region; a redistribution layer (RDL) over the first die; a plurality of first connectors over the RDL and at a side of the RDL opposite to the first die; a plurality of second connectors over the RDL and at the side opposite to the first die; a second die including a signal pad region and a power pad region, wherein the second die is face-to-face and electrically connected to the first die through the first connectors and the RDL, wherein a center of the second die is laterally shifted with respect to a center of the first die so as to correspond the signal pad region of the first die to the signal pad region of the second die. An associated method for fabricating the same is also disclosed.

Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a stacked body, a semiconductor member, a semiconductor portion, a first insulating film, and a charge storage film. The semiconductor member includes a first portion and a second portion, the first portion contacting with the semiconductor substrate, the second portion being provided on the first portion, contacting with the first portion, and having a second width smaller than a first width of the first portion in a first direction crossing a stacking direction. The first insulating film is provided on a side surface of the second portion. The charge storage film is provided on a side surface of the semiconductor portion, extends in the stacking direction, and includes a first portion located on an upper surface of the second portion of the semiconductor member.

Abstract: What is disclosed is a pixel array architecture for displays being based on a matrix of subpixels arranged in a rectilinear matrix oriented at an angle relative to a horizontal direction of the display, exhibiting a reduced pixel pitch for the subpixels.

Abstract: An electronic device may have control circuitry coupled to input-output devices such as a display. A flexible input-output device may be formed from an elastomeric substrate layer. The substrate layer may have signal paths to which components are mounted. Openings may be formed in the elastomeric substrate layer between the signal paths to create a stretchable mesh-shaped substrate. The electrical components may each include an interposer having solder pads soldered to the elastomeric substrate. Electrical devices such as micro-light-emitting diodes may be soldered to the interposers. The electrical components may also include electrical devices such as sensors and actuators. A stretchable lighting unit may have a stretchable light guide illuminated by a stretchable light source.

Abstract: A method of forming a vertical fin field effect transistor having a consistent channel width, including forming one or more vertical fin(s) on the substrate, wherein the one or more vertical fin(s) have a tapered profile, oxidizing the one or more vertical fin(s) to form an oxide by consuming at least a portion of the vertical fin material, and removing the oxide from the one or more vertical fin(s), wherein the one or more vertical fin(s) include a tapered upper portion, a tapered lower portion and a straight channel portion there between.

Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes a peripheral circuit gate pattern on a first substrate, an impurity region in the first substrate and spaced apart from the peripheral circuit gate pattern, a cell array structure on the peripheral circuit gate pattern, a second substrate between the peripheral circuit gate pattern and the cell array structure, and a via that is in contact with the impurity region and disposed between the first substrate and the second substrate. The via electrically connects the first and second substrates to each other.

Abstract: A silicon carbide semiconductor device includes a drift layer of a first conductivity type, a source region of the first conductivity type, an active trench formed in penetration through the source region, a base region, a termination trench formed around the active trench, a gate insulating film formed on a bottom surface, a side surface of the active trench, a gate electrode embedded and formed in the active trench with the gate insulating film interposed therebetween, a protective diffusion layer of a second conductivity type formed in a lower portion of the active trench and a part of a lower portion of the termination trench and having a first impurity concentration, and a termination diffusion layer of the second conductivity type formed on an outside of the protective diffusion layer in the lower portion of the termination trench and having a second impurity concentration lower than the first impurity concentration.

Abstract: A light-emitting device includes a light-emitting element configured to emit blue light, a first wavelength conversion member containing a Mn4+-activated fluorine complex phosphor, and a second wavelength conversion member containing a quantum-dot phosphor, in which the first wavelength conversion member and the second wavelength conversion member are spatially separated from each other.

Abstract: Provided is a substrate for a light emitting device having high reflectivity, high heat radiating properties, dielectric strength voltage properties, long-term reliability including heat resistance and light resistance, and excellent mass productivity. A substrate (20) for a light emitting device includes: a first insulating layer (11) having thermal conductivity which is formed on a surface of one side of a metal base (2); a wiring pattern (3) which is formed on the first insulating layer (11); and a second insulating layer (12) having light reflectivity which is formed on the first insulating layer (11) and on some parts of the wiring pattern (3), so that some parts of the wiring pattern (3) are exposed, in which the first insulating layer (11) is a layer of ceramic formed by thermal spraying.

Abstract: The present application provides an electrostatic discharge guard structure for photonic platform based photodiode systems. In particular this application provides a photodiode assembly comprising: a photodiode (such as a Si or SiGe photodiode); a waveguide (such as a silicon waveguide); and a guard structure, wherein the guard structure comprises a diode, extends about all or substantially all of the periphery of the Si or SiGe photodiode and allows propagation of light from the silicon waveguide into the Si or SiGe photodiode.

Abstract: A semiconductor package includes first bump pads on a first surface of an interconnection structure layer, elevated pads thicker than the first bump pads on the first surface of the interconnection structure layer, a first semiconductor device connected on the first bump pads, through mold ball connectors connected on the elevated pads, respectively, a molding layer disposed covering the first surface of the interconnection structure layer to expose a portion of each of the through mold ball connectors, outer connectors respectively attached to the through mold ball connectors, and a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer.

Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.

Abstract: A display panel is provided. The display panel has an active area and a border area out of the active area. The display panel includes a plurality of pixels, a first gate driver portion, a plurality of scan lines and a multiplexer portion. The pixels are located in the active area. The first gate driver portion is located in the border area. The scan lines are located in the active area, and connected to the first gate driver portion. The multiplexer portion is located in the border area. The multiplexer portion and the first gate driver portion at least partially overlap along a direction parallel to one of the plurality of scan lines.

Abstract: A fin field effect transistor (FinFET) on a silicon-on-insulator and method of forming the same are provided in the present invention. The FinFET includes first fin structure, second fin structure and an insulating layer. The first fin structure and the second fin structure are disposed on a substrate. The insulating layer covers the first fin structure and the second fin structure and exposes a first portion of the first fin structure and a second portion of the second fin structure. The first fin structure has a first height and the second fin structure has a second height different from the first height, and a top surface of the first fin structure and a top surface of the second fin structure are at different levels.

Abstract: A method of forming a strained channel for a field effect transistor, including forming a sacrificial layer on a substrate, forming a channel layer on the sacrificial layer, forming a stressor layer on the channel layer, wherein the stressor layer applies a stress to the channel layer, forming at least one etching trench by removing at least a portion of the stressor layer, channel layer, and sacrificial layer, wherein the etching trench exposes at least a portion of a sidewall of the sacrificial layer, and separates the stressor layer, channel layer, and sacrificial layer into two or more stressor islands, channel blocks, and sacrificial slabs, and removing the sacrificial slabs to release the channel blocks from the substrate using a selective etch, wherein the channel blocks adhere to the substrate surface.