Abstract: A semiconductor device includes a leadframe, a semiconductor chip, and an encapsulation resin encapsulating the leadframe and the semiconductor chip. The leadframe includes a first surface and a second surface facing away from the first surface. The semiconductor chip is mounted on the first surface of the leadframe. A part of the second surface of the leadframe is depressed toward the first surface to form a step surface. The step surface includes an uneven surface part where depressions are formed, and is covered with the encapsulation resin.

Abstract: A semiconductor device includes a chip, a plurality of first bumps, and a plurality of second bumps. The chip includes an active surface. The first bumps are disposed on the active surface along a first direction. The second bumps are disposed on the active surface along a second direction parallel to the first direction, wherein one of the second bumps is located between adjacent two of the first bumps, a closest distance from the second bumps to the fan-out region is smaller than a closest distance from the first bumps to the fan-out region, and a first width of one of the first bumps is larger than a second width of one of the second bumps.

Abstract: A heat-dissipating device includes at least one heat-dissipating surface and a micro-sized cooling mechanism formed directly on the heat-dissipating surface by an additive manufacturing process. The cooling mechanism includes at least one fluid passage, such as a micro-hose, for carrying a cooling medium from a coolant source directly to the heat-dissipating surface. The cooling mechanism is fluidly sealed to the heat-dissipating surface such that the cooling medium is in thermal contact directly with the heat-dissipating surface.

Abstract: A MOS RF surveillance and/or identification tag, and methods for its manufacture and use. The tag generally includes an interposer, an antenna and/or inductor on the interposer, and integrated circuitry on the interposer in a location other than the antenna and/or inductor. The integrated circuitry generally has a lowest layer in physical contact with the interposer surface. The method of manufacture generally includes forming a lowest layer of integrated circuitry on an interposer, forming successive layers of the integrated circuitry on the lowest layer of integrated circuitry, and attaching an electrically conductive functional layer to the interposer. Alternatively, an electrically conductive structure may be formed from a functional layer attached to the interposer.

Abstract: A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.

Abstract: A semiconductor memory device includes a first semiconductor layer; a stacked body including a plurality of electrode layers stacked in a first direction; a metal layer provided in the first direction between the first semiconductor layer and the stacked body; a second semiconductor layer extending in the first direction through the stacked body and the metal layer, and being electrically connected to the first semiconductor layer.

Abstract: Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.

Abstract: An interconnect structure in which the current capacity of an interconnect pattern involving a large amount of current is increased without preventing the miniaturization of signal lines and increasing the film thickness. The interconnect structure includes a resin layer; and interconnects formed on the resin layer, wherein the resin layer has a plurality of parallel grooves in an area in which the interconnects are formed, and the interconnects are formed of a plating film created on a resin layer front surface in the area, in which the interconnects are formed, and on inner wall surfaces of the plurality of grooves.

Abstract: An integrated circuit structure includes a first vertical transistor and a second vertical transistor. The first vertical transistor includes a first semiconductor channel, a first top source/drain region over the first semiconductor channel, and a first top source/drain pad overlapping the first top source/drain region. The second vertical transistor includes a second semiconductor channel, a second top source/drain region over the second semiconductor channel, and a second top source/drain pad overlapping the second top source/drain region. A local interconnector interconnects the first top source/drain pad and the second top source/drain pad. The first top source/drain pad, the second top source/drain pad, and the local interconnector are portions of a continuous region, with no distinguishable interfaces between the first top source/drain pad, the second top source/drain pad, and the local interconnector.

Abstract: There is set forth herein a method of fabricating a semiconductor structure, the method including forming a conductive metal layer over a source/drain region. The conductive metal layer in one aspect can prevent gouging of a source/drain region during removal of materials above a source/drain region. The conductive metal layer in one aspect can be used to pattern an air spacer for reduced parasitic capacitance. The conductive metal layer in one aspect can reduce a contact resistance between a source/drain region and a contact above a source/drain region.

Abstract: On an RAMO4 substrate containing a single crystal represented by the general formula RAMO4 (wherein R represents one or a plurality of trivalent elements selected from a group of elements including: Sc, In, Y, and a lanthanoid element, A represents one or a plurality of trivalent elements selected from a group of elements including: Fe(III), Ga, and Al, and M represents one or a plurality of divalent elements selected from a group of elements including: Mg, Mn, Fe(II), Co, Cu, Zn, and Cd), a buffer layer containing a nitride of In and a Group III element except for In is formed, and a Group III nitride crystal is formed on the buffer layer.

Abstract: A method of fabricating non-polar a-plane GaN/(Al,B,In,Ga)N multiple quantum wells (MQWs). The a-plane MQWs are grown on the appropriate GaN/sapphire template layers via metalorganic chemical vapor deposition (MOCVD) with well widths ranging from 20 ? to 70 ?. The room temperature photoluminescence (PL) emission energy from the a-plane MQWs followed a square well trend modeled using self-consistent Poisson-Schrodinger (SCPS) calculations. Optimal PL emission intensity is obtained at a quantum well width of 52 ? for the a-plane MQWs.

Abstract: A semiconductor device includes: a substrate; a nitride semiconductor layer on the substrate; a source electrode, a drain electrode and a gate electrode on the nitride semiconductor layer; and a SiN surface protective film covering the nitride semiconductor layer, wherein a composition ratio Si/N of Si and N that form a Si—N bond of the SiN surface protective film is 0.751 to 0.801.

Abstract: Provided is a display device including: a structure including a display area and a peripheral area surrounding the display area; and an inorganic encapsulation thin film disposed on the display and peripheral areas. The peripheral area includes at least one inorganic surface portion having a closed shape continuously.

Abstract: Disclosed herein is a packaged wafer manufacturing method including the steps of forming a groove along each division line on the front side of a wafer, each groove having a depth greater than the finished thickness of the wafer, next removing a chamfered portion from the outer circumference of the wafer to thereby form a step portion having a depth greater than the depth of each groove, next setting a die of a molding apparatus on the bottom surface of the step portion of the wafer in the condition where a space is defined between the die and the wafer, and next filling a mold resin into this space. Accordingly, the device area of the wafer is covered with the mold resin and each groove of the wafer is filled with the mold resin to thereby obtain a packaged wafer.

Abstract: A method of forming a vertical fin field effect transistor having a consistent channel width, including forming one or more vertical fin(s) on the substrate, wherein the one or more vertical fin(s) have a tapered profile, oxidizing the one or more vertical fin(s) to form an oxide by consuming at least a portion of the vertical fin material, and removing the oxide from the one or more vertical fin(s), wherein the one or more vertical fin(s) include a tapered upper portion, a tapered lower portion and a straight channel portion there between.

Abstract: Methods, systems, and apparatus for EM isolation structures. One of the apparatus includes a communication module, the communication module including: a printed circuit board; a plurality of integrated circuit packages, each integrated circuit package including at least one transmitter, receiver, or transceiver; and one or more metallic blocking structures configured to at least partially encircle a corresponding one of the plurality of integrated circuit packages, wherein each metallic blocking structure is configured to reduce signal leakage from the corresponding integrated circuit package.

Abstract: A method for forming patterns in a semiconductor device includes providing a substrate and a patterning-target layer formed over the substrate; forming a first feature in a first hard mask layer formed over the patterning-target layer; and forming a second feature in a second hard mask layer formed over the patterning-target layer. The first hard mask layer has a different etching selectivity from the second hard mask layer. The method further includes selectively removing a portion of the first feature within a first trench to form a reshaped first feature. In an embodiment, the first trench exposes a portion of the second feature, and the selectively removing of the first portion of the first feature does not etch the portion of the second feature.

Abstract: Embodiments of the disclosure described herein comprise a tunneling field effect transistor (TFET) having a drain region, a source region having a conductivity type opposite of the drain region, a channel region disposed between the source region and the drain region, a gate disposed over the channel region, and a heterogeneous pocket disposed near a junction of the source region and the channel region. The heterogeneous pocket comprises a semiconductor material different than the channel region, and comprises a tunneling barrier less than the bandgap in the channel region and forming a quantum well in the channel region to in crease a current through the TFET transistor when a voltage applied to the gate is above a threshold voltage.

Abstract: An optical apparatus including an optical functional layer having a high refractive index and a method of manufacturing the optical apparatus are provided. The optical functional layer includes a phase change material that has a first refractive index during heat treatment in a first temperature range and has a second refractive index, which is higher than the first refractive index, during heat treatment in a second temperature range that is higher than the first temperature range. The optical functional layer may be configured to have the second refractive index by using a micro-heater without having to be deposited at a high temperature.