Abstract: A network port includes a connection port, a PD unit, a PSE unit, a control unit, and a switch unit. The connection port is connected to an external Ethernet port. The control unit determines a type of the external Ethernet port and outputs determination signal correspondingly. The switch unit selectively connects the PSE unit to the connection port, or connects the PD unit to the connection port according to the determination signal output by the control unit. An Ethernet device is also provided. The network port and the Ethernet device integrate PD and PSE in a port, and switch to corresponding PSE mode or PD mode automatically according to the PSE device or PD device.

Abstract: In one embodiment execution units, graphics cores, or graphics sub-cores can be dynamically scaled across a frame of graphics operations. Available execution units within each graphics core may be scaled using utilization metrics such as the current utilization rate of the execution units and the submission of new draw calls. In one embodiment, one of more of the sub-cores within each graphics core may be enable or disabled based on current or past utilization of the sub-cores based on a set of current graphics operations.

Abstract: A battery control device includes: a battery; a storage circuitry configured to store a disconnection time which indicates a time at which a power supply is disconnected; and a diagnosis circuitry configured to, when the power supply is reactivated, diagnose a charge capacity of the battery at the time of reactivation based on a disconnection period obtained from the disconnection time and a time at when the power supply is reactivated, a temperature of the battery in a state during the power supply is disconnected and a deterioration degree of the battery.

Abstract: A method and system for cascading power consumption is described herein. The method may include providing power to a first sensor and a second sensor, wherein the first sensor consumes more power than the second sensor. The method may also include detecting the first sensor does not capture a sample of data. In addition, the method may include stopping the flow of power to the first sensor. Furthermore, the method may include monitoring an operating environment with the second sensor. The method may also include providing power to the first sensor in response to the second sensor detecting a sample of data.

Abstract: In an embodiment, a processor includes first logic to determine first power to be provided to a first portion of a computational resource during a time period. The first portion may be reserved for execution by the processor of a first workload to be executed during the time period. The first power may be determined based at least in part on the first workload and independently of a second workload. The processor may include second logic to determine second power to be provided to a second portion of the computational resource during the time period. The second portion may be reserved for execution by the processor of the second workload during the time period. The second power may be determined based at least in part on the second workload and independently of the first workload.

Abstract: The voltage applied to an integrated circuit is scaled so as to account for variations in the manufacturing processes, temperature, and the like, and to allow for power/performance optimization of the integrated circuit. The integrated circuit may characterized during a manufacturing test or anytime thereafter. The characterization data, which reflects the performance and power consumption of the integrated circuit, is used to determine an associated processing/speed bin, which in turn, defines the voltage that will be applied to the integrated circuit during normal operation. Optionally, a number of different supply voltages are applied to different circuit blocks disposed in the same integrated circuit. Each such circuit block may have a different characterization data associated with a different supply voltage.

Abstract: Embodiments of a method and apparatus are described for operating a mobile computing device in different modes using different operating systems. An apparatus may comprise, for example, a memory operative to store multiple operating systems, a processor operative to execute the multiple operating systems, an operating system management module operative to select a first operating system when the mobile computing device is in a first mode or a second operating system when the mobile computing device is in a second mode and the mobile computing device is coupled to one or more external devices. Other embodiments are described and claimed.

Abstract: A method and system are disclosed for placing a computer in a safe and secure lock down state from a remote location using a remote command device such as a cellular telephone. The method and system includes optional security provisions before restarting the computer.

Abstract: An electronic device with a power management mechanism and a power management method thereof are disclosed. The electronic device includes a multi-core processor and a temperature sensor. The multi-core processor has a plurality of processor cores. The temperature sensor is coupled to the multi-core processor. The temperature sensor detects the temperature of the multi-core processor and determines whether the electronic device enters an underclocking mode from a performance priority mode according to the detected temperature. When the temperature of the multi-core processor is greater than a first temperature threshold, the multi-core processor controls the electronic device to enter a first underclocking mode and dynamically adjusts an enabled core number. When the temperature of the multi-core processor is greater than a second temperature threshold, the multi-core processor controls the electronic device to enter a second underclocking mode.

Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

Abstract: In an active mode, a VDD line receives an internal power supply voltage from an external regulator. A VDD_RAM line receives an internal power supply voltage from an internal regulator. A PMOS switch includes a first PMOS transistor having a source and an N-type well connected to the VDD line, and a second PMOS transistor having a source and an N-type well connected to the VDD_RAM line and a drain connected to a drain of the first PMOS transistor. The first PMOS transistor is controlled based on a control command from a system control circuit and a voltage of the VDD_RAM line. The second PMOS transistor is controlled based on the control command and a voltage of the VDD line.

Abstract: The present invention relates to a method for controlling the operation of an electronic device for processing data, said device comprising at least one computational unit for receiving input data and processing said input data for generating output data, and further comprising a control unit for receiving at least a part of said input data and delivering at least one control signal to said at least one computational unit for controlling the operation of said at least one computational unit, characterized in said control unit using said input data to determine a computational effort and further using said control signal to control parameters of said at least one computational unit depending on said computational effort, wherein said parameters comprise a combination of: clock rate and/or supply voltage; and process complexity.

Abstract: This invention includes apparatus, systems, and methods for repairing a corrupted device still in the field by sending the corrupted device a known-good configuration derived from the majority group of devices in the field. First, an initial inventory and content scan of the device's hardware and software stack is taken. The attestation server uses the collection of results to determine a statistically known-good configuration for each type of device. The attestation server groups the known good devices by devices and ideally all of the devices of the same type are configured mostly the same. The attestation server sends an alert to the device that the device is configured differently than the plurality of existing devices. Finally, the attestation server will request a known-good configuration from one of the devices in the plurality of existing devices to repair the corrupted device in the field.

Abstract: A voltage control circuit includes a processing unit, a power control circuit, a first impedance circuit, a first switch, and a current source. The power control circuit is used for outputting a core voltage to the processing unit. The first switch and the first impedance circuit are connected in parallel between the processing unit and the power control circuit, and they feedback a feedback voltage to the power control circuit. The current source is used for providing or extracting an operating current via the first impedance circuit or the first switch. The first switch is turned on and the processing unit receives a first core voltage when the processing unit operates at a normal mode. The first switch is turned off and the processing unit receives a second core voltage when the processing unit operates at an overvoltage mode.

Abstract: Described is an apparatus which comprises: an input for providing a first voltage signal; a level translator, coupled to the input, to translate the first voltage signal to a second input voltage, the second input voltage having a voltage level higher than a voltage level of the first voltage signal; and an open loop reference core coupled to the level translator, the open loop reference core to receive the second input voltage and to generate an output indicating whether the first voltage signal is above or below a reference level.

Abstract: An information processing apparatus which operates in one of a normal power state and a plurality of power saving states, includes a storage unit to store power saving information that designates one of the plurality of power saving states, an acquisition unit to acquire from the connected peripheral device identification information for identifying the peripheral device, a specification unit to specify the power saving information associated with the acquired identification information based on the identification information and the setting information, and a control unit to control the apparatus to shift to the power saving state designated by the power saving information to the power saving state that is designated by the specified power saving information.

Abstract: A method of displaying power consumption by receiving information regarding Real Time Pricing (RTP) in which a power rate varies according to time; receiving power consumption amounts; and displaying predetermined visual displaying means based on the RTP information and the received power consumption amounts.

Abstract: An information processing apparatus includes a memory and a processor coupled to the memory. The processor is configured to: determine whether or not a difference between a total of power consumption values of physical or virtual computers and a preset upper-limit value satisfies a certain condition; select, in ascending order of priorities stored in a first storage and set based on details of processing executed by the computers, any of the computers as a target whose power consumption is to be reduced, when the difference satisfies the certain condition; and switch the computer selected to a state in which the power consumption is reduced.

Abstract: Apparatuses and methods are provided for reducing power consumption in a pattern-recognition processor. A power control circuit may be coupled to a block of programmed state machines to enable selective activation and deactivation of the block during a pattern search. The block may be deactivated if the pattern search is no longer active in that block and activated when needed by the pattern search. Additionally, the block may be deactivated based on an identifier of the data stream being searched. Excess blocks not used for any programmed state machines may be disabled such that they are not refreshed during a memory cycle.

Abstract: A system for generating a power consumption model of at least one server includes one or more computers configured to obtain n time series telemetry signals indicative of operating parameters of the at least one server, obtain a time series power signal indicative of power consumed by the at least one server, and correlate each of the n time series telemetry signals with the time series power signal. The one or more computers are further configured to select a set of the n time series telemetry signals having an overall correlation with the time series power signal greater than a predetermined threshold, and generate a power consumption model of the at least one server based on at least the set of the n time series telemetry signals.