Abstract: To start-up a computer system promptly at the time of power-on. The system includes an expansion card having an initialization command set in advance and a main body unit on which the expansion card is mounted. The main body unit includes a central processing section for executing initialization of the expansion card at the time of power-on based on the initialization command, a history holding section for storing the initialized expansion card, and a dictionary section for storing a common command which is the initialization command common to different expansion cards. The central processing section executes the common command, and also executes the initialization command set in the expansion card other than the expansion card stored in the history holding section and not included in the common command.

Abstract: In accordance with some embodiments, margining routines to determine acceptable voltage command values for specific CPU implementations at one or more different operating levels may be provided.

Abstract: A technique for rate verification of an incoming serial alignment sequence includes receiving an incoming serial stream. A determination is then made as to whether an align sequence is recognized in the incoming serial stream. When an align sequence is recognized, a check is made to determine if an appropriate number of align primitives are received during a predetermined number of clock periods. If the number of received align primitives matches the predetermined number, then a rate-verified align detect signal is asserted.

Abstract: Methods and devices for reducing power consumption in a multi-processor computing device include filtering indications from the second processor intended for the first processor while the first processor is in a low power state, so that only selected, such as significant, indications are transmitted. The second processor may be informed when the first processor is in a low power state. Indications generated by the second processor may be compared to indication filtering criteria to determine whether each should be transmitted to the first processor. Those indications satisfying the indication filtering criteria may be sent to the first processor, causing it to return to a normal power state. In mobile computing device the first processor may be an applications processor and the second processor may be a modem. Filtering of indications may be accomplished in the second processor or in a power controller in some implementations.

Abstract: An apparatus, method and program product for optimizing core performance and power in of a multi-core processor. The apparatus includes a multi-core processor coupled to a clock source providing a clock frequency to one or more cores, an independent power supply coupled to each core for providing a supply voltage to each core and a Phase-Locked Loop (PLL) circuit coupled to each core for dynamically adjusting the clock frequency provided to each core. The apparatus further includes a controller coupled to each core and being configured to collect performance data and power consumption data measured for each core and to adjust, using the PLL circuit, a supply voltage provided to a core, such that, the operational core frequency of the core is greater than a specification core frequency preset for the core and, such that, core performance and power consumption is optimized.

Abstract: An apparatus, system, and method are disclosed for resetting and bypassing microcontroller stations. A command module asserts and de-asserts a reset line in response to a command. A reset module resets a microcontroller station if the command module asserts and de-asserts the reset line within a time interval. In addition, the reset module bypasses the microcontroller station if the command module asserts and holds the reset line for a time period exceeding the time interval.

Abstract: A memory power supply control circuit includes a number of memory slots, a platform controller hub (PCH), a first synchronous rectification driver, a number of second synchronous rectification drivers, and a complex programmable logic device (CPLD). The PCH is connected to the memory slots. The first synchronous rectification driver maintains a working state at all time. The CPLD is connected between the PCH and the second synchronous rectification drivers. The CPLD receives information from the PCH to determine a number of used memory slots, and controls the working states of the second synchronous rectification drivers according to the number of used memory slots.

Abstract: Aspects of the disclosure provide a method for power mode switching. The method includes sending a pausing request to an application executed in an electronic system. The pausing request informs the application of an intent to switch the electronic system from an active mode to a power saving mode that causes the electronic system to pause executing the application. Then, the method includes determining that the application accepts the pausing request, and configuring the electronic system into the power saving mode, such that the application pauses at a pausing point determined in response to the pausing request.

Abstract: An apparatus, system, and method are disclosed for suspend-resume scheduling in conjunction with an operation requiring a suspend-resume cycle of a computer 200, including updating, for purposes of system configuration management, a non-volatile memory 506, such as an electrically erasable programmable read-only memory (“EEPROM”) 702. A control module 402 sends 806 a request to update the EEPROM 702. A suspend module 404 suspends 818 an operating system 204. A standby module 406 prepares 904 the computer 200 to enter a standby state, estimates 914 a sufficient amount of time to enter the standby state, places 916 the estimate into an alarm register 608, and then enters 918 the standby state. An update module 308 exits 1004 the standby state in response to an alarm signal 612, receives the request if present 1008, writes 1012 the EEPROM 702 with the updated information, and resumes 1018 the operating system 204.

Abstract: Exemplary methods, system, and computer program product embodiments for managing services within a data storage subsystem using a processor in communication with a memory device during a startup sequence are provided. At least one service facilitated by a provider is provided. At least one requirement is linked to the at least one service. The at least one service and the at least one requirement are incorporated into a specification file. A directed acyclic graph, interrelating the at least one service and an additional service based on the at least one requirement, is constructed. The directed acyclic graph is traversed using an initialization process to generate a determination which of an available plurality of services to provide. The determination further includes an analysis of the which of the available plurality of services to provide in view of at least one hardware resource in the data storage subsystem.

Abstract: Methods, apparatus, and computer-readable media for executing the same program module in a PEI phase and a DXE phase are disclosed. According to one method, a program module is first executed in the PEI phase. While the program module is executing in the PEI, it stores the memory address of a DXE entry point in a hand-off block. When the DXE phase is entered, the stored DXE entry point for the program module is retrieved from the hand-off block and the program module is executed at the DXE entry point.

Abstract: Methods, apparatus, and products are disclosed for reducing power consumption during execution of an application on a plurality of compute nodes that include: powering up, during compute node initialization, only a portion of computer memory of the compute node, including configuring an operating system for the compute node in the powered up portion of computer memory; receiving, by the operating system, an instruction to load an application for execution; allocating, by the operating system, additional portions of computer memory to the application for use during execution; powering up the additional portions of computer memory allocated for use by the application during execution; and loading, by the operating system, the application into the powered up additional portions of computer memory.

Abstract: A booting system including a boot code transmission control unit to sequentially execute a booting operation concurrently with storing boot codes stored in a NAND flash memory in an internal memory. The boot code transmission control unit includes storage units to store addresses of the boot codes stored in the internal memory and an address of a boot code to be accessed by a CPU core for the execution of the booting operation, respectively. These addresses are checked by monitoring a memory interface and a bus interface. When the boot code addresses are the same, the boot code transmission control unit transmits a boot code corresponding to the same address, among the boot codes stored in the internal memory, to the CPU core so that the CPU core can sequentially execute the booting operation.

Abstract: An illustrative method imports configuration data used by a server that supports electronic gaming machines (EGMs). Configuration data is used by operational software of the server that supports EGMs in a server-client relationship and is stored in accord with a first data structure template that defines records having fields that contain information of the configuration of each EGM. Configuration data stored in fields of records in accord with the first data structure template is automatically transferred to corresponding fields of records in accord with a second data structure template used by new operational software of the server by migration software.

Abstract: A clock signal may be aligned with a data signal by delaying the signals relative to each other until an edge of one signal aligns with an edge of the other signal, and then causing an inversion of the clock signal. A further variation may limit the relative delay period to one-half clock cycle and may use a double inversion of the clock signal.

Abstract: Disclosed herein is power controller for use with a graphics processing unit. The power controller monitors, manages and controls power supplied to components of a pipeline of the graphics processing unit. The power controller determining whether and to what extent power is to be supplied to a pipeline component based on status information received by the power controller in connection with the pipeline component. The power controller is capable of identifying a trend using the received status information, and determining whether and to what extent power is to be supplied to a pipeline component based on the identified trend.

Abstract: A power supply connected to an electrical load that supplies an output voltage to the electrical load. The power supply includes a first portion having a fast transient response topology that supplies a first part of an output current, and a second portion having a slow transient response topology that supplies a second part of the output current, such that the second part of the output current does not increase or decrease as fast as the first part of the output current. Advantageously, embodiments of the invention provide a more efficient power supply design that converts part of the total power supply output current using a fast transient response portion and part using a slow transient response portion of the power supply. Additionally, embodiments of the invention provide an alternate current path for transporting large amounts of current to a GPU, while maintaining the efficiency of the overall current path.

Abstract: A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others.

Abstract: A method and an apparatus for controlling voltage level and clock signal frequency supplied to a system.

Abstract: Universal serial bus wakeup when the bus is not powered. In one embodiment, a method of waking up a universal serial bus (USB) from a non-powered state, comprises: upon detection of a wakeup condition, a wakeup generation module associated with a USB device generating a wakeup signal on a power line of a USB bus coupled to the USB device, or on a single-wire sideband; and a host wakeup module detecting the wakeup signal and causing the USB bus that is coupled to the USB device to be supplied with power.