Abstract: A method for managing power consumed by storage systems and other devices is disclosed herein. In certain embodiments, such a method may include initially monitoring conditions (such as data traffic conditions) on a communication link between a first device and a second device. The method may further include determining whether the conditions on the communication link warrant powering down or powering up the second device. In the event the conditions warrant powering down the second device, a power-down command may be generated and transmitted from the first device to the second device. In the event the conditions warrant powering up the second device, a power-up command may be generated and transmitted from the first device to the second device. In selected embodiments, the power-up and power-down commands are one of SCSI commands and FICON commands. A corresponding apparatus, system, and computer-usable medium are also disclosed and claimed herein.

Abstract: A state machine and an external interface, including its associated input-outputs (IOs), are always powered on and used to manage the chip power modes and power mode transitions. The chip power modes are defined as RUN, HIBERNATE, POWERDOWN, with many more possible with this invention. For example, once the device is in HIBERNATE or POWERDOWN modes, the power supplies to the IC are either reduced, or completely disconnected except for this controller state machine. This invention's state machine and control mechanism, in response to some external “wake up event”, will bring the chip to RUN mode by managing the state of the external power supplies through its control interface. The implementation achieves small die size and extreme low power consumption.

Abstract: In a method of controlling the power state of a peripheral device, the peripheral is changed from a first power state to a second power state in response to communications across a network connected to the peripheral indicating that a user is proximately located to the peripheral. A user may be determined to be proximately located to the peripheral by monitoring communications across the network to detect traffic that is associated with a user logging onto a computer that can utilize the peripheral, by discovering a wireless terminal that is associated with a user and which is proximately located to the peripheral, by receiving information from a cellular communication network across the network that indicates that a user of the peripheral is proximately located to the peripheral, and/or in response to a time of day and/or day of week/month schedule.

Abstract: A power-sourcing equipment (PSE) has a powered communications interface to which a powered device (PD) is coupled. The PD presents a valid PD signature indicating that the PD is attached and capable of receiving normal operating power from the PSE. Per a power-withholding policy, the PSE operates in a power-withholding state to withhold the normal operating power notwithstanding the valid PD signature, and monitors for a signal via the powered communications interface indicating that the normal operating power should be delivered to the PD. The signal may be an alternative signature generated by a user-activated switch for example. In response to receiving the signal in the power-withholding state, the PSE enters a power-providing state in which it provides the normal operating power to the PD notwithstanding the power-withholding policy. An intermediate device (dongle) may be employed to generate the signal.

Abstract: Multiple modules are connected to a signal output module via first and second busses. Different commands may be transmitted on the two busses. Both busses may be hierarchically constructed so that all units are connected one after the other in a chain like manner on the busses. The modules cooperate to transition an output signal between different duty cycles and activate and deactivate responsive to timer comparisons.

Abstract: Apparatus and systems provide processing capabilities and power-line networking capabilities. An in-wall computing device has a power connector for receiving an Alternating Current (AC) signal from a power source and a housing that is sized for installation into an electrical wall box. The device may have internal data injection circuitry for injecting data into the AC signal or may have internal data receiving circuitry for extracting data from the AC signal. A system includes at least two in-wall computing devices, each having a power connector for receiving an AC signal from a power source. A first device has a user input interface and internal data injection circuitry for transmitting user input data to a second device over the AC signal. The second device has internal data receiving circuitry for extracting the user input data and controlling peripherals attached to peripheral ports of the device according to the data.

Abstract: For controlling power sequence in a blade center environment, a relationship component module creates a topology of interdependent relationships of devices in the blade center environment. The devices include server blades, storage blades, and switch modules. A sequence module defines a sequence of the devices in the blade center environment to power off and on based on the topology of interdependent relationships. The sequence includes an order of a first independent blade server, each dependent storage blade of the first independent blade server, and a second independent blade server. A monitor component module monitors a command from an Advanced Management Module (AMM) to regulate power for the devices in the blade center environment. The AMM regulates power within the blade center. A validation module validates that the command does not violate the interdependent relationships and the sequence of devices or else blocks the command if the command is not validated.

Abstract: A device is provided that includes a chip having a processor and wake-up logic. The device also includes power management circuitry coupled to the chip. The power management circuitry selectively provides a core power supply and an input/output (I/O) power supply to the chip. Even if the power management circuitry cuts off the core power supply to the chip, the wake-up logic detects and responds to wake-up events based on power provided by the I/O power supply.

Abstract: The present invention is directed to the automatic configuration of portal composite applications.

Abstract: A device, computer system, and method are disclosed. In one embodiment, the device includes a memory buffer driver circuit that can drive signals on a memory channel at a given voltage level. The voltage at the voltage level is supplied to the memory buffer driver circuit from a rail of a power delivery network. The voltage level exhibits a repeatable fluctuation cycle at a resonant frequency of the power delivery network. The device also includes an on-die termination logic circuit that asserts a first termination resistance on the memory channel after the memory channel enters an idle state but before the voltage level reaches a peak of the repeatable fluctuation cycle. The on-die termination logic circuit then deasserts the first termination resistance on the memory channel at a later point in time.

Abstract: This invention provides an information processing apparatus which includes a first storage unit and a second storage unit and implements a function of causing the first storage unit and the second storage unit to store data redundantly while maintaining a power saving mode even upon receiving an access request from an external apparatus in the power saving mode, and a method of controlling the same. To accomplish this, upon receiving an HDD access request in the power saving mode, the information processing apparatus operates after transiting to an HDD access mode in which only minimum necessary functions are activated without activating the main CPU. The contents of the HDD changed during the HDD access mode are stored as history information. Upon transiting from the power saving mode to the normal operating mode, the data in another HDD is updated in accordance with the history information, thereby implementing a mirroring function.

Abstract: In some embodiments, the invention involves a method and apparatus for secure/authenticated local boot of a host operating system on a computing platform using active management technology (AMT) with a third party data store (3PDS)-based ISO firmware image. A portion of non-volatile memory is hardware secured against access by the host processor and OS, and accessible only to the AMT. The AMT comprises an AT/ATAPI protocol emulator to access an ISO boot image from secured memory, while appearing to the host processor as a communication with an AT/ATAPI device. Other embodiments are described and claimed.

Abstract: Methods and apparatus relating to optimization of performance and/or power consumption during memory power down state are described. In an embodiment, a memory controller may include logic to cause one or more ranks of a DIMM to enter a clock enable slow mode. Other embodiments are also described.

Abstract: A system and method for multiple power over Ethernet (PoE) power supply management. Power supply status signals indicative of an operating condition of a plurality of PoE power supplies are provided to a plurality of power sourcing equipment (PSE) controller chips. Pre-configured combination logic within each of the PSE controller chips converts an indicated operational state of the plurality of PoE power supplies into a powering decision for each of the Ethernet ports served by the PSE controller chip within one microsecond.

Abstract: A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others.

Abstract: Apparatus and systems provide processing capabilities while utilizing power received via an Ethernet. A computing device has an Ethernet connector for receiving power and data, internal power supply circuitry for extracting power from the Ethernet connector, and a Central Processing Unit (CPU) for receiving the power. A housing may encompass the components of the computing device and be configured for installation in an electrical wall box. The housing may include a display or connectors for peripherals. A system includes at least two computing devices. Each device has an Ethernet connector for receiving power and communicating with other devices and are installed within a housing within an electrical wall box. One device has a display for receiving user input instructions for transmittal to another device, while another device has a peripheral connector for controlling a peripheral according to the instructions.

Abstract: A power switching circuit of a portable electronic device is disclosed. The portable electronic device can be coupled to an expansion device. The power switching circuit includes a first power terminal, a second power terminal, a first switch module, a second switch module, and a power pin. The first switch module is coupled to the first power terminal. The second switch module is coupled to the second power terminal. The power pin is coupled to the first switch module and the second switch module, respectively. When the portable electronic device is not coupled to the expansion device, the first switch module and the second switch module are turned off, such that first power provided by the first power terminal and second power provided by the second power terminal fail to be provided for the power pin via the first switch module and the second switch module.

Abstract: An information processing apparatus includes: a first recording medium that stores a first system controller for allowing to execute boot processing of the information processing apparatus and is accessed by using a first access path in a tree structure or by using a second access path based on a first conversion table representing a correspondence between the first and second access path; a memory disk generation section allowing to secure a memory disk section that operates as a second recording medium and is accessed by using a third access path; a conversion table generation section allowing to generate a second conversion table representing a correspondence between the second and third access path; and a duplication controller allowing to copy the first system controller onto the memory disk section as a second system controller and allowing to duplicate the first and second system controllers based on the second conversion table.

Abstract: A method performs statistical static timing analysis of a network that includes a phase-locked loop and a feedback path. The feedback path comprises a set of delays operatively connected from the output of the phase-locked loop back to the input of the phase-locked loop. One embodiment herein computes a statistical feedback path delay for the feedback path. The method can use a separate statistical parameter to represent random uncorrelated delay variation for each delay in the feedback path. The method also computes an output arrival time for the phase-locked loop based on the negative of the statistical feedback path delay.

Abstract: The disclosed embodiments provide a synchronization circuit that supports multiple parallel reads and writes. This synchronization circuit includes multiple coupled data storage locations that synchronize data and control signals between two time domains and control logic that facilitates simultaneously accessing a variable number of such data storage locations in the same clock cycle. During operation, the synchronization circuit receives a request to simultaneously access (e.g., read and/or write) two or more synchronized data storage locations. In response to the request, the control logic in the synchronization circuit determines whether the present state of the synchronization circuit can accommodate the request, and if so, simultaneously accesses two or more synchronized data storage locations.