Abstract: Implementations of power management in a device are described. The device includes a power driver configured to manage power supply to one or more components in system-on-chip (SOC) hardware. The device further includes power subsystems configured as drivers for controlling the components of the SOC hardware and a user interface configured to receive a selected power mode as an input and identify profiles of one or more applications being executed in the device. Based on the selected power mode, the power driver directs the power subsystems to change a mode of operation of at least one component determined from the profiles of the one or more applications being executed.

Abstract: A computer-readable storage medium stores a control program for an information processing apparatus that includes a process unit capable of executing an application program. The control program causes the information processing apparatus to execute a process. The process includes acquiring control information included in the application program, generating association information associating the application program with response performance information in accordance with the control information acquired in the acquiring, type information associating a combination of control information with a type of the application program, and response performance information associated with a type of the application program, and controlling operating frequency of the process unit in accordance with the response performance information corresponding to the application program when the application program described in the association information is operating.

Abstract: Embodiments of methods, systems, and apparatuses for configuring a hardware device in a platform are described. In an exemplary method, a configuration message is received that indicates that the hardware device is to be upgraded from a first configuration to a second configuration, wherein the first and second configurations were pre-determined based on previous testing of the hardware device and are stored in the hardware device. The hardware device is then configured to the second configuration.

Abstract: A method of operating a computing device to allow events to be conditionally executed based on a power state of the device at the time of execution of the events. Conditional execution may be implemented using multiple timers, each associated with a power state. A timer such as an “AC timer” or a “DC timer” associated with a respective power state may be used to wake up the device when, upon expiration, or time-out, of the timer, a current power state of the device and the power state associated with the timer match. An Advanced Configuration Power Interface (ACPI) may be employed to abstract implementation of the timers from underlying hardware of the device. The operating system and software applications may request establishing wake-up behavior of the device as commands to program conditional events, which may then be translated into commands to embedded controller to set the timers.

Abstract: Systems and methods for discrete power control of components within a computer system are described herein. Some illustrative embodiments include a system that includes a subsystem with a plurality of components (configurable to operate at one or more power levels), a control register (coupled to the plurality of components) including a plurality of bits (each uniquely associated with a one of the plurality of components), and a power controller coupled to, and configurable to cause, the plurality of components to operate at the one or more power levels. The power controller asserts a signal transmitted to the subsystem, commanding the subsystem to transition to a first power level. A first of the plurality of components, associated with an asserted bit of the control register, operates at a second power level corresponding to a level of power consumption different from that of the first power level indicated by the power controller.

Abstract: The disclosed systems and methods relate to improving PCI Express (PCI-E) L1 Active State Power Management (ASPM) exit latency by speculatively initiating early L1 exit based on a network stimulus. Aspects of the present invention may enable a higher level of performance and responsiveness while supporting the benefits of ASPM. Aspects of the present invention may minimize operational cost by reducing latency in processes that utilize a PCI-E interface. Aspects of the present invention may be embodied in a Network Interface Controller (NIC) or any other device with a PCI-E interface that supports ASPM.

Abstract: A booting method and a computer system thereof, suitable for rebooting the computer system when a setting value of a basic input output system (BIOS) is modified, are provided. When a modified setting value causes a situation in which a main power is cut off in advance and the computer system is rebooted, a control command is sent to a signal generator for controlling the signal generator to generate a control signal through the BIOS. Then, the control signal is transmitted to a switch by the signal generator for controlling the switch to be turned on or turned off. Afterwards, a power-failure signal transmitted by a chipset is changed by the switch, such that a power supply provides the main power continuously to reboot the computer system.

Abstract: A computer system is provided. In one embodiment, the computer system includes a memory, a peripheral device, a central processing unit (CPU), and a peripheral device controller. The CPU stores information about the data transmission in a descriptor in the memory when data transmission between the CPU and the peripheral device is required. The peripheral device controller reads the descriptor from the memory at an access frequency, records whether the descriptor read from the memory requests for data transmission as a recording result, and adjusts the access frequency according to the recording result.

Abstract: A network processor includes a transceiver circuit, a network data processing unit, and a clock signal control unit. The transceiver circuit transmits and receives a network signal, compares a voltage level of the network signal with a threshold value, outputs a comparison result, and operates under a first clock signal. The network data processing unit is coupled to the transceiver circuit to process the network signal, and operates under a second clock signal different from the first clock signal. The clock signal control unit disables supply of the second clock signal to the network data processing unit when the voltage level is smaller than the threshold value, and enables supply of the second clock signal to the network data processing unit when the voltage level is not smaller than the threshold value. An energy saving method for a network processor is also disclosed.

Abstract: Methods and systems for operating a semiconductor device (e.g., a microprocessor) are described. The microprocessor is initially operated at a voltage and frequency that would be within operating limits at any device temperature. Using models that relate device temperature, operating limits and power consumption with voltage and frequency, the amount of supply voltage and a new operating frequency can be selected. The models are periodically consulted thereafter to continue adjusting the supply voltage and operating frequency, so that the microprocessor is caused to operate at very close to its capacity, in particular in those instances when, for example, processor-intensive instructions are being executed.

Abstract: An electronic device with a power management mechanism and a power management method thereof are disclosed. The electronic device includes a multi-core processor and a temperature sensor. The multi-core processor has a plurality of processor cores. The temperature sensor is coupled to the multi-core processor. The temperature sensor detects the temperature of the multi-core processor and determines whether the electronic device enters an underclocking mode from a performance priority mode according to the detected temperature. When the temperature of the multi-core processor is greater than a first temperature threshold, the multi-core processor controls the electronic device to enter a first underclocking mode and dynamically adjusts an enabled core number. When the temperature of the multi-core processor is greater than a second temperature threshold, the multi-core processor controls the electronic device to enter a second underclocking mode.

Abstract: An important component in digital circuits is a phase rotator, which permits precise time-shifting (or equivalently, phase rotation) of a clock signal within a clock period. A digital phase rotator can access multiple discrete values of phase under digital control. Such a device can have application in digital clock synchronization circuits, and can also be used for a digital phase modulator that encodes a digital signal. A digital phase rotator has been implemented in superconducting integrated circuit technology, using rapid single-flux-quantum logic (RSFQ). This circuit can exhibit positive or negative phase shifts of a multi-phase clock. Arbitrary precision can be obtained by cascading a plurality of phase rotator stages. Such a circuit forms a phase-modulator that is the core of a direct digital synthesizer that can operate at multi-gigahertz radio frequencies.

Abstract: A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others.

Abstract: A method, computer program product, and computing system for decoupling a cooling fan within a computing device from a line voltage power supply. The cooling fan within the computing device is coupled to a battery backup unit. The cooling fan is energized for a defined test period. One or more battery statistics are monitored during at least a portion of the defined test period.

Abstract: A power-saving network management server, which is coupled to a network system including a network device and manages a state of power to the network device, wherein the power-saving network management server is configured to: store network configuration information and task allocation information; determine starting or stopping of the power supply to the port of the network device based on the updated network configuration information and task allocation information; store a determination result of the starting or stopping of the power supply to the port as a port determination result; and control the power supply to the port of the network device based on the port determination result.

Abstract: An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.

Abstract: A navigation device for a vehicle includes: a memory device including a NAND type flash memory for storing a predetermined program and a boot program and a controller for searching a failure block in the flash memory and managing a corresponding relation between a logic block and a physical block with eliminating failure blocks; a back-up power source; a power source switch for coupling the memory device with the back-up power source; a power source for generating a predetermined voltage with using the back-up power source; a control device energized from the power source with the predetermined voltage so as to be activated; and a power source control device. The control device determines whether activation is performed for the first time. The control device executes a stand-by process, and then, executes a boot process when the activation is performed for the first time. The control device executes the boot process without executing the stand-by process when the activation is after the first time.

Abstract: In a computer system, a standby master processor is configured to serve as a backup processor for an active master processor. A third party replica processor is configured to monitor and record changes on the active master processor when the active master processor is executing, and is further configured to synchronize itself with the standby master processor when the standby master processor takes over execution from the active master processor. Logs of changes are maintained. A negotiation occurs between the standby master processor and the third party replica processor to determine the status of the logs of the standby master processor and the third party replica processor, and logs are applied or paused relating to one or more of the standby master processor and the third party replica processor to synchronize the standby master processor and the third party replica processor.

Abstract: A booting method for low temperature environment and an electronic apparatus therefor are provided. The booting method includes the following steps: reading a booting process record from a memory unit of the electronic apparatus; executing a booting process according to the booting process record, wherein the booting process includes a plurality of booting subroutines; and when executing one of the booting subroutines, updating the booting process record stored in the memory unit of the electronic apparatus corresponding to the booting subroutine, wherein the booting subroutines include providing a power output by controlling a power supply unit of the electronic apparatus, and an output value of the power output gradually increases as executing the booting subroutines sequentially.

Abstract: A method, apparatus and system for selecting a highest prioritized task for executing a resource from one of a first and second expired scheduling arrays, where the first and second expired scheduling arrays may prioritize tasks for using the resource, and where tasks in the first expired scheduling array may be prioritized according to a proportionality mechanism and tasks in the second expired scheduling array may be prioritized according to an importance factor determined, for example, based on user input, and executing the task. Other embodiments are described and claimed.