Abstract: Some embodiments of the invention provide a method that pre-computes routes for groups of related net configurations. These routes are used by a router that uses a set of partitioning lines to partition a region of a design layout into a plurality of sub-regions. The method identifies groups of related sub-region configurations. For each group, the method stores a base set of routes. For each configuration in each group, the method also stores an indicia that specifies how to obtain a related set of routes for the particular configuration from the base set of routes stored for the configuration's group.

Abstract: A method of routing an interconnect metal layer of an integrated circuit, wherein single-width nets are replicated and routed in parallel to reduce the total resistance on the net; wide wires are decomposed into a several single-width wires routed in parallel to improve uniformity of metal interconnect routing and therefore manufacturability of metal interconnect layers. The decomposition step is performed during a preliminary wire route after initial physical placement. Access to pin shapes is ensured through a branching and a recombination of the parallel single-width wires. Separate wire segments are rejoined at the source and sink of the net. The parallel wire segments do not change the logic behavior of the circuit.

Abstract: One embodiment of the present invention provides a system that formally proves the functional equivalence of pipelined designs. First, the system receives a specification for a first pipelined design, which includes a first memory system, and a specification for a second pipelined design, which includes a second memory system. Next, the system determines a correspondence between operations on the first memory system and corresponding operations on the second memory system. This correspondence enables memory operations to be represented in a combinational form based on design inputs, thereby allowing both memory systems to be logically abstracted out of their respective designs. After the memory systems have been abstracted out, the system compares the combinational outputs of the first pipelined design and the combinational outputs of the second pipelined design to verify that the designs are functionally equivalent.

Abstract: The disclosure presents a formulation to support simulatable subset (also known as ‘simple-subset’) of a property specification language. This method is applicable for model checking and simulation. In this formulation, the ‘simple-subset’ is transformed to a set of basic formulas. Verification engines are required to support the basic formula only. The basic formula is a form of automata in the property specification language. This is called SERE implication. The efficiency of verification is dependent on size of automata. Miscellaneous opportunistic rules are applied to optimize SERE implication formulas.

Abstract: Systems and methods are disclosed herein for determining the placement of a standard cell, representing a semiconductor component in a design stage, on an integrated circuit die. One embodiment of a method, among others, comprises analyzing regions of a semiconductor die with respect to the susceptibility of the region to be exposed to radiation. This method further comprises placing the standard cell in one of the analyzed regions of the semiconductor die, the standard cell being placed based on the sensitivity of the standard cell to radiation. The method may also comprise running an algorithm, e.g. using a component placement engine, for determining the placement of semiconductor components on an integrated circuit die.

Abstract: A multi-layered substrate has a voltage reference signal circuit layout therein. A major change in the design of the multi-layered substrate is the moving of a reference signal trace from a signal layer to a non-signaling layer. Once the reference signal trace is moved, the signal traces within the signal layer can have a larger layout area. Similarly, the reference signal trace within the non-signaling layer can have greater layout flexibility in addition to electromagnetic shielding from other signal traces. Moreover, the reference signal trace having a greater width may be used to reduce parasitic resistance within the reference signal circuit.

Abstract: A method for generating a simulated aerial image of a mask projected by an optical system includes determining a coherence characteristic of the optical system. A coherent decomposition of the optical system is computed based on the coherence characteristic. The decomposition includes a series of expansion functions having angular and radial components that are expressed as explicit functions. The expansion functions are convolved with a transmission function of the mask in order to generate the simulated aerial image.

Abstract: Although there are a number of techniques available to reduce leakage current, there is still considerable room for improvement. Accordingly, the present inventors devised, among other things, an exemplary method which entails defining first and second leakage-reduction vectors for respective first and second portions of an integrated circuit, such as a microprocessor. The leakage-reduction vectors, in some embodiments, set the first and second portion to minimum leakage states and thus promise to reduce leakage power and extend battery life in devices that incorporate this technology.

Abstract: A method of performing analytical placement of components for a circuit design can include the steps of modifying an analytical formulation for placement of the circuit design a priori (when the circuit design or programmable device fabric includes inhomogeneous components) providing a modified analytical formulation and applying the modified analytical formulation during placement of the circuit design. The step of modifying can optionally include introducing terms into the analytical formulation that push components away from locations in which they cannot reside (such as a large hole in the programmable device fabric due to a large, fixed component such as a CPU core) or alternatively or optionally the step of introducing (115) terms into the analytical formulation that pull components that can only reside at a relatively small number of locations towards those locations.

Abstract: Systems and methods for verifying integrated circuit designs: (a) receive input corresponding to physical layouts of cells of the design and available master cells. The systems and methods then determine if the design cells are intended to correspond to one of the master cells, and if so, the systems and methods then determine if the layouts of the cells and the corresponding master cells match one another, e.g., by a layout vs. layout comparison of the design cell with the master cell to determine if the coordinates of the polygon(s) in the design cell match corresponding coordinates of the polygon(s) in the master cell. An “XOR” comparison may be used to determine if the design cell features match the corresponding master cell features. Computer-readable media may be adapted to include computer-executable instructions for performing such methods and operating such systems.

Abstract: Various embodiments of the invention determine whether paths of a first graph satisfy a constraint based on a plurality of sub-graphs of the first graph. Each graph is a directed acyclic graph of nodes and arcs. The first graph and a second graph are generated in a memory arrangement, with the first graph and the second graph having a shared sub-graph, and each path of the paths of the first graph is constrained by the constraint unless the path is a path of the second graph. The plurality of sub-graphs of the first graph are generated in the memory arrangement with each of the plurality of sub-graphs not including any path of the second graph and each of the paths of the first graph that is not a path of the second graph being included in at least one of the plurality of sub-graphs.

Abstract: An aspect of the present invention includes a method for reshaping sub-objects in at least one object in pattern design data to be presented to a mask writer or a direct writer for producing a pattern onto a workpiece, where said object comprises a plurality of slivers in a first direction, comprising the actions of: a) generating a list of slivers, repeating the actions of: b) comparing a dynamic object in an object list with the slivers in said list of slivers to look for adjacent slivers, c) removing adjacent slivers from said list of slivers to said object list, d) merging adjacent slivers with said dynamic object, e) terminating the repetition when no slivers in said list of slivers are adjacent to said dynamic object in said object list. Other aspects of the present invention are reflected in the detailed description, figures and claims.

Abstract: Methods and apparatuses for designing an integrated circuit. In one example of a method, a hardware description language (HDL) code is compiled to produce a technology independent RTL (register transfer level) netlist. A portion of an area of the IC is allocated to a specific portion of the technology independent RTL netlist. In a typical implementation of this method, the allocation restricts circuitry created from the specific portion to the portion of the IC.

Abstract: An apparatus of evaluating a layer matching deviation based on CAD information of the invention, is provided with means for storing CAD data and a function of displaying to overlap a scanning microscope image of a pattern of a semiconductor device formed on a wafer and a design CAD image read from the storing means and a function of evaluating acceptability of formation of the pattern by displaying to overlap a pattern image of the semiconductor device formed on the wafer and the design CAD image of the pattern, in addition thereto, a function capable of evaluating acceptability of formation of the pattern also with regard to a shape and positional relationship with a pattern formed at a later step by displaying to overlap a design CAD image of the pattern formed at the later step.

Abstract: A method of generating a metrology recipe includes identifying regions of interest within a device layout. A coordinate list, which corresponds to the identified regions of interest, can be provided and used to create a clipped layout, which can be represented by a clipped layout data file. The clipped layout data file and corresponding coordinate list can be provided and converted into a metrology recipe for guiding one or more metrology instruments in testing a processed wafer and/or reticle. The experimental metrology results received in response to the metrology request can be linked to corresponding design data and simulation data and stored in a queriable database system.

Abstract: The present invention relates to a method of interconnection routing for preventing crosstalk. The method comprises the following steps. Providing an aggressor connection path as a first net. Providing a victim connection path according to the requirements of a second net. Determining a voltage ramp time of the aggressor connection path, a victim total length of the victim connection path, a coupled wire length between the aggressor connection path and the victim connection path, and an equivalent load corresponding to the victim connection path. Evaluating a noise metric according to the voltage ramp time, the victim total length, the coupled wire length and the equivalent load. Modifying the victim connection path to shorten the coupled wire length if the noise metric is greater than a pre-determined value. Finally designating the victim connection path as the second net if the noise metric is less than the pre-determined value.

Abstract: A photomask designing method used in a lithography process, the lithography process comprises illuminating light on a photomask and converging the light which has passed through the photomask on a photosensitive substrate via a projection optical system, the photomask designing method comprises acquiring a transmittance characteristic of the projection optical system, the characteristic varing depending on a difference in optical paths of light in the projection optical system, the light passing through the projection optical system, and acquiring mask bias of the photomask by use of the transmittance characteristic of the projection optical system.

Abstract: In an automated integrated circuit design, if the performances of a layout of circuit devices are not within predetermined tolerances of performance specifications, at least one of the circuit devices is resized or repositioned and an updated value of a device parameter for each resized or repositioned circuit device is determined. A difference between the initial and updated value of each device parameter is then determined and each difference is combined with a ratio formed from changes in the value of one of the device parameters and changes in the value of one of the performances affected by the device parameter. The result of this combination is then combined with the initial value of the performance to determine an updated value therefor.

Abstract: A new method to design and verify a multi-power integrated circuit device is achieved. A multi-power gate-level netlist is provided. This multi-power gate-level netlist includes multi-power net information. This multi-power gate-level netlist is translated to thereby create a non-multi-power gate-level netlist. This translating comprises removing the multi-power net information. Circuit cells are then placed and routed to create a physical view of the multi-power integrated circuit device. This placing and routing step uses the non-multi-power gate-level netlist. Text labels for the multi-power net information are attached to the physical view. The physical view and the multi-power gate-level netlist are compared to verify the correctness of the physical view and to complete the design and verification of the multi-power integrated circuit device.

Abstract: In a configuration database, at least one latch data structure is created that corresponds to a hardware latch in a hardware system to be configured. The at least one latch data structure includes a method field indicating which of a plurality of different access methods can be used to access the hardware latch. In addition, the latch data structure includes at least one Dial data structure defining an instance of a Dial entity controlling which of a plurality of different possible latch values is placed in the hardware latch in response to each of a plurality of Dial settings. The configuration database further includes an association between the instance of the Dial entity and the hardware latch. The configuration database can then be referenced to set the hardware latch utilizing an access method indicated by the at least one latch data structure.