Abstract: Approaches for determining a static timing analysis of a logic design are disclosed. Physical delay arcs of a plurality of physical elements of an integrated circuit specify respective propagation delays from inputs of the physical elements to outputs of the physical elements. Logic components of the logic design are mapped to selected ones of the physical components of the physical elements. For each of the logic components, the logic delay arcs are determined from the physical delay arcs. Each logic delay arc for each logic component specifies a propagation delay from an input of the logic component to an output of the logic component. A static timing analysis of the logic components is performed using the logic delay arc, and data from the timing analysis is output.

Abstract: A method of creating a design-specific I/O model document can include reading a plurality of I/O pin models corresponding to available I/O pin profiles on a target device (355) and identifying I/O pins of the target device that are used by a circuit design (325). An I/O pin profile for each I/O pin of the target device that is used by the circuit design can be determined (345). An I/O pin model can be selected from the plurality of I/O pin models for each I/O pin of the target device that is used by the circuit design according to the I/O pin profiles (355). The design-specific I/O model document for the circuit design can be generated by including each selected I/O pin model within the design-specific I/O model document (365). The design-specific I/O model document can be output (380).

Abstract: The invention relates to a design method and tool for designing electronic circuits on a printed circuit board (10), wherein at least one self-contained, pre-composed domain is used, wherein the domain (110, 120, 130, 140, 150, 150, 160) is a module chosen from a pre-composed architecture library, comprising self-contained pre-designed electronic modules represented by logical architecture and corresponding physical architecture.

Abstract: Systems and methods for creating inspection recipes are provided. One computer-implemented method for creating an inspection recipe includes acquiring a first design and one or more characteristics of output of an inspection system for a wafer on which the first design is printed using a manufacturing process. The method also includes creating an inspection recipe for a second design using the first design and the one or more characteristics of the output acquired for the wafer on which the first design is printed. The first and second designs are different. The inspection recipe will be used for inspecting wafers after the second design is printed on the wafers using the manufacturing process.

Abstract: A method of verifying a design of logic circuit of a semiconductor device having a first circuit block to which the power continuously applied and a second circuit block receiving the power which turns on/off in response to the state of operation modes includes replacing a first basic logic cell including a storage element to a first verification logic cell in the blocks, replacing a second basic logic cell having no storage cell to a second verification logic cell in the blocks, and performing a logical simulation of the device.

Abstract: Computer aided design tools are provided that assist circuit designers in optimizing circuit performance. A circuit designer who is designing an integrated circuit may supply circuit design data and constraint data. Computer aided design tools may process the data to produce output data. The output data may include information on an implementation of the circuit design in a given type of integrated circuit device and may include report data on how the implementation of the circuit design is expected to perform. An optimization assistance tool analyzes the design and constraint data and the report data to identify potential problem areas. Recommendations may be provided to the circuit designer on how to address potential problems. Selectable options are displayed for the circuit designer. By selecting an appropriate option, the circuit designer can automatically launch a tool to make recommended settings adjustments.

Abstract: One embodiment of the present invention provides a system that formally proves the functional equivalence of pipelined designs. First, the system receives a specification for a first pipelined design, which includes a first memory system, and a specification for a second pipelined design, which includes a second memory system. Next, the system determines a correspondence between operations on the first memory system and corresponding operations on the second memory system. This correspondence enables memory operations to be represented in a combinational form based on design inputs, thereby allowing both memory systems to be logically abstracted out of their respective designs. After the memory systems have been abstracted out, the system compares the combinational outputs of the first pipelined design and the combinational outputs of the second pipelined design to verify that the designs are functionally equivalent.

Abstract: A layout-data generation equipment includes a logic circuit designing section which designs a logic circuit based on information of the specifications of a semiconductor integrated circuit, a layout-data generation section which creates layout-data based on the logic circuit, a resistance information extraction section which extracts resistance information of a wire from the layout-data, a circuit simulation execution section which executes a circuit simulation, an identification section of current direction which identifies a direction of a current in the wire based on the resistance information of a wire and an execution result of the circuit simulation, a verification section which verifies whether layout-data of the wire breaks a design rule, the design rule being extracted from the information of the specifications of a semiconductor integrated circuit and the verification section generates this verification result, and a data output section which outputs the layout-data.

Abstract: A yield of a semiconductor layout may be improved by selecting a pattern that does not satisfy at least one of multiple rules within the layout, adding a margin to a predetermined value of the at least one of the rules associated with selected pattern, based on a ground rule and a recommended rule of each of the rules, calculating an overall fail rate of at least one of the rules that varies according to the addition of the margin, and determining an adjusted margin to be added based on the calculated overall fail rate.

Abstract: A logical-group creating unit creates a logical group from a cell included in a selected range of a logical drawing that is specified in a logical page. A logical-group extracting unit extracts a same/similar logical group by determining whether logical drawings of created logical groups are same or similar to each other. A pattern creating unit creates an implementation pattern of a logical group included in extracted same/similar logical group.

Abstract: A method and apparatus for determining how well a photolithographic model simulates a photolithographic printing process. A test pattern of features is printed on a wafer and the shape of the printed features is compared with the shape of simulated features produced by the model. A cost function is calculated from the comparison that quantifies how well the model simulates the photolithographic printing process.

Abstract: Nets of a logic design are efficiently routed in a programmable logic device, which includes multiple types of programmable interconnects. Patterns are read from a library in a storage device. Each pattern includes an ordered set of the types of the programmable interconnects. A path is determined from the source to the destination for each net of the logic design. The path is through a sequence of the programmable interconnects having types that correspond to each type in the ordered set of a selected pattern. A description is output of the path for each of the nets.

Abstract: Systems for using relative positioning of items or components in a structure with dynamic ranges, such as an elastic I/O bus design for an Integrated Circuit (IC), are disclosed. Embodiments may include a user-defined type module having user-defined types representing relative instance positions within a structure. Embodiments may also include a translation helper module to receive information associated with a hierarchy and to return location information associated with the hierarchy and a translation module to translate between a specific location and a relative position of the instance based on one or more user-defined types and location information returned from the translation helper module to generate a list of translated results. Further embodiments of the translation module may include a relative position determiner to translate specific locations to relative positions and may also include a specific location determiner to translate relative positions to specific locations.

Abstract: A method, system and apparatus for constructing a comprehensive test plan using a case analysis graph is provided. Embodiments of the present invention further provide for automatically generating test cases from a case analysis graph and for measuring functional coverage of the test cases. Additional embodiments of the present invention provide for visualizing both the comprehensive test plan and functional coverage data.

Abstract: A design structure for an integrated circuit which includes: a first flip-flop which is capable of flushing and which operates by using a first clock signal CLK 1; a second flip-flop DFF 2 which operates by using a second clock signal CLK 2, and which is connected to the first flip flop; and a third flip-flop DFF 3 which operates by using the second clock signal CLK 2, and which is connected to the first flip-flop. A test on a path between the first and second flip-flops is carried out in a manner that test data is released and captured on receipt of the clock signal CLK 2 between the second flip-flop DFF 2 and the third flip-flop DFF 3 via the first flip-flop DFF 1, and that the test data is flushed by the first flip-flop DFF 1.

Abstract: Disclosed are methods and mechanisms for implementing tessellation-based processing of an integrated circuit design. Tessellation based routing of objects on an integrated circuit layout can be performed by identifying a spacing rule for tessellating at least a portion of the integrated circuit layout, forming one or more plane figures in the tessellation having one or more edges compliant with the spacing rule, the edges of the one or more plane figures forming a contour derived from a shape of a blockage object, and identifying a routing path along at least part of the one or more edges. Packing and pushing of objects may be performed using this approach.

Abstract: A method and apparatus for determining electro-migration (EM) in integrated circuit designs is disclosed. In one embodiment, a method includes pre-characterizing an output current waveform for a logic cell of the circuit at selected load and input slew points, estimating an effective load and operating slews at a chip level of the circuit and directly generating an equivalent current source waveform at output, evaluating current densities through a metal segment of the circuit using a fast solver, parametrically representing process variations and a netlist to parametrically model the interconnect variations of the circuit, and determining current densities for selected yield numbers using a parametrically generated current source on an interconnect network, wherein calculated results statistically predict a point of current density less than 9?? a through any metal segment in the parametrically modeled circuit.

Abstract: An apparatus and method for modifying a mask data set includes calculating a derivative of a figure-of-merit, indicative of a data set defined by a plurality of polygon edges and then segmenting polygon edges in response to said step of calculating.

Abstract: An embodiment provides systems and techniques for determining a process model. During operation, the system may receive a first optical model which models a first optical system of a photolithography process. Next, the system may use the first optical model to determine a second optical model that models a second latent image that is formed by the first optical system at a second distance. The system may also use the first optical model to determine a third optical model that models a third latent image that is formed by the first optical system at a third distance. Next, the system may receive process data which is obtained by subjecting a test layout to the photolithography process. The system may then determine a process model using the first optical model, the second optical model, the third optical model, the test layout, and the process data.

Abstract: A system and method to optimize a circuit layout, and more particularly, to a system and method of post layout data preparation to optimize a circuit layout and reduce random and systematic wire and via opens and shorts. The method includes stripping existing vias in a design layout and determining design parameters of the design layout including wiring placement and dimensions. The method further includes optimizing via layout by placing vias away from edges of the wiring and adjacent vias. The invention is also directed to a design structure on which a circuit resides.