Abstract: A validation/correction method is provided for design data or mask data by which a pattern which becomes critical in a process is extracted in advance so that the pattern can be corrected. Consequently, the process spec is achieved in a short period of time after OPC or process proximity effect correction (PPC).

Abstract: A wiring layout apparatus includes a layout design unit configured to design a wiring layout for a semiconductor integrated circuit; a critical wiring detection unit configured to analyze a delay of signal propagation in the wiring layout so as to detect wiring strip conductors that configure a signal path whose timing is critical; a rewiring unit configured to rearrange the wiring strip conductors so as to improve the uniformity of a wiring pattern of an area in the vicinity of the critical wiring strip conductor, with regard to the wiring layout; and a strip-conductor-size variation determination unit configured to evaluate the uniformity of the pattern of the rearranged wiring layout so as to determine whether or not variation in the size of the critical wiring strip conductor falls within a tolerance range.

Abstract: A method of full semiconductor chip timing closure includes the steps of determining a system level place and route. Next, a static timing analysis for each of a number of subsystems is performed. Finally, a full chip static timing analysis is performed.

Abstract: Method and system for chip optimization using model based verification (MBV) tool provide more accurate verification in determining hotspots and their characteristics. The MBV and the layout optimizer are implemented within a feedback loop. This type of verification allows for the MBV tool to provide hints, constraints and hotspot information to the layout optimizer. In addition, the model-based simulation results can be used to automatically fix the circuit designs and allow for specialized optimization flow for standard cell libraries.

Abstract: A method, system and computer program product for generating and verifying the correctness of isolation logic modules in design of integrated circuits (ICs). The method disclosed generates an isolation logic module for each power domain specified by a user, instantiates the generated module in a pre-determined wakeup domain, and then simulates shutdown conditions to ensure the correctness of the generated isolation logic module. The isolation logic is generated based on user-defined voltage constraints.

Abstract: Disclosed are methods and mechanisms for implementing tessellation-based processing of an integrated circuit design. Tessellation based routing of objects on an integrated circuit layout can be performed by identifying a spacing rule for tessellating at least a portion of the integrated circuit layout, forming one or more plane figures in the tessellation having one or more edges compliant with the spacing rule, the edges of the one or more plane figures forming a contour derived from a shape of a blockage object, and identifying a routing path along at least part of the one or more edges. Packing and pushing of objects may be performed using this approach.

Abstract: Statistical timing analysis techniques can be used to lead to the construction of robust circuits in a consistent manner through the entire design flow of synthesis, placement and routing. An exemplary technique can include receiving library data for a design including timing models. By comparing implementations of this data, a robust circuit can be defined based on a set of criteria, which can include worst negative slack, endpoint slack distribution, timing constraint violations, and total negative slack. At this point, statistical timing analysis can be used to drive logic changes that generate improved robustness in the design. The statistical timing analysis can use a static timing delay associated with the arc in statistical timing analysis as a mean and a specified percentage of the mean as the standard deviation.

Abstract: Within an Electronic Design Automation (EDA) tool, a method of macro inference can include translating a hardware description language (HDL) template into a macro template and translating a circuit design into a format corresponding to the macro template. The method further can include matching a portion of the translated circuit design with the macro template and replacing the portion of the circuit design matching the macro template with a macro associated with the macro template. The resulting updated circuit design is then output, e.g., to a user, a computer file, or another EDA tool.

Abstract: According to an aspect of the invention, there is provided a mask data correction method used when forming a photomask used in a photolithography process, comprising correcting mask data on the basis of simulation performed by using information including nonuniformity of an illumination luminance distribution in an exposure apparatus which uses the photomask formed by using the mask data obtained by the correction result.

Abstract: A system that places an integrated circuit (IC) device within an IC chip layout is presented. During operation, the system receives the IC device to be placed within the IC chip layout, wherein the IC chip layout includes one or more continuous rows of diffusion. Next, the system places the IC device within a continuous row of diffusion. The system then determines whether the IC device is to be electrically isolated from other IC devices. If so, the system inserts one or more isolation devices within the continuous row of diffusion so that the IC device can be electrically isolated from other IC devices. The system then biases the one or more isolation device so that the IC device is electrically isolated from other IC devices within the continuous row of diffusion.

Abstract: Computer readable media hosting a layout description of electric circuitry that includes a description of prospective fill units and includes characteristic data noting at least one characteristic of each fill unit. In one preferred embodiment, each prospective fill unit includes just a single prospective fill element. Also, in a preferred embodiment, said characteristic data includes effect on electrical characteristics of nearby electrical circuitry. These electrical characteristics may further include timing characteristics and capacitance characteristics. The effect on the thickness of nearby connective elements also may be noted.

Abstract: A method of performing node-based static timing analysis on a digital network and a program storage device for implementing the method, wherein the method comprises partitioning timing delays in the digital network into portions attributable to a factor of interest and portions attributable to other factors; multiplying the timing delays by different weights based on the factor of interest to produce weighted timing delays; and using the multiplied timing delays to determine a relative impact of the factor of interest on the various paths in the digital network. The method further comprises setting arrival times of timing signals at digital network path start points to zero and identifying digital network paths whose timing delays are dominated by a particular factor of interest. The different weights comprise any of a positive weight, a negative weight, and a zero weight.

Abstract: A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the victim net is calculated. The probabilistic noise is checked against the voltage threshold, and the victim net design is passed when the probabilistic noise does not exceed the voltage threshold. When the probabilistic noise does exceed the threshold, then an effective noise at a desired mean time to failure is computed, and the effective noise is checked against the voltage threshold. The victim net design is passed when the effective noise does not exceed the voltage threshold, and failed when the effective noise does exceed the threshold.

Abstract: A system and method for performing device-specific testing and acquiring parametric data on integrated circuits, for example ASICs, such that each chip is tested individually without excessive test time requirements, additional silicon, or special test equipment. The testing system includes a device test structure integrated into unused backfill space in an IC design which tests a set of dummy devices that are identical to a selected set of devices contained in the IC. The device test structures are selected from a library according to customer requirements and design requirements. The selected test structures are further prioritized and assigned to design elements within the design in order of priority. Placement algorithms use design, layout, and manufacturing requirements to place the selected test structures into the final layout of the design to be manufactured.

Abstract: The present invention provides a circuit analysis device including: storage unit having stored therein: connection information about multiple components; delay information including information about the delay time of a discrete component and a chain delay time which is a delay time in the case in which a chain delay effect is generated by a connection with another component about each kind of the multiple components; and chain effect propagating component information including information about kinds of chain effect propagating components which are components for transmitting the chain delay effect, and data processing unit for: referring to the information stored in the storage unit; performing a total delay time calculation process of sequentially adding the delay times of the components along a signal path in the circuit; and if the chain effect propagating component is halfway through the signal path in the total delay time calculation process, examining a connection relation between components that prec

Abstract: A method and system to efficiently create electromagnetic coupled basis functions for an electronic circuit that is defined by geometry data and topology data. The geometry data for the circuit are read, and a three-dimensional mesh of polygons for the circuit is created. External port geometry and internal port geometry (internal ports occur where vias are attached to conductive layers) are determined from the geometry data. Circuit electromagnetic basis functions are then created as are loop-tree formations that are coupled to the basis functions. The loops include local loops, via loops, and hole loops. The three-dimensional mesh is efficiently created by extruding a two-dimensional mesh for each layer and via in the circuit.

Abstract: A semiconductor mask correcting device is provided with an image acquiring unit acquiring a mask image, an extraction unit extracting only a main pattern from the mask data, an inspection unit inspecting a defective portion by comparing the extracted main pattern with a main pattern which is obtained from the mask image after a drawing by matching to each other, and a correction unit correcting the defective portion specified by the inspection unit, wherein the extraction unit includes a recognition section recognizing the main pattern and the assist pattern as a figure, a specification section specifying the assist pattern from figures which is recognized on the basis of a predetermined condition, and a main pattern extracting section extracting as the main pattern a figure other than the assist pattern.

Abstract: A method for generating a simulated aerial image of a mask projected by an optical system includes determining a coherence characteristic of the optical system. A coherent decomposition of the optical system is computed based on the coherence characteristic. The decomposition includes a series of expansion functions having angular and radial components that are expressed as explicit functions. The expansion functions are convolved with a transmission function of the mask in order to generate the simulated aerial image.

Abstract: Methods and apparatuses for designing an integrated circuit. In one example of a method, a hardware description language (HDL) code is compiled to produce a technology independent RTL (register transfer level) netlist. A portion of an area of the IC is allocated to a specific portion of the technology independent RTL netlist. In a typical implementation of this method, the allocation restricts circuitry created from the specific portion to the portion of the IC.

Abstract: A method for performing equivalence checking on logic circuit designs is disclosed. Within a composite netlist of an original version and a modified version of a logic circuit design, all level-sensitive sequential elements sensitized by a clock=0 are converted into buffers, and all level-sensitive sequential elements sensitized by a clock=1 are converted into level-sensitive registers. A subset of edge-sensitive sequential elements are selectively transformed into level-sensitive sequential elements by removing edge detection logic from the subset of the edge-sensitive sequential elements. A clock to the resulting sequential elements is then set to a logical “1” to verify the sequential equivalence of the transformed netlist.