Patents Examined by Bret Chen
  • Patent number: 9499904
    Abstract: The disclosed method of manufacturing carbon nanotubes includes the steps of growing CNTs on a substrate 12 and cleaning the inside of a growth furnace 13 by supplying a cleaning gas that contains water into the growth furnace 13. In the cleaning step, the cleaning is performed such that 0.7?(2[CO2]+[CO])/[H2]?1.3 is satisfied, where [H2], [CO2], and [CO] denote the concentrations of hydrogen, carbon dioxide, and carbon monoxide, respectively, in a gas within the growth furnace 13.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: November 22, 2016
    Assignee: ZEON CORPORATION
    Inventor: Akiyoshi Shibuya
  • Patent number: 9493873
    Abstract: A method is disclosed for coating, by means of a chemical vapor deposition (CVD) technique, a part with a coating (PAO) for protecting against oxidation. The method enables the preparation of a refractory coating for protecting against oxidation, having a three-dimensional microstructure, which ensures the protection against oxidation at a high temperature, generally at a temperature above 1200° C., for materials that are sensitive to oxidation, such as composite materials, and in particular carbon/carbon composite materials.
    Type: Grant
    Filed: November 23, 2012
    Date of Patent: November 15, 2016
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Alexandre Allemand, Olivier Szwedek, Jean-Francois Epherre, Yann Le Petitcorps
  • Patent number: 9487860
    Abstract: Vapor deposition methods of cobalt-containing films by using cobalt carbonyl nitrosyl are disclosed.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: November 8, 2016
    Assignee: L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude
    Inventors: Satoko Gatineau, Jean-Marc Girard, Nicolas Blasco, Mikiko Kimura
  • Patent number: 9478411
    Abstract: Methods of depositing and tuning deposition of sub-stoichiometric titanium oxide are provided. Methods involve depositing highly pure and conformal titanium on a substrate in a chamber by (i) exposing the substrate to titanium tetraiodide, (ii) purging the chamber, (iii) exposing the substrate to a plasma, (iv) purging the chamber, (v) repeating (i) through (iv), and treating the deposited titanium on the substrate to form sub-stoichiometric titanium oxide. Titanium oxide may also be deposited prior to depositing titanium on the substrate. Treatments include substrate exposure to an oxygen source and/or annealing the substrate.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: October 25, 2016
    Assignee: Lam Research Corporation
    Inventors: Shruti Vivek Thombare, Ishtak Karim, Sanjay Gopinath, Reza Arghavani, Michal Danek
  • Patent number: 9472391
    Abstract: A semiconductor device manufacturing method includes forming a thin film containing silicon, oxygen, carbon and a specified Group III or Group V element on a substrate by performing a cycle a predetermined number of times. The cycle includes: supplying a precursor gas containing silicon, carbon and a halogen element and having an Si—C bonding and a first catalytic gas to the substrate; supplying an oxidizing gas and a second catalytic gas to the substrate; and supplying a modifying gas containing the specified Group III or Group V element to the substrate.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: October 18, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Satoshi Shimamoto, Yoshiro Hirose, Atsushi Sano, Tsukasa Kamakura, Takaaki Noda
  • Patent number: 9466499
    Abstract: A substrate having a plurality of site-isolated regions defined thereon is provided. A first electrochromic material, or a first electrochromic device stack, is formed above a first of the plurality of site-isolated regions using a first set of processing conditions. A second electrochromic material, or a second electrochromic device stack, is formed above a second of the plurality of site-isolated regions using a second set of processing conditions. The second set of processing conditions is different than the first set of processing conditions.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: October 11, 2016
    Assignee: Intermolecular, Inc.
    Inventors: Jeroen Van Duren, Minh Huu Le, Minh Anh Nguyen, Sandeep Nijhawan
  • Patent number: 9463998
    Abstract: A method for manufacturing a film-coated glass film includes heating a cylindrical body made of glass or ceramic with a heater provided in an interior of the cylindrical body, heating a glass film by feeding the glass film over the heated cylindrical body, and forming a film made of an oxide, a nitride, or a metal on the glass film while the film is on and being heated by the cylindrical body.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: October 11, 2016
    Assignee: NIPPON ELECTRIC GLASS CO., LTD.
    Inventor: Takayoshi Saitoh
  • Patent number: 9457425
    Abstract: A method of manufacturing a glazing having a frequency selective surface comprising the steps of: a) depositing a coating on a substrate, said coating being non-transmitting to radio frequency (RF) radiation; b) providing a laser beam and c) removing a portion of the coating by laser ablation to form one or more curves and/or lines having a spacing selected to provide transparency of the coating to RF radiation of a desired wavelength; characterized by d) directing the laser beam and/or moving the substrate such that the relative motion of the intersection of the laser beam and the coating, with respect to the substrate, comprises motion in a first dimension, wherein said motion is simultaneously superimposed with a reciprocating motion in a second dimension; e) translating said intersection in the second dimension; and f) repeating at least step d) out of steps d) to f).
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: October 4, 2016
    Assignee: PILKINGTON GROUP LIMITED
    Inventor: Peter Paulus
  • Patent number: 9447926
    Abstract: A plasma process method of processing an object to be processed by a plasma process while enabling cooling of an inside of a plasma apparatus by taking in and exhausting a gas to evacuate an atmosphere of the inside includes measuring a temperature of the atmosphere of the inside of the plasma process apparatus while the plasma is not generated; and stopping taking the gas into the inside of the plasma process apparatus during the plasma process in a case where the measured temperature is lower than a first preset threshold temperature when the atmosphere is evacuated at a preset volumetric flow rate.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: September 20, 2016
    Assignee: Tokyo Electron Limited
    Inventors: Naomi Onodera, Kiyohiko Gokon, Jun Sato
  • Patent number: 9449809
    Abstract: The present disclosure describes methods of an interface adhesion improvement methods used on a transparent substrate for OLED or thin film transistor applications. In one embodiment, a method of forming a buffer layer on a surface of a substrate includes providing a substrate having an planarization material disposed thereon in a processing chamber, supplying a buffer layer gas mixture including a silicon containing gas into the processing chamber, controlling a substrate temperature less than about 100 degrees Celsius, forming a buffer layer on the planarization material, supplying an encapsulating barrier layer deposition gas mixture including a silicon containing gas and a nitrogen containing gas into the processing chamber, and forming an encapsulating barrier layer on the buffer layer.
    Type: Grant
    Filed: July 20, 2013
    Date of Patent: September 20, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Young Jin Choi, Jrjyan Jerry Chen, Beom Soo Park, Soo Young Choi
  • Patent number: 9447498
    Abstract: A method for performing uniform processing in multiple reaction chambers includes (a) conducting a cycle constituted by steps in each reaction chamber according to the order of the reaction chambers at which the steps are conducted; and then (b) conducting the steps in each reaction chamber after changing the immediately prior order of the reaction chambers at which the steps are conducted; and then (c) repeating process (b) until a target treatment is complete at the multiple reaction chambers. The target treatment conducted on a substrate in each reaction chamber is the same.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: September 20, 2016
    Assignee: ASM IP Holding B.V.
    Inventor: Eiichiro Shiba
  • Patent number: 9441302
    Abstract: Provided is a method for manufacturing a Zn—Mg alloy-coated steel sheet having high blackening resistance and coating adhesion. In one implementation, the method may include forming a Zn—Mg coating layer on a base steel sheet and performing a combustion chemical vapor deposition (CCVD) process to form an oxide film. The oxide film may include a metal oxide and the metal oxide may include silicon oxide (SiO2) and magnesium oxide (MgO). The base steel sheet may be maintained within a temperature range of 330° C. to 450° C. during the performing of the CCVD process.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: September 13, 2016
    Assignee: POSCO
    Inventors: Dong-Yoeul Lee, Kyung-Hoon Nam, Yong-Hwa Jung, Seok-Jun Hong, Tae-Yeob Kim, Young-Jin Kwak, Mun-Jong Eom, Woo-Sung Jung
  • Patent number: 9441291
    Abstract: A method of depositing a continuous TiN film on a substrate is provided. In the method, a continuous TiO2 film is deposited on a substrate, and then a continuous TiN film is deposited on the continuous TiO2 film. The TiN film is thicker than the TiO2 film.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: September 13, 2016
    Assignee: Tokyo Electron Limited
    Inventors: Takeshi Kumagai, Muneyuki Otani
  • Patent number: 9437426
    Abstract: A method of manufacturing a semiconductor device including: a process of transferring a substrate into a processing chamber; a first gas supplying process of supplying a B atom-containing gas into the processing chamber; a first purging process of purging an inside of the processing chamber under an atmosphere of the B atom-containing gas supplied in the first gas supplying process; a second gas supplying process of supplying an Si atom-containing gas into the processing chamber to form a non-doped Si film on the substrate, after the first purging process; and a second purging process of purging the inside of the processing chamber under an atmosphere of the Si atom-containing gas.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: September 6, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Naoharu Nakaiso, Kazuhiro Yuasa, Yuki Kitahara
  • Patent number: 9437419
    Abstract: A trialkylsilane-based silicon precursor compound may be expressed by Si(Ri)X, i=1-3, where each of “R1”, “R2”, and “R3” is a hydrogen or an alkyl having 1-5 carbon(s), all of “R1”, “R2”, and “R3” are not hydrogen, “X” is one of hydrogen, a hydroxyl group, an amide group, an alkoxide group, a halide group, or Si(R*)3, and “R*” is a hydrogen or an alkyl group having 1˜5 carbon(s).
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: September 6, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Younsoo Kim, Sangyeol Kang, Hiroki Sato, Tsubasa Shiratori, Naoki Yamada, Chayoung Yoo, Younjoung Cho, Chin Moo Cho, Jaehyoung Choi
  • Patent number: 9428829
    Abstract: A method of forming a high-quality graphene layer including forming a board layer; forming a stress reduction layer on the board layer; forming a metal catalyst layer on the stress reduction layer, the metal catalyst layer functioning as a catalyst for forming the graphene layer; and growing a graphene layer on the metal catalyst layer. The stress reduction layer reduces the stress of the metal thin film, thus, improving crystallinity and surface roughness of the metal thin film, and thereby effectively forming a high-quality graphene layer.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: August 30, 2016
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Byung Jin Cho, Jeong Hun Mun
  • Patent number: 9427726
    Abstract: Methods of making supported polyamines, supported polyamines, and the like, are disclosed.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: August 30, 2016
    Inventors: Watcharop Chaikittisilp, Christopher W. Jones
  • Patent number: 9431240
    Abstract: A method of manufacturing a semiconductor is provided. The method includes forming a thin film including a predetermined element and a borazine ring skeleton is formed on a substrate by performing a cycle a predetermined number of times. The cycle includes supplying a source gas including the predetermined element and a halogen group to the substrate and supplying a reaction gas including a borazine compound to the substrate under a condition where the borazine ring skeleton in the borazine compound is maintained.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: August 30, 2016
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yoshiro Hirose, Atsushi Sano, Katsuyoshi Harada, Satoshi Shimamoto
  • Patent number: 9422452
    Abstract: A polymerized film forming method for forming a polymerized film on a target surface of a workpiece using a first raw material gas which contains a first monomer and a second raw material gas which contains a second monomer differing from the first monomer includes: supplying the first raw material gas wherein difunctional non-aromatic amine having a hydrolyzable group is used for the first monomer; and supplying the second raw material gas wherein difunctional acid anhydride is used for the second monomer.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: August 23, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tatsuya Yamaguchi, Yoshinori Morisada
  • Patent number: 9422624
    Abstract: The present disclosure provides a heat treatment method, in which a substrate supporter supporting a plurality of substrates in the configuration of a shelf thereon is loaded in a vertical reaction tube surrounded by a heating mechanism and a heat treatment is performed. The method includes discharging a processing gas from a gas nozzle provided in the reaction tube to extend in a vertical direction of the substrate supporter, and supplying a temperature adjusting fluid into a flow path forming member provided to surround the gas nozzle in the reaction tube and adjusting a temperature of the processing gas in the gas nozzle.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: August 23, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Shigeru Nakajima, Hiromi Shima, Yusuke Tachino