Patents Examined by Brian E. Hearn
  • Patent number: 5599725
    Abstract: The present invention is directed to a unique method for fabricating a silicon based MOS transistor having an inverse-T refractory metal gate structure. The gate fabricated according to this invention comprises a main CVD tungsten portion and a lower sputtered tungsten portion outwardly extending from the bottom of the CVD portion such that a cross section of the gate appears as an inverted "T". A Cl.sub.2 /O.sub.2 plasma etch is used to etch the CVD tungsten layer and a chemical etch is used to etch the sputtered tungsten layer to form the gate electrode. It has been discovered that sputtered tungsten is more resistant to Cl.sub.2 /O.sub.2 reactive ion etch than is CVD tungsten. The sputtered tungsten layer acts as a shield to protect the underlying gate oxide layer from ion damage throughout the fabrication process.
    Type: Grant
    Filed: November 22, 1994
    Date of Patent: February 4, 1997
    Assignee: International Business Machines Corporation
    Inventors: Fernand Dorleans, Liang-Choo Hsia, Louis L. C. Hsu, Gerald R. Larsen, Geraldine C. Schwartz
  • Patent number: 5545578
    Abstract: A method for manufacturing a semiconductor device, e.g.
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: August 13, 1996
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-hoon Park, Young-woo Seo, Yong-hee Lee
  • Patent number: 5545576
    Abstract: A gate electrode, a semiconductor thin film, a channel protecting film and a photoresist are accumulated on the overall surface of a transparent substrate on which a gate electrode and a gate line are formed. Ultraviolet rays are irradiated through the substrate so that the photoresist and the channel protecting film are self-aligned with respect to the gate electrode and the gate line. A mask is formed on the channel protecting film so as to extend in a direction perpendicular to the channel protecting film. The channel protecting film and the semiconductor thin film are etched using the mask. As a result, the semiconductor thin film and the channel protecting film are patterned without positional deviation so as to have the same width W. Therefore, it is possible to reduce the thin film transistor forming region and the number of steps of the manufacturing process.
    Type: Grant
    Filed: April 21, 1995
    Date of Patent: August 13, 1996
    Assignee: Casio Computer Co., Ltd.
    Inventors: Hiroshi Matsumoto, Haruo Wakai, Hiroyasu Joubettou
  • Patent number: 5540785
    Abstract: A method for fabricating silicon on insulator structures having a dislocation free silicon layer. The method utilizes low temperature UHVCVD to deposit a very heavily doped etch stop layer having a very steep doping profile onto a substrate and a lightly doped active layer onto the etch stop layer. An insulator is formed on the active layer and a carrier wafer is formed on the insulator layer. The original substrate is removed in a first etch and the etch stop layer is removed in a second etch resulting in a thin, uniform active layer. In one embodiment, a small percentage of germanium is added to the etch stop layer to produce a defect free epitaxial active layer.
    Type: Grant
    Filed: April 4, 1994
    Date of Patent: July 30, 1996
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Dennard, Bernard S. Meyerson, Robert Rosenberg
  • Patent number: 5536360
    Abstract: The subject invention provides a method of enhancing the etch rate of boron nitride which comprises doping a layer of boron nitride with an element from Group IVA of the Periodic Table of the Elements, such as silicon, carbon, or germanium. The doped boron nitride layer can be wet etched at a faster rate with hot phosphoric acid than was possible prior to doping the boron nitride.
    Type: Grant
    Filed: January 3, 1995
    Date of Patent: July 16, 1996
    Assignee: International Business Machines Corporation
    Inventors: Son V. Nguyen, David M. Dobuzinsky
  • Patent number: 5529941
    Abstract: A method for making an integrated circuit in accordance with the present invention comprises fabricating at least one functional MOSFET with a hot electron resistant structure including a lightly doped drain, fabricating at least one output MOSFET with an ESD resistant structure including a gate means without associated spacers, and electrically coupling at least one functional MOSFET to at least one output MOSFET. An integrated circuit structure in accordance with the present invention includes at least one functional MOSFET having a hot electron resistant structure including a LDD drain, at least one output MOSFET having an ESD resistant structure including a gate means without associated spacers, and means for electrically coupling the two together. The functional MOSFET includes a gate insulator, a conductive gate region over the gate insulator, spacers along the sidewalls of the gate insulator and conductive gate regions, a pair of LDD regions, and source/drain regions.
    Type: Grant
    Filed: March 28, 1994
    Date of Patent: June 25, 1996
    Assignee: VLSI Technology, Inc.
    Inventor: Tiao-Yuan Huang
  • Patent number: 5525528
    Abstract: Ferroelectric capacitors in an integrated memory are renewed to improve retention performance. The renewal method is performed on a wafer containing ferroelectric memory die. In one method, a rejuvenation anneal is performed after all electrical tests, including those at elevated temperatures, have been accomplished, but before the failed die have been inked. The rejuvenation anneal is performed at or above the Curie temperature of the ferroelectric material. In the preferred embodiment, the ferroelectric material is PZT, and the rejuvenation anneal is a thermal treatment at 400.degree. Centigrade in a nitrogen flow of roughly ten liters per minute for about an hour. In another method, separate electrical cycling and depoling operations are performed to provide the equivalent benefits of the single rejuvenation anneal. The electrical cycling operation is accomplished by writing about one hundred cycles at five volts alternating logic states into each ferroelectric capacitor into the array.
    Type: Grant
    Filed: February 23, 1994
    Date of Patent: June 11, 1996
    Assignee: Ramtron International Corporation
    Inventors: Stanley Perino, Sanjay Mitra
  • Patent number: 5525527
    Abstract: A process for producing an array of solid state radiation detectors includes depositing on a substrate one or more layers of silicon-based materials and then depositing a metal layer overlying silicon-based substance. The metal layer is formed into an array of metal layer regions, and then the metal layer is used as a mask to remove exposed adjacent silicon-based substance layers thereby forming an array of silicon-based substance layers that are aligned with the array of metal layers for forming an array of photosensitive sensing devices. The process of the present invention reduces the number of microlithography steps that are used in forming an array of layered amorphous silicon photosensitive devices.
    Type: Grant
    Filed: February 3, 1995
    Date of Patent: June 11, 1996
    Assignee: Minnesota Mining and Manufacturing Company
    Inventor: Nang T. Tran
  • Patent number: 5523240
    Abstract: A gate-insulated thin film transistor is disclosed. One improvement is that the thin film transistor is formed on a substrate through a blocking layer in between so that it is possible to prevent the transistor from being contaminated with impurities such as alkali ions which exist in the substrate. Also, a halogen is added to either or both of the blocking layer and a gate insulator of the transistor in order that impurities such as alkaline ions, dangling bonds and the like can be neutralized, therefore, the reliability of the device is improved.
    Type: Grant
    Filed: March 28, 1994
    Date of Patent: June 4, 1996
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Shunpei Yamazaki
  • Patent number: 5523255
    Abstract: A method for forming a device isolation film of a semiconductor device, which includes the steps of forming a pad oxide film on a semiconductor substrate, forming an oxidation buffer layer on the pad oxide film, forming an oxidation prevention film on the oxidation buffer layer, forming an aperture in the oxidation prevention film and a longitudinally co-extensive recess in the oxidation buffer layer, to thereby expose a portion of the oxidation buffer layer, forming a cap oxide film on the exposed portion of the oxidation buffer layer by subjecting a first resultant structure obtained by the preceding steps to a thermal oxidation process, forming an oxynitride film at an interface between the cap oxide film and the oxidation buffer layer by heat-treating a second resultant structure obtained by the preceding steps in a nitrogen atmosphere, and, forming the device isolation film by subjecting a third resultant structure obtained by the preceding steps to a thermal oxidation process.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: June 4, 1996
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-woo Hyung, Don-young Ku, Byung-hong Chung, Yong-oon Hwang, Hung-mo Yang, Yun-seung Shin
  • Patent number: 5518964
    Abstract: A microelectronic connection component includes a dielectric sheet having an area array of elongated, strip-like leads. Each lead has a terminal end fastened to the sheet and a tip end detachable from the sheet. Each lead extends horizontally parallel to the sheet, from its terminal end to its tip end. The tip ends are attached to a second element, such as another dielectric sheet or a semiconductor wafer. The first and second elements are then moved relative to one another to advance the tip end of each lead vertically away from the dielectric sheet and deform the leads into a bent, vertically extensive configuration. The preferred structures provide semiconductor chip assemblies with a planar area array of contacts on the chip, an array of terminals on the sheet positioned so that each terminal is substantially over the corresponding contact, and an array of metal S-shaped ribbons connected between the terminals and contacts.
    Type: Grant
    Filed: July 7, 1994
    Date of Patent: May 21, 1996
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, John W. Smith
  • Patent number: 5518956
    Abstract: A process for repairing an electronic army wafer assembly having a short circuit between two non-insulative layers separated by a dielectric layer includes the step of selectively ablating one of the non-insulative layers so as to electrically isolate the situs of the short circuit while maintaining the electrical integrity of the underlying non-insulative layer intact. A laser beam is directed onto the non-insulative layer and scanned in a selected pattern to isolate the situs of the short circuit; the laser is further controlled such that a selected energy density is delivered to the surface to be ablated such that the underlying non-insulative layer is not damaged.
    Type: Grant
    Filed: September 2, 1993
    Date of Patent: May 21, 1996
    Assignee: General Electric Company
    Inventors: Yung S. Liu, Renato Guida, Ching-Yeu Wei
  • Patent number: 5518966
    Abstract: A method is disclosed for the wet etching of polysilicon, which comprises the steps of: annealing a lamination structure of a doped polysilicon and an undoped polysilicon at a predetermined temperature for a predetermined period; and applying to the annealed lamination structure a chemical etchant comprising nitric acid, fluoric acid, acetic acid and deionized water with the volume ratio of nitric acid to acetic acid to fluoric acid to deionized water being 30:3:x:15+(1-x) wherein x is a real number ranging from 0.2 to 1.0, so as to remove the doped polysilicon film. Instead of fluoric acid, alcohol may be used in the chemical etchant without affecting the etching selectivity. This method is superior in performance with regard to selective etching between the undoped polysilicon and the doped polysilicon. Therefore, the doped polysilicon which is useful in many ways, for example, storage electrode, insertion layer and contact, can be etched in such a thickness as is needed, with the chemical etchant.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: May 21, 1996
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Sang H. Woo
  • Patent number: 5516732
    Abstract: A carrousel type wafer processing machine in which wafers are held in vertical orientations in holders on a rotatable plate and sequenced through a plurality of processing stations for processing, such as by the application of a sputtered film thereto, is provided with a vacuum front end module that transfers wafers between cassette modules in which the wafers are horizontally disposed and a loading and unloading station of the processing machine, through a transfer chamber. The transfer chamber includes a wafer transfer arm, an aligning station, a preheating and degassing station, a cooling station preferably combined with the preheating station, and an uprighting station from which wafers are exchanged with the processing machine. The arm moves unprocessed wafers individually from a cassette module to the aligner, then to the preheating station, then to the uprighting station. The arm also moves processed wafers from the uprighting station, to the cooling station and to a cassette module.
    Type: Grant
    Filed: December 4, 1992
    Date of Patent: May 14, 1996
    Assignees: Sony Corporation, Materials Research Corporation
    Inventor: Christopher Flegal, deceased
  • Patent number: 5516725
    Abstract: A process is provided for producing a Schottky diode having a preselected barrier height .phi..sub.Bn. The substrate is preferably n-GaAs, the metallic contact is derived from a starting alloy of the Formula [.SIGMA.M.sub..delta. ](Al.sub.x Ga.sub.1-x) wherein: .SIGMA.M is a moiety which consists of at least one M, and when more than one M is present, each M is different, M is a Group VIII metal selected from the group consisting of nickel, cobalt, ruthenium, rhodium, indium and platinum, .delta. is a stoichiometric coefficient whose total value in any given .SIGMA.M moiety is 1, and x is a positive number between 0 and 1 (that is, x ranges from greater than 0 to less than 1). Also, the starting alloy is capable of forming with the substrate a two phase equilibrium reciprocal system of the binary alloy mixture [.SIGMA.M.sub..delta. ]Ga-[.SIGMA.M.sub..delta. ]Al-AlAs-GaAs. When members of an alloy subclass within this Formula are each preliminarily correlated with the barrier height .phi..sub.
    Type: Grant
    Filed: June 30, 1993
    Date of Patent: May 14, 1996
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Y. Austin Chang, Chia-Hong Jan, Chia-Ping Chen
  • Patent number: 5512500
    Abstract: A method of fabricating a semiconductor device forms a resist pattern for a gate electrode or the like on a semiconductor device in such a manner that only a fine resist pattern is formed on a resist member by an electron beam lithography and other resist patterns are formed on the same resist member by an optical lithography.
    Type: Grant
    Filed: March 14, 1995
    Date of Patent: April 30, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hisato Oyamatsu
  • Patent number: 5510276
    Abstract: A process for producing a pressure transducer or sensor using the silicon-on-insulator method is provided. The process includes the following steps: (a) producing a monocrystalline silicon film (44) on a silicon substrate (6) at least locally separated from the latter by an insulating layer (42), (b) producing an opening (24) in the silicon film down to the insulating layer, (c) partially eliminating the insulating layer via the opening in order to form the diaphragm in the silicon film, and (d) resealing the opening (26).
    Type: Grant
    Filed: December 15, 1993
    Date of Patent: April 23, 1996
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Bernard Diem, Marie-Therese Delaye
  • Patent number: 5510275
    Abstract: A power semiconductor device having a source region (24) and a drain region (26) disposed in a semiconductor substrate (10). A composite drift region is formed of an n-type first drift region (12) in the substrate (10) and of a second drift region (36) composed of a second type of semiconductor material such as gallium arsenide or silican carbide which is a different material than that of the substrate.
    Type: Grant
    Filed: November 29, 1993
    Date of Patent: April 23, 1996
    Assignee: Texas Instruments Incorporated
    Inventor: Satwinder Malhi
  • Patent number: 5510293
    Abstract: A method for manufacturing semiconductor device having metal leads 14 with improved reliability, and device for same, including metal leads 14 on a substrate 12, a low-dielectric constant material 18 at least between the metal leads 14, and thermoconductive insulating layer 22 deposited on the metal leads 14 and the low-dielectric constant material 18. Heat from the metal leads 14 is transferable to the thermoconductive insulating layer 22, and the thermoconductive insulating layer 22 is capable of dissipating the heat. The low-dielectric constant material 18 has a dielectric constant of less than 3.5. An advantage of the invention is to improve reliability of metal leads for circuits using low-dielectric constant materials.
    Type: Grant
    Filed: May 31, 1994
    Date of Patent: April 23, 1996
    Assignee: Texas Instruments Incorporated
    Inventor: Ken Numata
  • Patent number: 5508207
    Abstract: The present invention provides a method of manufacturing a semiconductor wafer whereby (1) deterioration of a micro-roughness in a low temperature range in hydrogen atmospheric treatment and increase of resistivity due to outward diffusion of an electrically active impurity in a high temperature range are prevented; (2) in the heat treatment in a hydrogen gas atmosphere, the concentration of gas molecules in the atmosphere, such as water, oxygen and the like, are brought to 5 ppm or less in water molecule conversion; and a reaction is suppressed in which a substrate surface is oxidized unequally and the micro-roughness deteriorates; and (3) the same kind of impurity as the electrically active impurity contained in a Si substrate is mixed into the atmosphere and the outward diffusion of the impurity in the vicinity of the Si substrate surface is prevented to prevent variation of the resistivity.
    Type: Grant
    Filed: April 26, 1994
    Date of Patent: April 16, 1996
    Assignee: Sumitomo Sitix Corporation
    Inventors: Masataka Horai, Naoshi Adachi, Hideshi Nishikawa, Masakazu Sano