Patents Examined by Brian E. Hearn
  • Patent number: 5508210
    Abstract: A method of element isolation includes implanting ions in a compound semiconductor substrate at the periphery of a semiconductor device in the substrate to produce a first insulating region having a region of maximum implanted ion concentration within a buffer layer at the deepest of multiple epitaxially grown layers. Even when there is a redistribution of implanted ions due to thermal processing, the implanted ions diffuse so that the concentration of ions becomes uniform in the depth direction and a thermally stable ion implantation concentration distribution as well as stable device characteristics are obtained. A second insulating region having a resistivity different from that of the first insulating region may be produced in a second ion implantation step, relaxing an electric field at the interface between the insulating region and a gate electrode, securing a stable, high gate junction breakdown voltage. Thus, a highly reliable element isolating technique and a highly reliable device are obtained.
    Type: Grant
    Filed: November 17, 1993
    Date of Patent: April 16, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Shinichi Terazono
  • Patent number: 5506167
    Abstract: An improved SRAM resistor structure having implanted therein ions of an material in the surface layer of a drain junction region juxtaposed to an overlying metal contact layer providing the benefits of high resistance, low energy consumption, a single ion implantation step in an easily controlled process while producing a precise resistance desired and a method of making the SRAM resistor structure.
    Type: Grant
    Filed: April 13, 1995
    Date of Patent: April 9, 1996
    Assignee: United Microelectronics Corp.
    Inventors: Hwi-Huang Chen, Gary Hong
  • Patent number: 5506153
    Abstract: Controllable power semiconductor components such as, for example, IGBTs and thyristors are provided, which, compared to known components, have a relatively lightly doped n-buffer zone, a relatively flat p-emitter, and an n-base having a comparatively long charge carrier life expectancy. An advantage is achieved that the controllable power semiconductor component has a temperature-independent tail current, despite a low on-state dc resistance and a high blocking voltage.
    Type: Grant
    Filed: June 13, 1995
    Date of Patent: April 9, 1996
    Assignee: Siemens Aktiengesellschaft
    Inventors: Heinrich Brunner, York C. Gerstenmaier
  • Patent number: 5506174
    Abstract: Semiconductor rectifier devices having oppositely extending terminals lying in a common plane are fabricated using upper and lower lead frames each comprising a pair of parallel side rails and spaced apart cross bars extending between the side rails. Cantilevered terminals are mounted along the cross bars. The cross bars of the upper frame lie in a plane downwardly off-set from the plane of the upper frame, and the cross bars of the lower frame lie in a plane upwardly off-set from the plane of the lower frame. Free ends of the terminals of the upper frame lie in a plane upwardly off-set from the plane of the upper frame cross bars, and free ends of the terminals of the lower frame are off-set downwardly from the plane of the lower frame cross bars. Semiconductor chips are mounted on the terminal free ends of the lower frame, and the upper frame is disposed on top of the lower frame with the upper frame terminals contacting the chips.
    Type: Grant
    Filed: July 12, 1994
    Date of Patent: April 9, 1996
    Assignee: General Instrument Corp.
    Inventors: William Vandenheuvel, Johannes Vandenbroeke
  • Patent number: 5504032
    Abstract: A high precision micromechanical accelerometer comprises a layered structure of five (5) semiconductor wafers insulated from one another by thin semiconductor material oxide layers. The accelerometer is formed by first connecting a coverplate and a baseplate to associated insulating plates. Counter-electrodes, produced by anisotropic etching from the respective insulating plates, are fixed to the coverplate and the baseplate respectively. The counter-electrodes are contactable through the cover or baseplate via contact windows. A central wafer contains a unilaterally linked mass (pendulum) that is also produced by anisotropic etching and which serves as a movable central electrode of a differential capacitor. The layered structure is hermetically sealed by semiconductor fusion bonding. A stepped gradation from the top is formed at a wafer edge region for attaching contact pads to individual wafers to permit electrical contacting of individual wafers. The invention permits fabrication of a .mu.
    Type: Grant
    Filed: April 7, 1994
    Date of Patent: April 2, 1996
    Assignee: LITEF GmbH
    Inventors: Thomas Gessner, Martin Hafen, Eberhard Handrich, Peter Leinfelder, Bruno Ryrko, Egbert Vetter, Maik Wiemer
  • Patent number: 5504019
    Abstract: There is Disclosed a semiconductor device comprising a silicon film formed on a substrate having at least a surface formed of an insulative material, the silicon film being heat-treated at a temperature below 600.degree. C. and being partially coated with a silicon oxide film formed by electronic cyclotron resonance plasma CVD.
    Type: Grant
    Filed: July 7, 1994
    Date of Patent: April 2, 1996
    Assignee: Seiko Epson Corporation
    Inventors: Mitsutoshi Miyasaka, Thomas W. Little
  • Patent number: 5504024
    Abstract: A method for fabricating a MOS transistor includes forming an oxide layer over a silicon substrate of a first conductivity type. A gate electrode is formed over the oxide layer. Ions of a second conductivity type are implanted into the silicon substrate to form lightly-doped source/drain regions. Impurity-containing spacers are formed on sidewalls of the oxide layer and the gate electrode. The spacers are thermally processed to drive impurities of a first conductivity type into the source/drain regions. Finally, ions of a second conductivity type are implanted into the substrate to form heavily-doped source/drain regions.
    Type: Grant
    Filed: July 14, 1995
    Date of Patent: April 2, 1996
    Assignee: United Microelectronics Corp.
    Inventor: Chen-Chung Hsu
  • Patent number: 5504042
    Abstract: This invention provides an improved porous structure for semiconductor devices and a process for making the same. This process may be applied to an existing porous structure 28, which may be deposited, for example, between patterned conductors 24. The process may include baking the structure in a reducing atmosphere, preferably a forming gas, to dehydroxylate the pore surfaces. The process may include baking the structure in a halogen-containing atmosphere to bond halogens to the pore surfaces. It has been found that a porous structure treated in such a manner generally exhibits improved dielectric properties relative to an untreated sample.
    Type: Grant
    Filed: June 23, 1994
    Date of Patent: April 2, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Chi-Chen Cho, Bruce E. Gnade, Douglas M. Smith
  • Patent number: 5504017
    Abstract: Voids in a metallization pattern comprising a barrier layer, such as those generated by stress migration, are detected by applying a current across a test section of the metallization pattern to generate hot spots which are detected as by employing an infrared microscope or with a liquid crystalline material.
    Type: Grant
    Filed: December 20, 1994
    Date of Patent: April 2, 1996
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John T. Yue, Shekhar Pramanick
  • Patent number: 5502004
    Abstract: In a method for forming a metal wiring layer of a semiconductor device an insulating layer is formed on a semiconductor substrate having impurity-doped regions. A contact hole is formed in the insulating layer to expose an impurity-doped semiconductor region. Thereafter, a diffusion barrier layer is formed on the inner surface of the contact holes and on the surface of the semiconductor substrate exposed by the contact holes. The diffusion barrier layer is heat-treated for two minutes to one hour in a vacuum at a temperature of 450.degree. C. to 650.degree. C. Then, a metal wiring layer of a semiconductor device is formed on the diffusion barrier layer.
    Type: Grant
    Filed: September 7, 1993
    Date of Patent: March 26, 1996
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chang-soo Park
  • Patent number: 5501995
    Abstract: A method for manufacturing an electrode, e.g., a gate electrode of a MOS transistor, and an electrode and MOS transistor manufactured in accordance with this method. The method includes the steps of forming a first diffusion preventing layer on an underlying layer, forming a mask pattern having an opening on the first diffusion preventing layer, forming a metal layer on a portion of the first diffusion preventing layer exposed by the opening in the mask pattern, forming a metal layer on the exposed portion of the first diffusion preventing layer, forming a second diffusion preventing layer on the resultant structure, etching back the second diffusion preventing layer to leave a remaining portion thereof on the metal layer, removing the mask pattern, and forming a third diffusion preventing layer on exposed portions of the remaining portion of the second diffusion preventing layer, exposed sidewalls of the metal layer, and exposed portions of the first diffusion preventing layer.
    Type: Grant
    Filed: December 19, 1994
    Date of Patent: March 26, 1996
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-koock Shin, Kyu-charn Park, Jong Moon, Tae-earn Shim
  • Patent number: 5500386
    Abstract: A method of manufacturing a semiconductor device, where on top of a substrate having already-completed circuit elements and wiring, etc., an insulation underlayer a, Pt layer for a bottom electrode, a dielectric film and a Pt layer for a top electrode are shaped.A top electrode, capacitance insulation film and bottom electrode are formed by etching the Pt layer for the top electrode or the Pt layer for the bottom electrode using an etching gas contained an S component while composing a Pt and S compound. Alternatively the Pt and S compound can be composed first, and then the compound can be etched.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 19, 1996
    Assignee: Matsushita Electronics Corporation
    Inventors: Shoji Matsumoto, Hideo Nikou, Satoshi Nakagawa
  • Patent number: 5498566
    Abstract: An isolation region structure of a semiconductor device and a method for fabricating the same using both a buried oxide isolation technique and a local oxidation of silicon technique, thereby capable of having an advantage of high integrity. In the isolation region structure, narrow trenches are filled only with a polysilicon film whereas wide trenches are filled with a field oxide film and a polysilicon film so as to isolate adjacent active regions from each other.
    Type: Grant
    Filed: June 26, 1995
    Date of Patent: March 12, 1996
    Assignee: LG Semicon Co., Ltd.
    Inventor: Chang J. Lee
  • Patent number: 5498575
    Abstract: A method of mounting electronic components on circuit boards, which includes the steps of obtaining a bonding film member by filling bonding material into openings in a predetermined pattern of an electrically-insulating and heat-proof film and holding the bonding material in the openings by a flux layer laminated on one surface of the film, overlaying the bonding material of the bonding film member onto conductive layers of a circuit board by supplying the bonding film member onto the circuit board, superposing electrodes of electronic components onto the bonding material of the bonding film member by supplying the electronic components onto the bonding film member, and melting the bonding material by heating the circuit board.
    Type: Grant
    Filed: June 22, 1994
    Date of Patent: March 12, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Onishi, Kenichiro Suetsugu
  • Patent number: 5496743
    Abstract: A Novel method of making a semiconductor device (e.g., a HBT) is disclosed. A semiconductor body that comprises bulk semiconductor material and epitaxial semiconductor material on the bulk material is processed by carrying out a first sequence of processing steps on the epitaxial material. The sequence comprises forming at least first and second contact means on the epitaxial material. The resulting intermediate body is mounted, epitaxial material down, on a carrier body (e.g., a Si wafer with integrated circuitry thereon), such that the first and second contact means are electrically connected to, respectively, third and fourth contact means on the carrier body. Mounting is accomplished, exemplarily, by means of anisotropically conductive adhesive means. Subsequent to mounting of the intermediate body on the carrier body, a second sequence of processing steps is carried out on the intermediate body.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: March 5, 1996
    Assignee: AT&T Corp.
    Inventor: Serge Luryi
  • Patent number: 5496775
    Abstract: An integrated circuit (IC) device comprises towers of bonded gold balls located on each bond pad. The towers allow for early encapsulation of the IC die. The IC can then be tested and attached to tab tape or a printed circuit board without particulate contamination concerns.
    Type: Grant
    Filed: April 8, 1994
    Date of Patent: March 5, 1996
    Assignee: Micron Semiconductor, Inc.
    Inventor: J. M. Brooks
  • Patent number: 5496755
    Abstract: Integrated circuits and fabrication methods incorporating both two-terminal devices such as IMPATT diodes (446) and Schottky diodes (454) and three-terminal devices such as n-channel MESFETs (480) in a monolithic integrated circuit.
    Type: Grant
    Filed: August 8, 1994
    Date of Patent: March 5, 1996
    Assignee: Texas Instruments Incorporated
    Inventor: Burhan Bayraktaroglu
  • Patent number: 5496774
    Abstract: An integrated circuit fabrication method begins with semiconductor devices formed on a substrate. A patterned metal layer is deposited on the substrate to connect the semiconductor devices. A nitride layer is deposited over the metal layer and substrate. The nitride layer topography comprises hills located over metal regions and valleys located over non-metal regions. Spin-on-glass (SOG) is deposited over the nitride layer, thereby filling the valleys and covering the hills. The SOG layer and the nitride layer hills are etched back at substantially the same etch rate, using plasma etching, to form a planar surface. An oxide layer is then deposited over the planar surface to encapsulate the semiconductor devices, metal layer, nitride layer and SOG layer. Vias may then be etched through the oxide layer and the nitride layer to expose portions of the underlying metal layer and facilitate upper layer metal connections thereto.
    Type: Grant
    Filed: December 21, 1994
    Date of Patent: March 5, 1996
    Assignee: VLSI Technology, Inc.
    Inventors: Dipankar Pramanik, Vivek Jain, Milind G. Weling
  • Patent number: 5496749
    Abstract: A first sheet of photomask is used when a gate electrode and a gate bus line are formed, a second sheet of photomask is used when patterning is applied to a semiconductor film which becomes an active layer of a transistor on the gate electrode, a third sheet of photomask is used when a pixel electrode, a source electrode, a drain electrode, a drain bus line and a drain bus terminal portion are formed, and a fourth sheet of photomask is used when a film on the drain bus terminal portion, the gate bus terminal .portion and pixel portion is removed, thereby to form thin film transistors arranged in a matrix form.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: March 5, 1996
    Assignee: Fujitsu Limited
    Inventors: Yasuhiro Nasu, Teruhiko Ichimura, Tomotaka Matsumoto
  • Patent number: 5496768
    Abstract: In the first laser beam radiation, a laser beam having a predetermined energy density is scanned on each of predetermined unit irradiated regions at a scanning pitch smaller than the beam size, and in the second laser beam radiation, a laser beam having an energy density lower than that of the laser beam of the first radiation is scanned at a scanning pitch smaller than the beam size on each of unit irradiated regions different from those of the first laser beam radiation.
    Type: Grant
    Filed: November 23, 1994
    Date of Patent: March 5, 1996
    Assignee: Casio Computer Co., Ltd.
    Inventor: Toshio Kudo