Abstract: The present invention provides a method of manufacturing a semiconductor wafer whereby (1) deterioration of a micro-roughness in a low temperature range in hydrogen atmospheric treatment and increase of resistivity due to outward diffusion of an electrically active impurity in a high temperature range are prevented; (2) in the heat treatment in a hydrogen gas atmosphere, the concentration of gas molecules in the atmosphere, such as water, oxygen and the like, are brought to 5 ppm or less in water molecule conversion; and a reaction is suppressed in which a substrate surface is oxidized unequally and the micro-roughness deteriorates; and (3) the same kind of impurity as the electrically active impurity contained in a Si substrate is mixed into the atmosphere and the outward diffusion of the impurity in the vicinity of the Si substrate surface is prevented to prevent variation of the resistivity.

Abstract: Controllable power semiconductor components such as, for example, IGBTs and thyristors are provided, which, compared to known components, have a relatively lightly doped n-buffer zone, a relatively flat p-emitter, and an n-base having a comparatively long charge carrier life expectancy. An advantage is achieved that the controllable power semiconductor component has a temperature-independent tail current, despite a low on-state dc resistance and a high blocking voltage.

Abstract: Semiconductor rectifier devices having oppositely extending terminals lying in a common plane are fabricated using upper and lower lead frames each comprising a pair of parallel side rails and spaced apart cross bars extending between the side rails. Cantilevered terminals are mounted along the cross bars. The cross bars of the upper frame lie in a plane downwardly off-set from the plane of the upper frame, and the cross bars of the lower frame lie in a plane upwardly off-set from the plane of the lower frame. Free ends of the terminals of the upper frame lie in a plane upwardly off-set from the plane of the upper frame cross bars, and free ends of the terminals of the lower frame are off-set downwardly from the plane of the lower frame cross bars. Semiconductor chips are mounted on the terminal free ends of the lower frame, and the upper frame is disposed on top of the lower frame with the upper frame terminals contacting the chips.

Abstract: An improved SRAM resistor structure having implanted therein ions of an material in the surface layer of a drain junction region juxtaposed to an overlying metal contact layer providing the benefits of high resistance, low energy consumption, a single ion implantation step in an easily controlled process while producing a precise resistance desired and a method of making the SRAM resistor structure.

Abstract: This invention provides an improved porous structure for semiconductor devices and a process for making the same. This process may be applied to an existing porous structure 28, which may be deposited, for example, between patterned conductors 24. The process may include baking the structure in a reducing atmosphere, preferably a forming gas, to dehydroxylate the pore surfaces. The process may include baking the structure in a halogen-containing atmosphere to bond halogens to the pore surfaces. It has been found that a porous structure treated in such a manner generally exhibits improved dielectric properties relative to an untreated sample.

Abstract: A high precision micromechanical accelerometer comprises a layered structure of five (5) semiconductor wafers insulated from one another by thin semiconductor material oxide layers. The accelerometer is formed by first connecting a coverplate and a baseplate to associated insulating plates. Counter-electrodes, produced by anisotropic etching from the respective insulating plates, are fixed to the coverplate and the baseplate respectively. The counter-electrodes are contactable through the cover or baseplate via contact windows. A central wafer contains a unilaterally linked mass (pendulum) that is also produced by anisotropic etching and which serves as a movable central electrode of a differential capacitor. The layered structure is hermetically sealed by semiconductor fusion bonding. A stepped gradation from the top is formed at a wafer edge region for attaching contact pads to individual wafers to permit electrical contacting of individual wafers. The invention permits fabrication of a .mu.

Abstract: Voids in a metallization pattern comprising a barrier layer, such as those generated by stress migration, are detected by applying a current across a test section of the metallization pattern to generate hot spots which are detected as by employing an infrared microscope or with a liquid crystalline material.

Abstract: A method for fabricating a MOS transistor includes forming an oxide layer over a silicon substrate of a first conductivity type. A gate electrode is formed over the oxide layer. Ions of a second conductivity type are implanted into the silicon substrate to form lightly-doped source/drain regions. Impurity-containing spacers are formed on sidewalls of the oxide layer and the gate electrode. The spacers are thermally processed to drive impurities of a first conductivity type into the source/drain regions. Finally, ions of a second conductivity type are implanted into the substrate to form heavily-doped source/drain regions.

Abstract: There is Disclosed a semiconductor device comprising a silicon film formed on a substrate having at least a surface formed of an insulative material, the silicon film being heat-treated at a temperature below 600.degree. C. and being partially coated with a silicon oxide film formed by electronic cyclotron resonance plasma CVD.

Abstract: A method for manufacturing an electrode, e.g., a gate electrode of a MOS transistor, and an electrode and MOS transistor manufactured in accordance with this method. The method includes the steps of forming a first diffusion preventing layer on an underlying layer, forming a mask pattern having an opening on the first diffusion preventing layer, forming a metal layer on a portion of the first diffusion preventing layer exposed by the opening in the mask pattern, forming a metal layer on the exposed portion of the first diffusion preventing layer, forming a second diffusion preventing layer on the resultant structure, etching back the second diffusion preventing layer to leave a remaining portion thereof on the metal layer, removing the mask pattern, and forming a third diffusion preventing layer on exposed portions of the remaining portion of the second diffusion preventing layer, exposed sidewalls of the metal layer, and exposed portions of the first diffusion preventing layer.

Abstract: In a method for forming a metal wiring layer of a semiconductor device an insulating layer is formed on a semiconductor substrate having impurity-doped regions. A contact hole is formed in the insulating layer to expose an impurity-doped semiconductor region. Thereafter, a diffusion barrier layer is formed on the inner surface of the contact holes and on the surface of the semiconductor substrate exposed by the contact holes. The diffusion barrier layer is heat-treated for two minutes to one hour in a vacuum at a temperature of 450.degree. C. to 650.degree. C. Then, a metal wiring layer of a semiconductor device is formed on the diffusion barrier layer.

Abstract: A method of manufacturing a semiconductor device, where on top of a substrate having already-completed circuit elements and wiring, etc., an insulation underlayer a, Pt layer for a bottom electrode, a dielectric film and a Pt layer for a top electrode are shaped.A top electrode, capacitance insulation film and bottom electrode are formed by etching the Pt layer for the top electrode or the Pt layer for the bottom electrode using an etching gas contained an S component while composing a Pt and S compound. Alternatively the Pt and S compound can be composed first, and then the compound can be etched.

Abstract: An isolation region structure of a semiconductor device and a method for fabricating the same using both a buried oxide isolation technique and a local oxidation of silicon technique, thereby capable of having an advantage of high integrity. In the isolation region structure, narrow trenches are filled only with a polysilicon film whereas wide trenches are filled with a field oxide film and a polysilicon film so as to isolate adjacent active regions from each other.

Abstract: A method of mounting electronic components on circuit boards, which includes the steps of obtaining a bonding film member by filling bonding material into openings in a predetermined pattern of an electrically-insulating and heat-proof film and holding the bonding material in the openings by a flux layer laminated on one surface of the film, overlaying the bonding material of the bonding film member onto conductive layers of a circuit board by supplying the bonding film member onto the circuit board, superposing electrodes of electronic components onto the bonding material of the bonding film member by supplying the electronic components onto the bonding film member, and melting the bonding material by heating the circuit board.

Abstract: In the first laser beam radiation, a laser beam having a predetermined energy density is scanned on each of predetermined unit irradiated regions at a scanning pitch smaller than the beam size, and in the second laser beam radiation, a laser beam having an energy density lower than that of the laser beam of the first radiation is scanned at a scanning pitch smaller than the beam size on each of unit irradiated regions different from those of the first laser beam radiation.

Abstract: Disclosed is a method of fabricating a metal semiconductor field effect transistor, comprising the steps for, forming the channel using an ion-implantation, sequentially forming a first insulator layer at a first predetermined temperature and a second insulation layer at second predetermined temperature over the surface of the substrate, etching the first and second insulation layers using a gate pattern of a photo-resist pattern to expose the channel region as a mask, forming a refractory metal over the surface of the first and second insulation layer add the exposed channel region, etching the refractory metal, thereby dividing it into two parts of which one is formed on the channel region and the other is formed on the second insulation layer, selectively etching the first and second insulation layers to lift-off the refractory metal over the first and second insulation layers, thereby forming a gate of a T-shape on the channel region, ion implanting Si into a substrate using the gate and a channel pattern

Abstract: A bipolar transistor having an emitter, a base, and a collector includes an intrinsic base region having narrow side areas and a wider central area. The side areas are located adjacent to the extrinsic base region, while the central area is disposed underneath the emitter. The lateral doping profile of the base is tailored so that the doping concentrations in the extrinsic region and the central area are relatively high compared to the doping concentration of the narrow side areas of the intrinsic base. The combination of the narrow side areas and the lateral base doping profile constrains the depletion region within the base thereby lowering punch-through voltage of the transistor without loss of beta.

Abstract: A first sheet of photomask is used when a gate electrode and a gate bus line are formed, a second sheet of photomask is used when patterning is applied to a semiconductor film which becomes an active layer of a transistor on the gate electrode, a third sheet of photomask is used when a pixel electrode, a source electrode, a drain electrode, a drain bus line and a drain bus terminal portion are formed, and a fourth sheet of photomask is used when a film on the drain bus terminal portion, the gate bus terminal portion and pixel portion is removed, thereby to form thin film transistors arranged in a matrix form.

Abstract: A Novel method of making a semiconductor device (e.g., a HBT) is disclosed. A semiconductor body that comprises bulk semiconductor material and epitaxial semiconductor material on the bulk material is processed by carrying out a first sequence of processing steps on the epitaxial material. The sequence comprises forming at least first and second contact means on the epitaxial material. The resulting intermediate body is mounted, epitaxial material down, on a carrier body (e.g., a Si wafer with integrated circuitry thereon), such that the first and second contact means are electrically connected to, respectively, third and fourth contact means on the carrier body. Mounting is accomplished, exemplarily, by means of anisotropically conductive adhesive means. Subsequent to mounting of the intermediate body on the carrier body, a second sequence of processing steps is carried out on the intermediate body.

Abstract: Alignment marks used in different processes are arranged on scribing lines. The scribing lines are used for cutting off individual semiconductor devices formed on a wafer, and the alignment marks have widths which are larger than widths of the scribing lines. The width of areas corresponding to position where alignment marks are formed area enlarged so as to accommodate the alignment marks within the areas. A part of the area a used alignment mark is covered with a new film so that the area is permitted to have a scribing line having a desired width every time a used alignment is generated. A new alignment mark is arranged within other areas where an alignment mark is not formed. In such an arrangement of the alignment marks, the center line of the scribing line is made clear and the area where the semiconductor devices are formed can be made large.