Abstract: This invention provides a semiconductor device and process for making the same with dramatically reduced capacitance between adjacent conductors and an interlayer dielectric construction which emphasizes mechanical strength, etch compatibility, and good heat transfer. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric and provide mechanical strength, heat transfer, and a solid layer for via etch. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

Abstract: A method for forming patterned buried components, such as collectors, sources and drains, in silicon-on-insulator (SOI) devices. The method is carried out by epitaxially growing a suitable sequence of single or multiple etch stop layers ending with a thin silicon layer on a silicon substrate, masking the silicon such that the desired pattern is exposed, introducing dopant and activating in the thin silicon layer to form doped regions. Then, bonding the silicon layer to an insulator substrate, and removing the silicon substrate. The method additionally involves forming electrical contact regions in the thin silicon layer for the buried collectors.

Abstract: A process for manufacturing an offset gate structure thin film transistor which includes the steps of forming a first semiconductor layer, e.g., an active layer made of amorphous silicon or polysilicon, on a major surface of a substrate, e.g.

Abstract: The single crystal silicon wafers which have undergone a treatment with a chemical liquid such as an acid or an alkali are stored without entailing contamination of their surfaces by causing the wafers to be immediately immersed, either directly or after being washed with water, in an aqueous hydrogen peroxide solution. The prevention of the contamination of surfaces of the wafers is attained effectively by setting the concentration of hydrogen peroxide in the aqueous hydrogen peroxide solution in the range of from 0.01 to 30% by weight and the temperature of the aqueous hydrogen peroxide solution at the time that the wafers are immersed in the solution in the range of from 10.degree. to 30.degree. C.

Abstract: An integrated circuit includes a ground plane structure which provides a uniform ground potential throughout the integrated circuit and improves its performance. The ground plane structure is carried atop the active circuit elements of the integrated circuit and connects with each of the ground-potential contact pads of the circuit. A method of making the integrated circuit includes applying a ground plane precursor structure over all of the integrated circuit topology, and removing portions of the precursor structure where the ground plane is not desired. A method of providing bump structures at each of the contact pads for use in TAB bonding of the electrical connections of the integrated circuit to a package structure is also set forth.

Abstract: A method for the preparation of semiconductor devices which comprises steps of forming a nitride film on a first conductivity type semiconductor substrate, selectively removing the nitride film, oxidation with the remaining nitride film as the mask to form insulation oxide films for element isolation on the semiconductor substrate, forming a second insulation film on the entire surface of the substrate, and implanting a second conductivity type impurity through the entire surface of the substrate to form second conductivity type channel stoppers under the insulation oxide films.

Abstract: A field effect transistor which is not susceptible to mask edge defects at its gate spacer oxides. The transistor is formed upon a (100) silicon semiconductor substrate through successive layering of a gate oxide, and a gate electrode. A pair of gate spacer oxides is then formed covering opposite edges of the gate oxide and the gate electrode. A screen oxide is then formed over the surface of the semiconductor substrate, the gate and the gate spacer oxides. The upper surface of the screen oxide has an angle of elevation not exceeding 54.44 degrees with respect to the semiconductor substrate. The screen oxide also smoothly flows from thicker regions at the junctures of the gate spacer oxides and the semiconductor substrate to thinner regions over the surface of the semiconductor substrate. The semiconductor substrate adjoining the gate spacer oxides is then ion implanted through the screen oxide to form amorphous source/drain electrodes.

Abstract: An inexpensive packaged integrated circuit with improved heat dissipative capacity and electrical performance. In one embodiment, the packaged integrated circuit includes a semiconductor die, a plurality of electrically conductive package leads, a thermal induction plate and a plurality of electrically conductive bond wires. A surface of the thermal induction plate may remain exposed outside the package. The thermal induction plate reduces package lead inductance and provides shielding of electromagnetic radiation that can cause electromagnetic interference. Preferably, holes are formed through the thermal induction plate to enhance flow of the package material during formation of a package and provide interlocking of the package to the remainder of the integrated circuit. In another embodiment, the packaged integrated circuit further includes a heat sink having a surface exposed to the exterior of the package.

Abstract: A process for fabricating the metal-to-metal antifuse of the present invention includes the steps of forming a first metal layer on a semiconductor or other microcircuit structure; forming a first barrier layer over the first metal layer; forming a thick insulating layer over the barrier layer; forming an antifuse aperture in the thick insulating layer; forming a first heavily doped amorphous silicon layer in the aperture over the first barrier layer; forming a dielectric antifuse material layer over the first amorphous silicon layer; forming a second heavily doped amorphous silicon layer over the first dielectric antifuse material layer; forming a second barrier layer over the second amorphous silicon layer; and forming a second metal layer over the second barrier layer.

Abstract: An object of the invention is to prevent the occurrence of breaking or short-circuiting of a wiring caused by a difference in level in an isolation trench area formed in an SOI substrate. An oxide film is formed for a pad on the main surface of an SOI layer formed on an insulating substrate, a silicon nitride film are formed and an SiO.sub.2 film in order, then an isolation trench reaching to the insulating substrate is by means of an R.I.E process using the SiO.sub.2 film as a mask. Thereafter an insulating film is formed on an inside wall of the isolation trench by means of thermal oxidation, the isolation trench is filled with polysilicon, the polysilicon is etched back while controlling the etching so that the top of the polysilicon in the isolation trench remains higher than the top of the silicon nitride film, an extra part of the polysilicon deposited on the surface of the substrate, is removed and then the SiO.sub.

Abstract: With a semiconductor device manufacturing method, a lower-layer interconnection is formed on a circuit board on which a plurality of semiconductor chips are mounted. Using a screen plate with openings corresponding to desired positions on the lower-layer interconnection, screen printing of a metal paste is effected, and the printed metal paste is dried and calcined by heat treatment to form a metal pillar on the lower-layer interconnection. An insulating film covering the lower-layer interconnection and the metal pillar is formed so that the tip of the metal pillar may be exposed. An upper-layer interconnection is formed on the insulating film so that this layer may contact with the exposed tip of the metal pillar.

Abstract: The present invention provides a multi-chip module having multiple compartments. Circuitry is arranged on a substrate in such a manner that circuit components requiring specific operating environments are located in discrete areas dedicated to accommodate the circuit components. A cover, having multiple chambers that align with the discrete areas on the substrate, is secured to the substrate to define the multiple compartments. The compartments are separated by material that effectively isolates the compartments relative to one another.

Abstract: A process of providing an external wiring and connecting package for a semiconductor chip wherein the chip is a major contributor to the strength of the package. External contacts and wiring are provided by a multilayer wiring member that may include a mesh ground plane with embedded power bus layer over a conductor layer for expansion mismatch control and impedance control, a protective encapsulation covers the bonds from the wiring conductors to the chip, and external contact connections employ fused metal through the contact members.

Abstract: A cube package of stacked silicon semiconductor chips. To accommodate cube packaging, a metal transfer layer is added over the passivated chip face to bring all of the surface electrical contacts to a common chip edge. The metal transfer layer is insulated from the chip face and from the adjacent chip in the stack by polymer layers having a low dielectric constant, and a thermal expansion coefficient matching that of the stacked chips. An adhesive polymer layer is added to strengthen the bond between the first polymer layers and the adjacent chip in the stack, by deposition of the adhesive layer and partial cure at the wafer level, and then full cure when the chips are stacked together to form the cube.

Abstract: A method of making a gettering structure for dielectrically isolated wafer structures, such as bonded wafers. A getterer layer is deposited over the wafer having semiconductor regions isolated from each other by trenches. The polysilicon is etched back leaving the polysilicon on the sides of the regions. The polysilicon may be doped. The polysilicon is oxidized and a second layer of polysilicon may be deposited to fill voids in the trenches.

Abstract: Process for producing a semiconductor field detector magnetic head and head obtained by this process. On a silicon substrate (30) is produced a semiconductor sensor (32) and then the magnetic circuit of the head (36,48,50,52,54). Application to magnetic recording. (FIG.

Abstract: A semiconductor gas rate sensor includes a base composed of a first semiconductor substrate and a second semiconductor substrate bonded thereto by a thermosetting adhesive layer deposited on a mating surface of the second semiconductor substrate, the base having a gas flow passage defined therein and a nozzle defined therein for injecting a gas flow into the gas flow passage, and a detector disposed in and extending across the gas flow passage for detecting a deflected state of the gas flow when an angular velocity acts on the base, the nozzle being formed between a recess defined in mating surface of the first semiconductor substrate and the mating surface of the second semiconductor substrate.

Abstract: A flash EPROM cell has a reduced cell size by providing vertical coupling between the floating gate and the bit line during programming. The erase operation is done by tunneling of electrons from the sharp tip of the Poly spacer to the control gate. The cell is adapted so that the source for each cell within the array is the source of an adjacent cell and the drain is the drain to another adjacent cell. The cell is formed by forming the drain regions into the substrate through openings in a first insulator that is preferably the field oxide. A second insulator is deposited over the first insulator, over the substrate and along the side walls of the openings and is preferably a thin layer so that the opening is covered with a thin insulating layer. The insulated opening is filled with a first doped polysilicon layer. The field oxide is selectively removed.

Abstract: A method for fabricating semiconductor devices with a self-spaced contact is provided. Spacing required between the self-spaced contact and a gate region is lessened, thus reducing chip size, and parasitic capacitance and resistance. A transistor region includes a gate and diffusion region. A pad oxide layer comprises an uppermost layer of the gate. A spacer oxide is formed on side walls of the gate region. The thickness of the pad oxide layer controls the width of the spacer oxide region. The spacer oxide insulates the gate from the diffusion regions, so that electrical contacts may be formed close to the gate for reducing the overall size of the semiconductor device. The doping structure of the diffusion regions is controlled by the width of the spacer oxide regions. Thus, the doping structure of the diffusions can be altered to reduce parasitic capacitance and resistance.

Abstract: A method for manufacturing semiconductor device having metal leads 14 with improved reliability, and device for same, comprising metal leads 14 on a substrate 12, a low-dielectric constant material 18 at least between the metal leads 14, and thermoconductive insulating layer 22 deposited on the metal leads 14 and the low-dielectric constant material 18, and dummy leads 16 proximate metal leads 14. Heat from the metal leads 14 is transferable to the dummy leads 16 and thermoconductive insulating layer 22, which are both capable of dissipating the heat. A thin thermoconductive layer 24 may be deposited over the metal leads 14 prior to depositing at least the low-dielectric constant material 18 and the thermoconductive insulating layer 22. The low-dielectric constant material 18 has a dielectric constant of less than 3.5. An advantage of the invention is to improve reliability of metal leads for circuits using low-dielectric constant materials.