Abstract: A semiconductor structure (8) comprising a semiconductor chip support structure (9), a circuit board substrate (40) with circuit board substrate probes (36) extending therefrom and a method for fabricating the semiconductor structure (8). The semiconductor chip support structure (9) includes, for example, clips (43, 53) to replaceably mount semiconductor chips (47, 48) to the semiconductor chip support structure (9). The circuit board substrate (40) is mated with the semiconductor chip support structure (9) so that the circuit board substrate probes (36) contact bonding pads (49) on the semiconductor chips (47, 48). If a semiconductor chip (47, 48) becomes damaged, the circuit board substrate (40) may be separated from the semiconductor chip support structure (9) and the damaged semiconductor chip (47, 48) replaced with a good semiconductor chip (47, 48).

Abstract: The present invention provides a novel method of forming an isolation region comprising a trench isolation region and a selective oxidation film region involved in a semiconductor integrated circuit device. A silicon oxide film is deposited on a surface of a trench groove formed within a semiconductor bulk, followed by a deposition of a polycrystalline silicon material. The silicon oxide film within the trench groove is subjected to etching up to a predetermined depth so as to form a hollow portion. A polycrystalline silicon film is deposited within the hollow portion and on both surfaces of the polycrystalline silicon material and the semiconductor bulk. The polycrystalline silicon film within the hollow portion, the polycrystalline silicon material and the semiconductor bulk in the vicinity of the trench groove is subjected to selective oxidation so as to form a selective oxidation film region.

Abstract: A process for producing a semiconductor service of the type having a semiconductor substrate; a semiconductor layer disposed on the semiconductor substrate; a first element formed in a region of the semiconductor layer and having a perimeter including a bottom; a second element formed in another region of the semiconductor layer; an insulating layer surrounding the perimeter of the first element, for electrically insulating and separating the first element from the second element and the semiconductor substrate; an electrical shield layer disposed between the insulating layer and the first element, surrounding the perimeter of the first element, and adapted to a reference electric potential applied thereto, for shielding the first element from an electrical fluctuation of the semiconductor substrate caused by the second element; and an electrode for applying the reference electric potential to the electrical shield layer.

Abstract: A method of patterning a metallized substrate using a thin partially cured etch block layer. In accordance with the method, a substrate is provided and a layer of metal, such as aluminum, is deposited on the substrate. A thin layer of organic dielectric material, such as polyimide, is deposited over the layer of metal. The thin layer of organic dielectric material is deposited to a thickness on the order one micron, for example, which is thin enough to have etch resistance when acting as an etch block layer for subsequent wet etch patterning of the layer of metal, and thick enough to have no pinhole defects. The deposited thin organic dielectric layer is then partially cured. The underlying layer of metal is then patterned and wet etched using the partially cured thin organic dielectric material as the blocking layer. An additional thick layer of organic dielectric material is then deposited or coated over the patterned layer of metal and partially cured organic dielectric layer.

Abstract: A method for forming a field oxide layer of a highly integrated semiconductor device comprises the steps of depositing a pad oxide layer and a nitride layer over a substrate, removing the nitride layer over a field region, forming spacers on the side walls of the remaining nitride layer, doping an impurity into the field region using the spacers as a mask, thermally oxidizing the substrate exposed in the field region, growing the field oxide layer, and planarizing the upper portion of the field oxide layer by an etchback process, thereby reducing the step coverage problem of the field oxide layer.Therefore, the size of bird's beak and stress can be reduced at the edges of the field region. The heavily doped channel stop layer is formed only in the middle section of the field region, thereby preventing the lowering of the breakdown voltage and punch-through.

Abstract: A process useful for isolating active areas of semiconductor devices in which an isolation trench is created in a substrate, the isolation trench being lined with an oxidation barrier and filled with a thick film. An oxidation step is performed in which the thick film is oxidized. The oxidation is self-limiting as the oxidation barrier prevents the substrate surrounding the trench from being oxidized.

Abstract: Plasma etching with hydrogen bromide or bromine as an etching gas allows a precise control in attaining vertical etching or taper etching with a desired taper angle by controlling the temperature of a mass to be etched, which mass is usually a semiconductor wafer.

Abstract: A method and an electrically conductive interconnect structure (30) for controlling electromigration. The electrically conductive interconnect structure (30) comprises a groove (33) adjacent an electrically conductive interconnect (39). The electrically conductive interconnect (39) is patterned from a deposited layer of conductive material which contains global grain microstructures. Moreover, the electrically conductive interconnect (39) is patterned to have polycrystalline and single-grain segment lengths that are less than a length at which an electromigration flux fails to overcome a gradient-driven counter flux in a line segment. The groove (33) controls the polycrystalline and single-grain segment lengths to be less than the critical length, thereby reducing electromigration.

Abstract: An integrated circuit fabrication process for creating field oxide regions in a substrate is disclosed. In the process, masking layers of oxide, nitride and deposited silicon dioxide are formed on the substrate. A pattern that defines the field oxide regions in the substrate is introduced into the substrate through these masking layers. The field oxide region is bordered by steep sidewalls in a portion of the substrate and the masking layers overlying the substrate. A thin layer of oxide is grown on the exposed portion of the substrate, and a conformal second layer of nitride followed by a conformal layer of a polycrystalline material are formed over the substrate/mask structure. The polycrystalline layer is selectively removed, so that the only portion of the polycrystalline material that remains on the structure is the portion covering the sidewalls.

Abstract: A trench structure is produced in a substrate wafer in a two-step trench process. A trench mask is produced in a first etching step and the trench structure is realized in the substrate wafer in a second etching step. An auxiliary lithography structure is produced in the substrate wafer in the trench process. A protective structure that protects the substrate wafer in the region of the auxiliary lithography structure against an etching attack in the second etching step is formed in the region of the auxiliary lithography structure in the manufacture of the trench mask.

Abstract: This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

Abstract: In a method of planarizing a semiconductor wafer having aluminum interconnect tracks formed thereon, a method is disclosed for applying inorganic spin-on glass which comprises applying the spin-on glass to the wafer in a coating and spinning chamber in a moisture-free environment, transferring the wafer in a moisture-free environment to a curing station, curing the spin-on glass at a temperature in the range of about 80.degree. to 250.degree. C. in the moisture-free environment at the curing station, and returning the wafers to the coating and spinning chamber. The above steps are repeated until a sufficient film thickness has been achieved without in the interim exposing the wafer to moisture conditions such that reverse hydrolysis si minimized during the planarization process. In this way crack-free inorganic SOG films can be produced.

Abstract: A manufacturing method for a semiconductor device, which can attain a low ion voltage in a manufacturing method for a semiconductor device involving a process for forming a groove by etching prior to selective oxidation, selectively oxidizing a region including the groove and thereby making a channel part of the groove, is disclosed. A groove part is thermally oxidized by using a silicon nitride film as a mask. A LOCOS oxide film is formed by this thermal oxidation, and concurrently a U-groove is formed on the surface of an n.sup.- -type epitaxial layer eroded by the LOCOS oxide film, and the shape of the U-groove is fixed. A curve part formed during a chemical dry etching process remains as a curve part on the side surface of the U-groove. Then, an n.sup.+ -type source layer is formed by means of thermal diffusion to a junction thickness of 0.5 to 1 .mu.m, and a channel is set up as well.

Abstract: To form a contact layer on source and drain electrodes of a stagger-type TFT, a conductive material is selectively sticked to the surface of the source and drain electrodes and a contact layer is selectively deposited by using the conductive material as growth species to form an active semiconductor layer on the contact layer. For an inverted-stagger-type TFT, a conductive material is selectively deposited on the surface of a contact layer to use the selectively deposited conductive material as source and drain electrodes so that patterning is unnecessary. To selectively deposit a contact layer of a TFT by alternately repeating etching and deposition, the temperature for the etching is set to 200.degree. C. or lower. A contaminated layer on the surface of a semiconductor film serving as an active semiconductor layer and contact layer of a TFT is removed by plasma at the temperature of 200.degree. C. or lower.

Abstract: A process for the preparation of a thin film transistor is provided which includes sequentially depositing a gate insulating layer, an amorphous silicon layer, and an n+ amorphous silicon layer. The n+ amorphous silicon layer is disposed between source and drain electrodes and is oxidized by a plasma oxidation process so that switching properties, interface properties between the amorphous silicon layer and the n+ amorphous silicon layer and a production yield are enhanced, while the preparation steps of forming an etch stopper and removing the n+ amorphous silicon layer disposed between the source electrode and the drain electrode are reduced.

Abstract: The method of fabricating a poly-silicon resistor includes a step for providing a dopant gas and a nitrous oxide gas as well as a silane gas to thereby deposit a silicon layer on a substrate by chemical vapor deposition under a deposition temperature not higher than 600 degrees centigrade so that the silicon layer includes the dopant of the dopant gas and oxygen, and a step for annealing the silicon layer under a temperature not lower than 600 degrees centigrade.

Abstract: A method of fabricating a transistor on a wafer including: forming a doped transistor body 42 on top of an insulator 34; doping source/drain regions in the transistor body; forming a gate oxide 44 on top of the transistor body; forming sidewall spacers along the transistor body; depositing a metal layer over the transistor body; forming an amorphous silicon layer over the metal layer, the amorphous silicon layer patterned in a gate and a local interconnect configuration; annealing to form silicided regions above the source/drain regions within the transistor body, and where the metal layer reacts with the amorphous silicon layer to create a silicided gate 50 and a silicided local interconnect 50; and etching unsilicided portions of the metal layer to leave silicided source/drain regions, a silicided gate, and a silicided local interconnect.

Abstract: A pattern for a wafer for a MOS-gated semiconductor device includes plural ribbons extending from a source contact region to another source contact region, each of the ribbons having a single source region between two channel regions, so as to increase the device's current-carrying capability per unit area relative to the prior art. The pattern increases the size of the active current-carrying area (the channel and neck regions of the device) relative to the area of the source contact areas. The source contact regions may be discrete or linear, and the ribbons may extend therefrom perpendicularly or at other angles.

Abstract: An ESD/EOS protection circuit (100) for protecting an integrated circuit. A MOS transistor (102) is arranged in a multi-finger configuration having a plurality of drain regions (124), a plurality of source regions (122) and a plurality of gates (118). A first metal layer (162) substantially covers each of the drain regions (124) and is in contact with each of the drain regions (124) via drain contacts (130). A second metal layer (154) substantially covers each of the source regions (122) and is in contact with each of the source regions via source contacts (128). A plurality of source contacts (128) are located at a minimum distance from gates (118). Metal-to-metal contacts (160) connect a third metal layer (156) with the second metal layer (154) over each of the source regions (122).

Abstract: An isolation structure is disclosed which isolates an active region (24) from other proximate active regions. The isolation structure utilizes the combination of a LOCOS structure (26) comprising bird's beak structure (26a) and (26b). A trench (34) is formed through the LOCOS structure (26). A channel stop implant region (40) is formed along the sidewalls of the trench (34). A trench plug (46) is used to fill the trench. The isolation structure thereby uses the isolation capabilities of trench isolation structures, but prevents the leakage currents common along trench sidewalls by isolating the trench sidewalls from the active region using the LOCOS structures.