Patents Examined by Brian K. Dutton
  • Patent number: 5843796
    Abstract: An improved insulated gate bipolar transistor (IGBT) device structure and a method for fabricating such a device. This structure uses self-aligned and substantially undiffused successive N+ and P+ implants. The P+ implant is at high energy, which forms a subsurface P+ region below the entire bottom of an N+ "source" region of the IGBT. This low resistivity region suppresses thyristor latch-up when contacted via a surface trench. Self-aligned techniques provide method and product improvements.
    Type: Grant
    Filed: September 11, 1995
    Date of Patent: December 1, 1998
    Assignee: Delco Electronics Corporation
    Inventor: Donald Ray Disney
  • Patent number: 5811314
    Abstract: A method for dice manufacturing and sifting out of defective dice by using a magnet includes the following steps: applying magnetic ink onto defective dice; hardening to ink dot on said defective dice; removing the adhesive tape from the dice; removing defective dice through the use of the magnet. Said ink preferably comprises approximately 60%-95% percentage by weight ferromagnetic powder and 40%-5% percentage by weight thermoset resin. By using the magnetic ink and the magnetic separation method, the automation of dice manufacturing can be improved and thereby productivity is increased.
    Type: Grant
    Filed: June 7, 1996
    Date of Patent: September 22, 1998
    Assignee: General Instrument of Taiwan, Ltd.
    Inventors: Yi-Ching Chen, Hahnjong Hsiung, William J. Nelson, Christopher M. Knowles
  • Patent number: 5795793
    Abstract: A reduced mask process for forming a MOS gated device such as a power MOSFET uses a first mask to sequentially form a cell body and a source region within the cell body, and a second mask step to form, by a silicon etch, a central opening in the silicon surface at each cell and to subsequently undercut the oxide surrounding the central opening. A contact layer then fills the openings of each cell to connect together the body and source regions. Only one critical mask alignment step is used in the process.
    Type: Grant
    Filed: September 1, 1994
    Date of Patent: August 18, 1998
    Assignee: International Rectifier Corporation
    Inventor: Daniel M. Kinzer
  • Patent number: 5792675
    Abstract: In an accelerometer sensor of crystalline material, whose components are composed partly of monocrystalline and partly of polycrystalline material, a band-shaped seismic mass preferably is composed of polycrystalline material, whose suspension by means of suspension segments of monocrystalline material at the end regions permits a movement in the longitudinal direction upon the occurrence of an acceleration. Parallel plates extend from this mass at right angles to their longitudinal direction and, together with additional plates, which run parallel to said plates and are anchored at a base, form a capacitor arrangement and are composed, in particular, of monocrystalline material. At least the monocrystalline material is doped to attain an electric conductivity. When lightly doped, the long and thin plates and suspension segments have a high conductivity, given a very small mechanical prestressing, and can easily be isotropically undercut.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: August 11, 1998
    Inventor: Michael Offenberg
  • Patent number: 5780345
    Abstract: There is disclosed a short-channel FET which is excellent in properties and adapted for mass production. FETs of this construction can be packed at a high density. There is also disclosed a method for forming this FET. The semiconductor substrate of this FET has a plateau-shaped portion protruding from the body of the substrate. This plateau-shaped portion is substantially identical in contour with a gate electrode formed over it. The gate electrode is in register with the plateau-shaped portion. With respect to the relation of doped regions of the substrate becoming the source and drain to the channel region, the narrowest portion in the channel region is not in contact with a gate-insulating film.
    Type: Grant
    Filed: March 1, 1996
    Date of Patent: July 14, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuhiko Takemura, Norihiko Seo
  • Patent number: 5759870
    Abstract: Methods for surface micro-machining silicon wafers, including coating cavity sidewalls with oxidation-resistant material to prevent lateral oxidation. This in turn prevents "bird's beak" during formation of a diaphragm. The methods are useful for, among other things, the manufacture of absolute-type pressure sensors. Along with bulk micro-machining techniques, the methods can be used to produce gauge- and differential-type pressure sensors, as well.
    Type: Grant
    Filed: August 28, 1995
    Date of Patent: June 2, 1998
    Assignee: BEI Electronics, Inc.
    Inventors: Weijie Yun, Liwei Lin, Tariq M. Haniff
  • Patent number: 5744397
    Abstract: Disclosed herein is a method of manufacturing a semiconductor device, which comprises steps of forming metal patterns, irradiating an electron beam to electrically neutralize the charge distribution of the metal layer and forming an O.sub.3 -TEOS layer used for planarization of the interlayer insulating layer.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: April 28, 1998
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Dong Sun Sheen
  • Patent number: 5736436
    Abstract: A gate electrode, a semiconductor thin film, a channel protecting film and a photoresist are accumulated on the overall surface of a transparent substrate on which a gate electrode and a gate line are formed. Ultraviolet rays are irradiated through the substrate so that the photoresist and the channel protecting film are self-aligned with respect to the gate electrode and the gate line. A mask is formed on the channel protecting film so as to extend in a direction perpendicular to the channel protecting film. The channel protecting film and the semiconductor thin film are etched using the mask. As a result, the semiconductor thin film and the channel protecting film are patterned without positional deviation so as to have the same width W. Therefore, it is possible to reduce the thin film transistor forming region and the number of steps of the manufacturing process.
    Type: Grant
    Filed: November 20, 1995
    Date of Patent: April 7, 1998
    Assignee: Casio Computer Co., Ltd.
    Inventors: Hiroshi Matsumoto, Haruo Wakai, Hiroyasu Joubettou
  • Patent number: 5733806
    Abstract: A method for forming a self-aligned semiconductor device (10) having sidewall spacers (16,17) used to align the formation of a source region (23) and a drain region (24) along with the formation of a gate structure (35). Spacers (16,17) can be formed using a sacrificial structure process where a sacrificial structure (14) is formed which determines the location of a final gate structure (35). The deposition of a dielectric layer over the sacrificial structure (14) and subsequent etch will form spacers (16,17). A second method for forming spacers (18,19), uses a photolithographic process to pattern a dielectric layer without the use of a sacrificial structure process. The spacers (16,17) are used in conjunction with implant mask regions (22) to form the source and drain regions (23,24) which are aligned to the gate structure (35).
    Type: Grant
    Filed: September 5, 1995
    Date of Patent: March 31, 1998
    Assignee: Motorola, Inc.
    Inventors: Gordon M. Grivna, Karl J. Johnson
  • Patent number: 5733811
    Abstract: An epitaxial layer of a first conductivity type is grown on a main surface of a semiconductor substrate of the first conductivity type. After a gate oxide film is formed on the entire surface of the epitaxial layer, a gate electrode made of polysilicon and having a plurality of stripe sections and an electrode leading-out section is formed. Then, ions are implanted using a first resist and the gate electrode and a deep well of a second conductivity type for raising a drain breakdown characteristic is formed in the surface region of the epitaxial layer by conducting a thermal oxidation process. After ions are implanted using a second resist and the gate electrode, a plurality of bases of the second conductivity type are formed in the surface region of the epitaxial layer by conducting a thermal oxidation process. These bases are connected with one another immediately below a part of each stripe section which part is near the electrode leading-out section of the gate electrode.
    Type: Grant
    Filed: April 11, 1995
    Date of Patent: March 31, 1998
    Assignee: NEC Corporation
    Inventor: Kazuzi Yamazaki
  • Patent number: 5688725
    Abstract: In a vertical trench MOSFET, a layer of increased dopant concentration is formed in a lightly-doped or "drift" region which separates the body region from the drain region of the MOSFET. The layer of increased dopant concentration denominated a "delta" layer, operates to spread out the current as it emerges from the channel of the MOSFET and thereby reduces the resistance of the MOSFET when it is turned on.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: November 18, 1997
    Assignee: Siliconix Incorporated
    Inventors: Mohamed N. Darwish, Richard K. Williams
  • Patent number: 5686323
    Abstract: A method of manufacturing a semiconductor device comprises the steps of:forming an insulative film onto a semiconductor substrate;forming openings into said insulative film;implanting desired impurities into the semiconductor substrate through at least the openings;forming an out diffusion preventing film onto the surfaces of the semiconductor substrate exposed in at least the opening portions after the impurities have been implanted;annealing the semiconductor substrate after the out diffusion preventing film has been formed; andforming a conductive layer onto the out diffusion preventing film.
    Type: Grant
    Filed: February 28, 1994
    Date of Patent: November 11, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yuzo Kataoka
  • Patent number: 5683919
    Abstract: A flip-chip integrated circuit having a transistor 300 with terminals 314, 312, 320 contacted from opposite sufaces of a semiconductor substrate 302. The terminals contacted from opposite surfaces of the substrate may be vertically aligned. The active devices may also be etched or implanted to reduce parasitic capacitances and therefore improve transistor performance.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: November 4, 1997
    Assignee: Texas Instruments Incorporated
    Inventor: Hua Quen Tserng
  • Patent number: 5681768
    Abstract: A transistor having reduced hot carrier implantation is disclosed which is formed on an outer surface (12) of a semiconductor substrate (10). The transistor comprises a source region (22) and a drain region (24) which define there between a channel region (34). A gate insulator layer (14) insulates a gate conductor (16) from the channel region (34). A sidewall insulator body (20) is formed such that a thickened region of insulator separates an end of gate conductor (16) from a portion of channel region (34) proximate drain region (24). This thickened insulator reduces the local electric field in channel region (34) near drain region (24) and correspondingly reduces the implantation into gate insulator (14) of hot carriers generated from impact ionization.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 28, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Michael C. Smayling, David A. Baglee
  • Patent number: 5677204
    Abstract: A semiconductor device (100) including a silicon substrate (1), a gate oxide film (2) formed on the silicon substrate (1) and having a defect (3) and a dielectric breakdown voltage failure portion (4), and a polysilicon film (5) formed on the gate oxide film (2) is immersed in a chemical etchant (7) in a wet etching apparatus (9). With the silicon substrate (1) serving as an anode, a DC voltage source (6) of the wet etching apparatus (9) applies voltage to the silicon substrate (1) to perform anode oxidation. Passivation layers (10) are formed on parts of the surface of the polysilicon film (5) which overlies the defect (3) and dielectric breakdown voltage failure portion (4) but are not formed on the surface of the polysilicon film (5) in regions insulated by the gate oxide film (2). The polysilicon film (5) in the regions on which the passivation layers (10) are not formed is removed by the chemical etchant (7).
    Type: Grant
    Filed: April 10, 1996
    Date of Patent: October 14, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yukari Imai, Toshiharu Katayama, Naoko Otani
  • Patent number: 5677200
    Abstract: A method of manufacturing a color charge-coupled device is disclosed including the steps of alternately forming a plurality of light detectors corresponding to first to third colors and a plurality of charge transmission regions on a semiconductor substrate; forming a pad on one side of the substrate excluding a portion where the light detectors and charge transmission regions are formed; forming a planarizing film on the substrate excluding the pad; coating a microlens material on the planarizing film and patterning the microlens material so as to be left only on the planarizing film above the light detectors; thermally flowing the microlens material, to thereby form microlenses on the planarizing film above the light detectors; and hard-baking first to third dyeing layer, to thereby form first to third color filter layers on each microlens excluding the edge portion.
    Type: Grant
    Filed: May 17, 1995
    Date of Patent: October 14, 1997
    Assignee: LG Semicond Co., Ltd.
    Inventors: Chul Ho Park, Jin Seop Shim, Kwang Bok Song
  • Patent number: 5668045
    Abstract: A process for stripping the outer edge of a bonded BESOI wafer. The bonded BESOI wafer comprises a handle wafer, an oxide layer on one surface of the handle wafer, a device layer bonded to the oxide layer, and a p.sup.+ etch-stop layer on the device layer having an exposed face. The process comprises masking the exposed face of the p.sup.+ etch-stop layer, and abrading the periphery of the BESOI wafer to remove edge margins of the p.sup.+ etch-stop layer and device layer.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: September 16, 1997
    Assignee: SiBond, L.L.C.
    Inventors: David I. Golland, Robert A. Craven, Ronald D. Bartram
  • Patent number: 5663075
    Abstract: A photo FET device having a large area backside optical energy reception surface is disclosed. The photo FET device is fabricated in the source gate and drain upward configuration and then inverted onto a new permanent substrate member and an original surrogate substrate member removed in order to expose the active area backside optical energy reception surface. Electrical characteristics including curve tracer electrical data originating in both dark and illuminated devices and devices of varying size and both depletion mode and enhancement mode operation are also disclosed. Fabrication of the device from gallium arsenide semiconductor material and utilization for infrared energy transducing in a number of differing electronic applications are also disclosed.
    Type: Grant
    Filed: July 14, 1994
    Date of Patent: September 2, 1997
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: Gerald D. Robinson
  • Patent number: 5661066
    Abstract: In an integrated circuit comprising an IIL and a high frequency npn bipolar transistor which has a deep p.sup.- -type base region 45 for its inverted npn output transistors, circuit elements such as a resistor part R, a capacitor part C, a diode part D and an isolated crossing connection part Cr are provided with deep p.sup.- -type regions 54, 54', 65', 71 and 82 which are formed at the same time with the p.sup.- -type region 45 in the IIL, and thereby, reliability of the circuit elements as well as characteristic thereof are improved, thereby further improving manufacturing yields.
    Type: Grant
    Filed: April 2, 1991
    Date of Patent: August 26, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toyoki Takemoto, Haruyasu Yamada, Tsutomu Fujita, Tadao Komeda
  • Patent number: RE36311
    Abstract: A description is given of two versions of an integrated structure in the emitter switching configuration comprising a high-voltage bipolar power transistor and a low-voltage MOS power transistor. In the vertical MOS version, the emitter region of the bipolar transistor is completely buried, partly in a first N- epitaxial layer and partly in a second N- epitaxial layer; the MOS is located above the emitter region. The bipolar is thus a completely buried active structure. In the horizontal MOS version, in a N- epitaxial layer there are two P+ regions, the first, which constitutes the base of the bipolar transistor, receives the N+ emitter region of the same transistor; the second receives two N+ regions which constitute the MOS source and drain regions, respectively; the front of the chip is provided with metal plating to ensure the connection between the MOS drain and the bipolar emitter contacts.
    Type: Grant
    Filed: June 2, 1994
    Date of Patent: September 21, 1999
    Assignee: SGS-Thomson Microelectronics, S.r.l.
    Inventors: Ferruccio Frisina, Giuseppe Ferla