Abstract: Capacitive coupling between neighboring conductive lines of the semiconductor device is reduced by applying an alternating magnetic field in a direction perpendicular to the plane of the conductive lines.

Abstract: A HIGFET having a gate pad situated over a non conducting portion of the channel layer of the heterostructure wafer. The method of producing this device involves application of a very thin layer of gate metal on the wafer to protect the wafer surface during further processing. A photoresist coating is formed over the active area of the channel layer of the FET. An ion isolation implantation is applied to the wafer resulting in a non conducting portion of the channel layer that is not covered by the photoresist layer. The photoresist layer is removed and a thick layer of gate metal is applied on the thin layer of gate metal. The gate layers are fashioned into a pad over the non conducting portion of the channel layer and at least one finger over the conducting portion of the channel layer, resulting in the gate having minimized parasitic gate capacitance.

Abstract: A process for fabricating memory cells of a read-only memory (ROM) device is disclosed. First, a gate oxide layer, a first polysilicon layer, and a first silicide layer are formed subsequently on the surface of a silicon substrate. The layers are patterned to form parallel strip-shaped configurations extending along a first direction on the surface of the silicon substrate. Next, impurities are implanted into the surface of the substrate in the areas between the strip-shaped configurations thereby constituting buried bit lines of the memory cells. Sidewall spacers are then formed on the sidewalls of the strip-shaped configurations. A second silicide layer is then formed over the exposed surface of the buried bit lines in a self-aligned process, thereby improving the electrical conductivity of the buried bit lines. After that, the portions of the second silicide layer and the first polysilicon layer covering the coding region of the memory cells are removed.

Abstract: A method for making stable arsenic doped semiconductor devices (11,53,56) using dry etching techniques includes forming a polycrystalline semiconductor layer (29) on a upper surface of a semiconductor substrate (12), and patterning the polycrystalline semiconductor layer (29) using a dry etch process such as a plasma etch process. The semiconductor substrate (12) is then exposed to an elevated temperature to substantially reduce any defects contiguous with the upper surface of semiconductor substrate (12) resulting from the dry etch process. Arsenic is then incorporated into the semiconductor substrate (12) to form N+ regions (44). Surface sensitive devices such as MOSFET devices (53,56) are then formed on or within the semiconductor substrate (12).

Abstract: A semiconductor component is formed in a semiconductor wafer, of a first conductivity type. The semiconductor component includes a plurality of first regions, of a second conductivity type, in a top surface of the wafer and coated with a first metallization layer. The semiconductor component further includes a second region, of the second conductivity type, and a third region, of the first conductivity type, each formed in the top surface of the wafer. A second metallization layer coats the second and third regions. A fourth region, of the first conductivity type, is formed in a bottom surface of the semiconductor wafer and opposes the first and second regions. A fifth region, of the second conductivity type, is also formed in the bottom surface and opposes the third region. A rear surface metallization covers the bottom surface of the semiconductor wafer.

Abstract: A thin film transistor and method for forming the same are disclosed. The transistor comprises a gate conductor (14) and a gate insulator (16). A semiconductor channel layer (18) is formed adjacent the gate insulator (16). A mask block (22) is formed covering a channel region (30) in the channel layer (18). A source region (26) and a drain region (28) are formed in the channel layer (18) adjacent opposite ends of the mask block (22). Conductive bodies (32) and (34) are formed in contact with source region (26) and drain region (28), respectively. Electric contacts (42) and (44) are then formed in contact with conductive bodies (32) and (34), respectively.

Abstract: A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.

Abstract: The present invention improves a current--voltage characteristic by perfectly eliminating defects in the polycrystal silicon layer of TFT by hydrogenation. In the first process, hydrogen is doped into the polycrystal silicon layer 16 of TFT 1 by the hydrogen plasma doping method to eliminate a greater part of the defects in the polycrystal silicon layer 16. Thereafter, in the second process, after an amorphous silicon nitride film 23 including hydrogen is formed on the polycrystal silicon layer 16 or on the stopper layer 17 provided on the polycrystal silicon layer 16, hydrogen is released from the amorphous silicon nitride film 23 including hydrogen by the annealing process and such released hydrogen is then diffused into the polycrystal silicon layer 16 in order to eliminate remaining defects in the polycrystal silicon layer 16.

Abstract: An electron emitting device causes electron emission by a current supply in a coarse resistor film. The coarse thin resistor film is composed at least of a coarse thin silicon film.

Abstract: A vertical field effect transistor (700) and fabrication method with buried gates (704) having gate sidewall crystal orientation the same as the substrate surface and a low index substrate crystal orientation without tilt to a higher index direction. The gate (704) may have modulated doping along the channel (706), and the drain (708) may have a lighter doping level than the channel which may be accomplished by an epitaxial overgrowth of the gates (704) to form the channels (706).

Abstract: A high voltage alternating current rectifier circuit for an NMOS or CMOS transistor environment in which four N-channel transistors are simultaneously fabricated distant from a utilization circuit, such as one or more EEPROM transistors. The four N-channel transistors have lightly doped sources and drains formed prior to the time gates are formed, the doping concentrations and the thickness of oxide overlying the gates selected to establish breakdown voltages exceeding 20 volt peaks. This allows an input spiral antenna or other inductor to be used for coupling radio frequency energy and signals from a remote source to a chip having a utilization circuit employing the rectifier circuit as a source of power.

Abstract: A CMOS-technology, DRAM integrated circuit includes paired P-type and N-type wells in a substrate, which wells are fabricated using a self-aligning methodology. Similarly, FET's of the DRAM circuit are fabricated in the wells of the substrate using a self-aligning methodology to provide FET's of opposite polarity in a DRAM which may have paired memory cells and dummy cells for symmetry of circuitry. The DRAM includes a multitude of annular multi-plate capacitor structures formed atop the FET's of the substrate, and plural layers of insulative dielectric with embedded bit and word traces providing for connection of the multitude of memory cells of the DRAM to external circuitry.

Abstract: The present invention provides an apparatus for semiconductor processing in which the reactor chamber and the vacuum conduit means connected to the chamber are coated with a film of halogenated polymer material having a low vapor pressure and a low sticking coefficient. Preferred materials include low molecular weight polyfluoroethylene polymers such as polytetrafluoroethylene and polychlorotrifluoro-ethylene. A method is provided to prevent contaminant buildup on coated surfaces of semiconductor processing chambers and vacuum conduit means connected thereto during processing of a workpiece.

Abstract: Region forming steps or interconnect-forming steps through which low voltage CMOS devices are formed in a semiconductor wafer are also employed to simultaneously form one or more regions or layers at selected sites of a substrate where high voltage devices are to be formed. Such selective modification of an already existing mask set designed for low voltage CMOS typography allows additional doping of the substrate or provision of further overlay material to accommodate the effects of high voltage operation of selected areas of the water and thereby effectively performs precursor tailoring or modification of those portions of the wafer where a high voltage condition will be encountered.

Abstract: Low threshold voltage MOS devices having buried electrodes are disclosed herein. Such devices have source and drain regions which include tip regions and plug regions. The buried electrodes have bottom boundaries located above the bottoms of the plug regions. The buried electrode has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. The exact dopant concentrations and locations of the buried electrodes should be provided such that punch through is avoided in MOS devices.

Abstract: A flash memory EEPROM transistor is formed on a surface of a semiconductor substrate. In portions of the substrate, at the surface thereof, a doped source region and a doped drain region are formed with a channel region therebetween. A tunnel silicon oxide dielectric layer is formed over the semiconductor substrate aside from the source region. Above the source region is formed a gate oxide layer which is thicker than the tunnel oxide layer. Above a portion of the tunnel oxide dielectric layer, over the channel region and above a portion of the gate oxide layer is formed a stacked-gate structure for the transistor comprising a floating gate layer, an interelectrode dielectric layer, and a control gate layer. The source region is located on one side of the stacked gate structure with one edge of the source region overlapping the gate structure. The drain region which is located on the other side of the stacked gate structure with one edge thereof overlapping the gate structure.

Abstract: A bridging member extending across a cavity in a semiconductor substrate (e.g. single crystal silicon) has successive layers--a masking layer, an electrically conductive layer (e.g. polysilicon) and an insulating layer (e.g. SiO.sub.2). A first electrical contact (e.g. gold coated with ruthenium) extends on the insulating layer in a direction perpendicular to the extension of the bridging member across the cavity. A pair of bumps (e.g. gold) are on the insulating layer each between the contact and one of the cavity ends. Initially the bridging member and then the contact and the bumps are formed on the substrate and then the cavity is etched in the substrate through holes in the bridging member. A pair of second electrical contacts (e.g. gold coated with ruthenium) are on the surface of an insulating substrate (e.g. pyrex glass) adjacent the semiconductor substrate. The two substrates are bonded after the contacts are cleaned.

Abstract: A method for fabricating a metal oxide semiconductor field effect transistor, capable of achieving a reduction in topology by forming a trench on a silicon substrate by use of a temporary field oxide film and forming a gate electrode in the trench and capable of eliminating occurrence of a spiking phenomenon due to a metal wiring being in direct contact with the silicon substrate by forming a silicide film on a source and a drain, and capable of obtaining an increased contact margin of the metal wiring by overlapping the silicide film with a field oxide film formed on the silicon substrate.

Abstract: A semiconductor device includes a semiconductor substrate having a main surface, and a laminated structure. The laminated structure is made up of a nonmonocrystalline silicon layer and a layer of refractory metal or refractory metal silicide, formed on the nonmonocrystalline silicon layer, and formed on the main surface of the semiconductor substrate. The resistivity of the nonmonocrystalline silicon layer is set at less than substantially 1.times.10.sup.-2 .OMEGA..multidot.cm by doping an impurity thereinto at the time of deposition of the nonmonocrystalline silicon layer.

Abstract: A method of fabricating a semiconductor device including forming a Schottky contact on the surface of a substrate by patterning a layer of nickel to define a contact and annealing the nickel below approximately 600.degree. C. A trench is etched around the Schottky contact utilizing the Schottky contact as an etch mask and inert ions are implanted in the trench to form a damage region. The trench is passivated with a dielectric layer. An ohmic contact can be formed on the reverse side of the substrate prior to formation of the Schottky contact.