Abstract: A method for fabricating a self-aligned thin-film transistor, in accordance with the present invention, first involves forming a gate electrode on an insulating layer. Next, a gate dielectric layer is formed to enclose the gate electrode. Subsequently, a semiconductor layer, a conducting layer, and a first dielectric layer are formed to cover the substrate and the gate dielectric layer. Afterwards, a chemical mechanical polishing process is applied to subsequently polish the first dielectric layer and the conducting layer to expose the semiconductor layer above the gate electrode. Therefore, the conducting layer disposed at opposite sides of the gate electrode is self-aligned to act as the source/drain regions of the fabricated TFT device.

Abstract: A source cell having reduced area and reduced polysilicon window width requirements for use as the source region in a DMOS transistor is disclosed, comprising: a source region of semiconductor material disposed on a semiconductor substrate; a plurality of backgate contact segments of predetermined size and separated by predetermined distances; and a plurality of source contact windows alternating with the backgate contact segments so that a narrow source contact region is formed of alternating source contact and backgate contact material. A DMOS transistor embodying the source region including the backgate contact segments and windowed source contacting regions of the invention is disclosed. An integrated circuit providing an array of DMOS transistors having the improved source regions of the invention is disclosed.Other devices, systems and methods are also disclosed.

Abstract: A method of processing wafers for power devices in which the wafer has a desired thickness less than the thickness necessary to provide mechanical support. A silicon wafer of the desired thickness is bonded to a carrier wafer until most, if not all, of the processing steps are completed, after which the silicon wafer is separated from its carrier wafer. The carrier wafer may serve as a diffusion source, and the areas of the bonding of the silicon wafer to the carrier wafer may be selected consistent with the devices or groups of devices to be formed by the separation of the two wafers. The carrier wafer may by bonded to the device wafer over nearly the full surface area and the carrier wafer remain a part of the final device.

Abstract: An integrated structure active clamp for the protection of a power device against overvoltages includes a plurality of serially connected diodes, each having a first and a second electrode, obtained in a lightly doped epitaxial layer of a first conductivity type in which the power device is also obtained; a first diode of said plurality of diodes has the first electrode connected to a gate layer of the power device and the second electrode connected to the second electrode of at least one second diode of the plurality whose first electrode is connected to a drain region of the power device; said first diode has its first electrode comprising a heavily doped contact region of the first conductivity type included in a lightly doped epitaxial layer region of the first conductivity type which is isolated from said lightly doped epitaxial layer by a buried region of a second conductivity type and by a heavily doped annular region of the second conductivity type extending from a semiconductor top surface to said bu

Abstract: A layer of amorphous silicon covers the top surface of a semiconductor wafer to act as a moisture and contaminant barrier and to prevent the formation of aluminum hillocks on the aluminum bonding pads for the source and gate electrodes of a power MOSFET or other power semiconductor device. The amorphous silicon is easily penetrated by wire bonding apparatus used to make wire bonds to the conductor pads beneath the amorphous silicon.

Abstract: An apparatus for depositing particles onto a wafer comprises a particle generating means; particle size controlling means connected to an output terminal of the particle generating means; a first transmitting tube connected to an output of the particle size controlling means; second and a third transmitting means connected to an output terminal of the first transmitting tube; first counting means connected to an output terminal of the second transmitting tube; particle depositing means connected to an output terminal of the third transmitting means; second counting means connected to the particle depositing means; and a power supplier connected to the particle depositing means. The apparatus and a method for depositing the particles onto the wafer provide a wafer on which particles of known size and kind are deposited. Also, the particles of a different kind and size are deposited on the same wafer.

Abstract: A method of manufacturing an inverse-T shaped transistor is disclosed including the steps of sequentially forming a first insulating film and a second insulating film on a semiconductor substrate of a first conductivity type, sequentially removing a portion of the second insulating film and a portion of the first insulating film, to thereby form an inverse-T shaped void region therein, filling the inverse-T shaped void region with a conductor to form a gate electrode having a central body portion and wings, removing the remaining first and second insulating films, and implanting impurity ions of a second conductivity type, to thereby form low concentration impurity regions in substrate areas below both wings of the gate electrode and, simultaneously, to form high concentration impurity regions in substrate areas not covered by the gate electrode.

Abstract: In a method of manufacturing a thin film transistor, a light shielding gate electrode is formed on a transparent insulating substrate. On the substrate including the gate electrode are laminated a gate insulating film, a semiconductor film, a protection insulating film, and a photoresist film. The photoresist film is patterned in alignment with the gate electrode. The protection insulating film is isotropically etched using the patterned photoresist film as a mask to have inclined portions. After the surface of the semiconductor film is rinsed to remove a natural oxide film, a metal film is deposited to form a metal silicide layer in alignment with the patterned protection insulating film. The metal film is patterned in such a manner that the metal portions are separated from the patterned protection insulating film.

Abstract: A method of manufacturing a lightly doped drain MOS transistor having the double shallow junction is disclosed including the steps of forming a gate and a gate insulating film on a semiconductor substrate of a first conductivity type, sequentially; forming, on the top and sidewalls of the gate, on side edges of the gate insulating layer, and on the substrate, an insulating film including two kinds of impurities whose diffusivity and conductivity type are different from each other forming a cap insulating film on the insulating film; performing the heat treatment process thereby to form impurity regions of a second conductivity type and impurity regions of the first conductivity type surrounding the impurity regions of the second conductivity type, on both sides of the gate in the substrate; etching the insulating film and the cap insulating film thereby to form sidewall spacers on both sides of the gate; and ion-implanting an impurity of the second conductivity type in the substrate thereby to form impurity r

Abstract: A fabricating method of a semiconductor device includes preparing a compound semiconductor substrate including an active layer epitaxially grown on the substrate, forming a test element group FET (TEGFET) having a characteristic value on the compound semiconductor substrate and measuring a characteristic value of the TEGFET, forming an FET having a characteristic value on the compound semiconductor substrate, measuring the characteristic value of the FET, obtaining a variation of the carrier concentration of the active layer of the FET relative to a required value by comparing the measured characteristic value of the FET with reference data obtained from the TEGFET and correcting the variation by implanting ions under conditions that correct the variation. Therefore, after forming a gate electrode of the FET, the carrier concentration of the active layer of the FET is corrected, so the the yield of the device is improved.

Abstract: A gate power MOSFET on substrate (20) has a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. Layer (430) on surface (28) patterns areas (446) as stripes or a matrix, and protected areas. Undercut sidewalls (444) of thickness (452), with protruding rims (447), contact the sides of layer (434'). Trench (450) in areas (446) has silicon sidewalls aligned to oxide sidewall (447) and extending depthwise through P-body layer (26) to depth (456). Gate oxide (460) is formed on the trench walls and gate polysilicon (462) refills trench (450) to a level (464) near surface (28) demarcated by the undercut sidewall rims (447). Oxide (468) between spacers (444) covers polysilicon (462). Removing layer (430) exposes surface (28') between the sidewalls (444). Source layer (72) is doped atop the body layer (26') and then trenched to form trench (80) having sidewalls aligned to inner side faces of sidewalls (444).

Abstract: A method for coding a semiconductor ROM. The method includes the steps of: carrying out a local oxidizing process on a semiconductor substrate to separate the substrate into field regions and active regions; forming a gate insulating layer; depositing a polysilicon layer; and patterning the structure by applying a photo etching process to form a polysilicon gate only on a portion where an enhancement transistor is to be formed. Further, impurity ions are ion-implanted into a source/drain region by utilizing a gate of an enhancement transistor as a mask, and simultaneously, impurity ions are ion-implanted into a region where a drain, a gate and a source of a depletion transistor are to be formed, whereby n type impurity layers of the same depth are formed to interconnect them.

Abstract: The apparatus includes a gas diffuser plate having an integral heat pipe for accurately controlling the temperature of the diffuser plate during CVD processing to prevent unwanted tungsten (or other material) deposition on the diffuser plate. The apparatus is also useful as an RF plasma cleaning device in which the diffuser plate acts as an RF electrode, the heat pipe tube acts as an RF input lead, and the apparatus further includes a connector to an RF power source. Additionally, in combination, the heat pipe-cooled gas diffuser plate and RF electrode may be used advantageously in plasma enhanced chemical vapor deposition (PECVD).

Abstract: A method of fabricating a charge coupled device (CCD) using etching processes rather than high temperature oxidation to form field regions. The method leaves in place at least one of a first insulation film and a second insulation film that have been formed over the surface of a first conductivity-type semiconductor substrate while (1) injecting channel stop ions into selected regions of a well region to thereby form separation regions between what will become photodiode regions corresponding to pixels of the CCD, while (2) forming a photodiode region for each pixel of said CCD, and while (3) forming charge transfer regions for selectively outputting charges formed at the photodiode regions. The method provides for improved operational performance of the CCD by preventing contamination of the substrate, photodiode regions and charge transfer regions during formation of the CCD.

Abstract: A hybrid (composite) integrated circuit element comprises a substrate, a thin film type integrated circuit formed on a substrate through a thin film process, and a lamination type passive circuit element such as a capacitor, inductor, resitance and a combination thereof formed on the integrated circuit. During the firing of passive circuit element in a hydrogen atmosphere, the semiconductor layer which constitutes the integrated circuit is also heat annealed. Various substrates can be used as the substrate, for example, quartz, ceramic and a cheap semiconductor substrate which has not been treated with a mirror-grinding by the use of a glass layer.

Abstract: A method of manufacturing a semiconductor device with a buried channel field effect transistor, comprising the formation of a stack of layers on a substrate with an active semiconductor layer having a non-zero aluminium (Al) content, a semiconductor cap layer without aluminium (Al), a masking layer provided with a gate opening; a first selective etching step with a first etching compound containing fluorine (F) in the cap layer down to the upper surface of the active layer, whereon a stopper layer of aluminium fluoride (AlF.sub.3) is formed automatically; then elimination of the stopper layer; a second, non-selective etching step in the active layer with a second etchant until a first, central gate recess is completed; a third, selective etching process with the first etchant in the cap layer, which takes place laterally for forming the flanks of a second recess whose bottom is the upper surface.

Abstract: An implant mask (14) and an etch mask (16) are utilized in forming a silicon carbide JFET (10). A source opening (17) and a drain opening (18) are formed in the masks (14,16). The etch mask (16) is removed, and a source area (19) and a drain area 21 are implanted through the openings (17,18) and source and drain contact (23, 24) are formed. A protective layer (26) is used to form source and drain contacts (23,24). A gate contact (27) is utilized to ensure the gate (28) is self-aligned to the gate contact (27).

Abstract: A fully self-aligned, charge coupled device (CCD) comprises a semiconductor substrate having implanted barrier and/or storage regions, an insulating dielectric layer disposed over the substrate, a first layer of closely spaced electrodes in self-alignment with at least one implant underneath the first electrodes, a second layer of closely spaced electrodes in self-alignment with the first electrodes and with at least one implant underneath the second electrodes also in self-alignment with the first electrodes.

Abstract: A trenched DMOS transistor is fabricated using seven masking steps. One masking step defines both the P+ deep body regions and the active portions of the transistor which are masked using a LOCOS process. A second masking step defines the insulating oxide in the termination region. The insulating (oxide) layer in the termination region is thus thicker than in the active region of the transistor, thereby improving process control and reducing substrate contamination during processing. Additionally, the thicker field oxide in the termination region improves electric field distribution so that avalanche breakdown occurs in the cell (active) region rather than in the termination region, and thus breakdown voltage behavior is more stable and predictable.

Abstract: A component integration structure (10) for a microwave system includes a silicon substrate (12) having a resistivity greater than about 2,000 ohm-cm. A first die (14) is disposed on the silicon substrate, and a first passive element (20) is disposed on the silicon substrate and electrically coupled to the first die. In addition, a second passive element (22) and a second die (16) may be disposed on the silicon substrate. The second passive element is electrically coupled to the first passive element. An integration method sorts each of a plurality of active devices for placement on either the first die or the substrate depending on which of two different processing flows has the most favorable characteristics for fabricating each particular device.