Patents Examined by Brian Sircus
  • Patent number: 7173350
    Abstract: In a load drive control system containing a control apparatus and a drive apparatus which drives a load in accordance with a drive control signal supplied from the control apparatus, a single signal produced from the control apparatus serves both as the drive control signal and as a power supply enabling control signal for the drive apparatus, without the need to provide an internal DC power supply in the drive apparatus. A switching element in the drive apparatus is controlled to apply a supply voltage from a drive power source to circuits in the drive apparatus only while the drive control signal is being supplied from the control apparatus.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: February 6, 2007
    Assignee: Denso Corporation
    Inventors: Yosuke Okitsu, Junji Sugiura
  • Patent number: 7173800
    Abstract: In a method and a detector (7) for time-optimum reception of protection commands in a remote tripping device, at least two detector elements (1, 2) are operated, which are all designed for a signal at the same frequency but for different transmission times. Where at least one of these detector elements (1, 2) detects the presence of the signal, the signal is regarded as having been detected.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: February 6, 2007
    Assignee: ABB Schweiz AG
    Inventors: Hermann Spiess, Hans Benninger
  • Patent number: 7170194
    Abstract: A system for supplying additional power to a module having an internal power supply, the system comprising: a module having an associated power supply, the power supply not being designed to accommodate power sharing; at least one load associated with the module, the load receiving power from the power supply; a variable current limited power source connected to the module supplying additional power to the at least one load; and a controller; whereby the variable current limited power supply is responsive to an output of the controller to vary the current limit of the variable current limited power supply.
    Type: Grant
    Filed: January 26, 2004
    Date of Patent: January 30, 2007
    Assignee: PowerDsine, Ltd.
    Inventors: Dror Korcharz, Yair Darshan, Ilan Atias, David Pincu
  • Patent number: 7170730
    Abstract: A method for isolating suites includes the steps of isolating the suites when an alarm is initiated, setting a timer during isolation creating a window of time to clear a short circuit, clearing said short circuit, removing isolation from the suites as the timer reaches completion, determining if there is a short circuit in each of the suites, and isolating suites that have a short circuit.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: January 30, 2007
    Assignee: GE Security, Inc.
    Inventor: Peter Galgay
  • Patent number: 7170734
    Abstract: The invention relates to an air ionization device comprising a high voltage line which can be connected to an AC voltage power source and point electrodes which are coupled capacitively to the high voltage line for generating a corona discharge.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: January 30, 2007
    Assignee: Haug GmbH & Co. KG
    Inventor: Christof Muz
  • Patent number: 7170727
    Abstract: An input pad for a differential current input to an integrated circuit contains a switchable and tunable input impedance. The input pad also contains ESD protection and common mode rejection while maintaining low capacitance. The common mode rejection comprises two resistors that combine to remove the common mode current from the two input lines, produce a reference current, and drive two output transistors that cancel the common mode current from the outputs.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: January 30, 2007
    Assignee: LSI Logic Corporation
    Inventor: Kenneth Richardson
  • Patent number: 7170732
    Abstract: A surge current delay time period is added to a current limit delay time period in order to permit a longer time for a possibly temporary larger-than-steady-state electrical current, such as for a start-up power requirement. A system is described for permitting a legitimate surge current by distinguishing true over-current fault conditions from temporary surges in terms of high current duration time.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: January 30, 2007
    Assignee: Micrel Incorporated
    Inventors: David Andersen, Thruston Awalt
  • Patent number: 7170196
    Abstract: An electrical power feed for a submarine system and a method of supplying electrical power to the submarine system in which a plurality of power converters are used for feeding electrical power into the submarine system. A plurality of control circuits are each connected to at least one of the power converters and control the level of power output by the respective power converter(s) to which it is connected. Each power converter is connected to only one control circuit and at least some of the power converters operate independently from each other.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: January 30, 2007
    Assignee: Alcatel
    Inventors: Tony Farrar, Simon Timothy Perry
  • Patent number: 7170262
    Abstract: A variable frequency power system with a power source having a rotating output and a speed control to regulate rotational speed of the rotating output. A generator coupled to and driven by the rotating output of the power source, whereby the speed control of the power source directly controls output power frequency of the generator due to control of rotational frequency of the rotating output. A voltage regulator connected between the generator and the motor regulates output voltage from the generator to the electrical motor load. A system controller controls output power frequency of the generator. The system controller interfaces with the speed control of the power source and configured to monitor generator output and operational conditions of the electrical motor load. The system controller adjusts the speed control based on generator output and operational conditions of the electrical motor load.
    Type: Grant
    Filed: December 24, 2003
    Date of Patent: January 30, 2007
    Assignee: Foundation Enterprises Ltd.
    Inventor: Dana Robert Pettigrew
  • Patent number: 7170733
    Abstract: An electric pole (1) for a low-voltage automatic power circuit breaker, comprising: a fixed contact (2) and a movable contact (3) that can be coupled/uncoupled with respect to each other, said fixed contact being electrically connected to a phase conductor, and a sensing unit that comprises a first section suitable to accommodate a current sensor associated with the phase conductor, the current sensor generating sensing signals that are indicative of the intensity of the electrical current that flows through the phase conductor, the sensing unit being electrically connected to a protection unit of the automatic power circuit breaker, the protection unit being suitable to receive the sensing signals and to generate control signals for actuation means operatively connected to said movable contact, and comprising at least one input section (14) provided with one or more electrical input terminals (141); whose particularity consists of the fact that the sensing unit comprises a second section (20), which is rigid
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: January 30, 2007
    Assignee: ABB Services S.r.l.
    Inventors: Severino Colombo, Osvaldo Carrara
  • Patent number: 7170729
    Abstract: A semiconductor integrated circuit of the present invention includes, between a power line 1 and a ground line 2, an NMIS transistor 3 capable of supplying fixed signals with low and high levels to the outside, an NMIS transistor 6 having a source connected to a gate of the NMIS transistor 3, a PMIS transistor 7 having a drain connected to a gate of the NMIS transistor 6, and an ESD protection power clamp circuit 14. If a surge is applied to the power line 1, the ESD protection power clamp circuit 14 is clamped to pass the surge to the ground line. While the surge is passed, the potential of the power line 1 rises to turn on the three transistors 3, 6, and 7. At this time, the NMIS transistor 6 and the PMIS transistor 7 can reduce the gate potential of the NMIS transistor 3 lower than the potential of the power line 1.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: January 30, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hiroaki Yabu
  • Patent number: 7167349
    Abstract: An earth leakage breaker includes a main contact, a switch mechanism, an operating handle, a leakage tripping device and an over-current tripping device having an earth-leakage-detection circuit disposed in a main-body case. A power-supply line connects the earth-leakage-detection circuit to the main circuit for supplying voltage between phases of the main circuit as a power source of the earth-leakage-detection circuit. Further, a test switch is provided for turning on and off a power-supply circuit of the power-supply line connected to the earth-leakage-detection circuit, and an operation of the test switch is linked to an ON/OFF operation of the switch mechanism.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: January 23, 2007
    Assignee: Fuji Electric FA Components & Systems Co., Ltd.
    Inventors: Hisanobu Asano, Koji Asakawa, Yasuhiro Takahashi
  • Patent number: 7166930
    Abstract: A UPS includes a UPS circuit that selectively supplies power to a load from first and second power sources, and a display (e.g., an LCD) coupled to the UPS circuit and operative to provide display graphical and/or textual information pertaining thereto. The UPS apparatus further comprises a backlight circuit coupled to the UPS circuit and operative to provide different backlightings of the display responsive to respective states of the UPS circuit.
    Type: Grant
    Filed: July 21, 2003
    Date of Patent: January 23, 2007
    Assignee: Eaton Power Quality Corporation
    Inventor: Brian R. Young
  • Patent number: 7167348
    Abstract: A Digital Programmable Motor Overload Protector includes a base module and a detachable, removable user interface module interfaced through a serial communications link. The base module provides motor overload analysis through a programmable Digital Signal Processor (DSP) which digitizes real time motor operating conditions, comparing stored user trip and alarm levels against these conditions, communicating the results to the detachable user interface and a multi-drop communications link using the industry standard MODBUS RTU protocol to a facility's automation system. Motor operating conditions, user settings, override conditions, pass events, and resettable parameters are available through the password protected removable user interface module or the multi-drop communications interface.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: January 23, 2007
    Assignee: AMT Capital, Ltd.
    Inventors: William H. Knox, Jr., William E. Calligan, Jr.
  • Patent number: 7164566
    Abstract: Methods and apparatus are provided an electrostatic discharge (ESD) protection device having a first terminal and a second terminal. The ESD protection device comprises a vertical transistor having a collector coupled to the first terminal, a base, and an emitter coupled to the second terminal. A zener diode has a first terminal coupled to the first terminal of the ESD protection device and a second terminal coupled to the base of the vertical transistor. Subsurface current paths are provided to redistribute current from a surface of the vertical transistor in an ESD event. The method comprises generating an ionization current when a zener diode breaks down during an ESD event. The ionization current density from a surface zener diode region is reduced. The ionization current enables a transistor to dissipate the ESD event.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: January 16, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hongzhong Xu, Beth A. Baumert, Richard T. Ida
  • Patent number: 7164214
    Abstract: A programmable uninterruptible power supply for coupling battery powered systems associated with a mobile site, such as a vehicle, to the primary electrical system of the mobile site operates to selectively couple the battery powered systems to the electrical system of the mobile site and to a secondary, or back-up battery separate from the primary battery associated with the electrical system of the mobile site. Various system control functions are performed, including reverse battery protection, over voltage and under voltage protection, battery drain protection, battery charging detection, reverse current detection and uninterruptible power switching. For detected adverse operating conditions, the load is disconnected from the electrical system of the mobile site and the back-up battery is used to operate the battery powered systems which are to be protected from such adverse operating conditions.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: January 16, 2007
    Inventors: Dean Eisenberger, Jeff Legg
  • Patent number: 7164563
    Abstract: A resettable circuit interrupting device such as a GFCI that, when reverse wired during installation, will trip and prevent power being applied to the load side of the GFCI when powered up. A current limiting circuit is connected between the phase and a ground terminal on the line side of the differential transformer of the GFCI. When the GFCI is connected correctly, the current through the current limiting circuit will have no significant effect on the GFCI, and it will operate normally. When, however, the line conductors are connected to the load terminals of the GFCI and the load conductors are connected to the line terminals of the GFCI, the current through the current limiting circuit will appear as a ground fault and cause the GFCI to trip.
    Type: Grant
    Filed: January 22, 2004
    Date of Patent: January 16, 2007
    Assignee: Leviton Manufacturing Co., Inc.
    Inventors: David Y. Chan, Bernard J. Gershen
  • Patent number: 7164562
    Abstract: A protection configuration for converter means which comprise a plurality of controllable switches, the protection configuration comprising a protection circuit coupled to the alternating voltage side of the converter means, which protection circuit comprises at least one protective switch configured to short-circuit the alternating voltage side of the converter means, wherein the protection configuration, in predetermined failure situations, is configured to close the protective switch and thus to short-circuit the alternating voltage side of the converter means. After the failure situation has cleared up, the protection configuration is configured to short-circuit the alternating voltage side of the converter means by means of the controllable switches to enhance commutation of the protective switch.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: January 16, 2007
    Assignee: ABB OY
    Inventor: Reijo Virtanen
  • Patent number: 7164565
    Abstract: An ESD protection circuit for an integrated circuit includes an ESD clamping circuit, an ESD triggering circuit, and an ESD disabling circuit. The ESD clamping circuit is operably coupled to a first power pin of the integrated circuit and a second power pin of the integrated circuit. The ESD triggering circuit is operably coupled to the ESD clamping circuit, wherein, when enabled and when sensing an ESD event, the ESD triggering circuit provides a clamping signal to the ESD clamping circuit such that the ESD clamping circuit provides a low impedance path between the first and second power pins. The ESD disabling circuit is operably coupled to disable the ESD triggering circuit when the integrated circuit is in a normal operating mode.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: January 16, 2007
    Assignee: Sigmatel, Inc.
    Inventor: Fujio Takeda
  • Patent number: 7164567
    Abstract: A device for ESD protection of a high frequency circuit (1) of a semiconductor device comprises first (3) and second (4) p-type and first (6) and second (5) n-type JFET's, wherein the first p-type JFET (3) is connected with its gate to a high voltage source, its source to an input/output pad (2) of the semiconductor device, and its drain to the source of the first n-type JFET (6), the second p-type JFET (4) is connected with its gate to the high voltage source, its source to the drain of the second n-type JFET (5), and its drain to an input/output terminal of the circuit (1), the first n-type JFET transistor (6) is connected with its gate to ground (GND), and its drain to the input/output terminal, and the second n-type JFET transistor (5) is connected with its gate to ground (GND), and its source to the input/output pad (2).
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: January 16, 2007
    Assignee: Infineon Technologies AG
    Inventors: Andrej Litwin, Ola Pettersson