Abstract: A vertical field effect transistor according to an embodiment of the present invention does not require a spacer and, accordingly, remarkably alleviates the problem that electric charge is scattered at an interface, thereby having excellent electrical characteristics. The vertical field effect transistor includes a substrate, a source electrode positioned on the substrate, an active layer positioned on the source electrode and having vertically grown crystal grains, a drain electrode positioned on the active layer to be spaced by the active layer away from the source electrode, a gate insulating layer positioned on a lateral surface of the active layer, and a gate electrode positioned on the gate insulating layer.

Abstract: A substrate includes a dielectric structure, a conductive layer, a first hole and a second hole. The conductive layer is stacked on the dielectric structure. The first hole extends from a top surface of the conductive layer and exposes the dielectric structure. The second hole is spaced apart from the first hole, extends from the top surface of the conductive layer and exposes the dielectric structure. A first depth of the first hole is substantially equal to a second depth of the second hole. An elevation of a topmost end of the first hole is different from an elevation of a topmost end of the second hole.

Abstract: A light-emitting device includes a semiconductor substrate, an epitaxial structure that has a first surface facing the semiconductor substrate and a second surface opposite to the first surface, and a transparent bonding structure that is disposed between the first surface and the semiconductor substrate. The transparent bonding structure has a first bonding surface facing the first surface of the epitaxial structure and a second bonding surface opposite to the first bonding surface, and has a slit extending from the first bonding surface toward the second bonding surface and terminating at a position that is a distance away from the second bonding surface. A method for manufacturing a light-emitting device is also provided.

Abstract: A method of controlling the thickness of a layer of material applied to a surface, where the surface has one or more bodies of another material disposed therein, the another material being significantly harder than the first mentioned material, the one or more bodies of another material being disposed on the surface before the layer of material is applied to the surface, the layer of material when applied to the surface having a sufficient thickness to cover the one or more bodies of the another material, the layer of material then being mechanically reduced in thickness, such as by polishing, to expose at least a portion of the one or more bodies of the another material.

Abstract: A method for manufacturing a memory device includes forming a dielectric layer over a substrate, in which the substrate has a cell region and a logic region adjacent to the cell region. A bottom electrode, a memory layer, and a top electrode are formed in sequence over the cell region of the substrate. A first spacer is formed extending upwards from the bottom electrode. A second spacer is formed extending upwards from the dielectric layer and lining with sidewalls of the bottom electrode and the first spacer.

Abstract: A semiconductor device includes a substrate and a well region both having a first conductivity type, a trench in the substrate and directly above the well region, a first trench gate and a second trench gate disposed in the trench and laterally separated from each other, a dielectric isolation portion disposed in the trench and between the first and second trench gates, and a dielectric liner in the trench and under bottom surfaces of the first and second trench gates. A middle region of a bottom surface of the dielectric isolation portion protrudes downward and is lower than two side regions of the bottom surface of the dielectric isolation portion. Below a horizontal line of the bottom surfaces of the first and second trench gates, the thickness of the dielectric isolation portion is greater than the thickness of the dielectric liner.

Abstract: A method for forming a semiconductor device structure includes forming a layer stack comprising alternating sacrificial layers of a first semiconductor material and channel layers of a second semiconductor material. The method includes forming over the layer stack a plurality of parallel and regularly spaced core lines and forming spacer lines on side surfaces of the core lines. The method includes forming first trenches extending through the layer stack by etching the layer stack while using the core lines and the spacer lines as an etch mask and forming insulating walls in the first trenches and in the gaps by filling the first trenches and the gaps with insulating wall material. The method also includes forming second trenches extending through the layer stack by etching the layer stack while using the spacer lines and the insulating walls as an etch mask, thereby forming a plurality of pairs of fin structures.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a diffusion break opening on the backside and filling with a diffusion break material to serve as a planarization stop. In some embodiments, a single diffusion break opening is formed. In other embodiments, a mixed diffusion break opening is formed.

Abstract: An IC driver includes a cascode arrangement of first-type transistors coupled in series with a cascode arrangement of second-type transistors different from the first-type transistors. Each cascode arrangement includes an active area extending in a first direction, gate structures extending perpendicular to the first direction and overlying the active area at locations corresponding to the transistors of the cascode arrangement, first through fourth metal segments extending in the first direction in a first metal layer of the IC, first and second vias electrically coupling respective first and second gate structures to the first and second metal segments, a third via electrically coupling a source terminal of the cascode arrangement to the third metal segment, and a fourth via electrically coupling a drain terminal of the cascode arrangement to the fourth metal segment. The third and fourth metal segments are aligned along the first direction.

Abstract: A thin imaging device including a light source is provided. The imaging device includes a light-emitting device which emits infrared light. Infrared light emitted by the light-emitting device and reflected by a subject is received by a photoelectric conversion device included in a pixel circuit. Since an EL element is used as the light-emitting device, a thin imaging device with a light source can be formed. A pixel circuit utilizing an oxide semiconductor transistor having a property of low off-state current is used, whereby image capturing by a global shutter method is possible and a distortion-free image can be obtained even when the subject is moving.

Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxygen plasma treatment to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a spacer layer along a first fin structure and a second fin structure, etching a first portion of the spacer layer and the first fin structure to form first fin spacers and a first recess between the first fin spacers, etching a second portion of the spacer layer and the second fin structure to form second fin spacers and a second recess between the second fin spacers, and forming a first source/drain feature in the first recess and a second source/drain feature in the second recess. The second fin structure is wider than the first fin structure. The first fin spacers have a first height, and the second fin spacers have a second height that is greater than the first height.

Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.

Abstract: Provided is an integrated dicing die bonding sheet having excellent storage stability and stress relaxation properties, having no problems such as chip flying, chipping, cracking, and the like during a dicing process, and having excellent production efficiency; and a method of manufacturing a semiconductor device (particularly including a MEMS device) using the same. An integrated dicing die bonding sheet including a base film, and a silicone-based adhesive sheet having an adhesive surface adhered to the semiconductor wafer, wherein at a stage after dicing the semiconductor wafer and prior to heating, the base film can be interfacially peeled from the silicone-based adhesive sheet, and after the adhesive surface is heated within a range of 50 to 200° C., a peeling mode of the adhesive surface from another non-pressure-sensitive adhesive base material changes to cohesive failure, exhibiting permanent adhesion.

Abstract: A display device includes: a substrate; a first pixel on the substrate; a dam structure on the substrate and surrounding the first pixel in a plan view; a spacer in an area surrounded by the dam structure in the plan view; a first inorganic encapsulation layer on the dam structure and the spacer; and an organic encapsulation layer on the first inorganic encapsulation layer, wherein an upper surface of the spacer is at a higher position than an upper surface of the dam structure and an upper surface of the organic encapsulation layer.

Abstract: A semiconductor device includes a substrate, an active pattern on the substrate, the active pattern extending in a first horizontal direction, a first plurality of nanosheets on the active pattern, the first plurality of nanosheets stacked and spaced apart from each other in a vertical direction, and a gate electrode on the active pattern. The gate electrode extends in a second horizontal direction different from the first horizontal direction, and the gate electrode surrounds the first plurality of nanosheets. The semiconductor device includes an inner spacer on at least one side surface of the gate electrode, the inner spacer between adjacent ones of the first plurality of nanosheets, and the inner spacer including a crystalline insulating material.

Abstract: A semiconductor structure includes spaced apart first and second fins over a substrate, a separating wall over the substrate and having opposite first and second wall surfaces, multiple first channel features extending away from the first wall surface over the first fin such that the first channel features are spaced apart, multiple second channel features extending away from the second wall surface over the second fin such that the second channel features are spaced apart, two spaced apart first epitaxial structures on the first fin such that each first channel feature interconnects the first epitaxial structures, two spaced apart second epitaxial structures on the second fin such that each second channel feature interconnects the second epitaxial structures, and a dielectric structure including at least one bottom dielectric portion separating at least one of the first and second epitaxial structures from a corresponding first and second fins.

Abstract: The laminate of the invention has a semiconductor substrate, a support substrate, a release layer disposed so as to come into contact with the semiconductor substrate, and an adhesive layer disposed between the support substrate and the release layer, characterized in that the release layer is a film formed from a releasing agent composition containing a polyorganosiloxane component essentially containing polydimethylsiloxane; the polyorganosiloxane component has a viscosity of 5.50×103 Pa·s to 0.75×103 Pa·s, as measured at 25° C.; and the film has a thickness of 0.01 ?m to 4.90 ?m.

Abstract: A display device includes a substrate on which a plurality of light emitting elements are disposed. A plurality of lines are disposed on an upper surface of the substrate. A plurality of upper pads are disposed on the upper surface of the substrate and electrically connected to the plurality of lines. A plurality of link lines are disposed on a lower surface of the substrate. A plurality of lower pads are disposed on the lower surface of the substrate and electrically connected to the plurality of link lines. A plurality of side lines electrically connect the plurality of upper pads and the plurality of lower pads. The plurality of side lines include a plurality of first side lines and a plurality of second side lines, and the plurality of first side lines and the plurality of second side lines are disposed on different layers.

Abstract: The present technology relates to an image sensor and an electronic device that can reduce an FD capacity. An image sensor includes a substrate, a first pixel including a first photoelectric conversion area provided in the substrate, a second pixel including a second photoelectric conversion area adjacent to the first photoelectric conversion area and provided in the substrate, a trench provided in the substrate between the first photoelectric conversion area and the second photoelectric conversion area, a first area included in the first pixel, a second area included in the second pixel, and a third area in contact with the first area, the second area, and the trench. The present technology can be applied to, for example, a CMOS image sensor.