Patents Examined by Brian Turner
  • Patent number: 10937778
    Abstract: A tier of a 3D circuit comprising: one or more macro circuits, each macro circuit comprising a plurality of macro cells arranged in an array, the macro cells being separated from each other by spaces; and interconnection vias positioned in the spaces between the macro cells.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: March 2, 2021
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Hughes Metras, Fabien Clermidy, Didier Lattard, Sébastien Thuries, Pascal Vivet
  • Patent number: 10937682
    Abstract: A semiconductor tool and methods of forming semiconductor device assemblies. The semiconductor tool is a bond tip having a vacuum port and a plurality of purge ports with channels coupling the vacuum port with the purge ports. Air may be withdrawn through the vacuum to create a vacuum on the bottom of the bond tip to selectively couple a semiconductor device with the bond tip. The bond tip positions the semiconductor device on top of a stack of semiconductor devices to form a semiconductor device assembly. The assembly may be heated to reflow interconnects between the semiconductor device and the top device of the stack of semiconductor devices. Fluid provided through the purge ports may help to counter warpage of the semiconductor device to help form adequate interconnects between the devices. Fluid may also be provided through the vacuum port to counter the warpage.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: March 2, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Yet Hong Tan
  • Patent number: 10937668
    Abstract: A semiconductor package manufacturing method includes the steps of bonding a plurality of semiconductor chips to the front side of a wiring substrate, next supplying a sealing compound to the front side of the wiring substrate to thereby form a sealing layer from the sealing compound on the front side of the wiring substrate, thereby forming a package substrate, next holding the package substrate on a holding tape, next cutting the front side of the resin layer by using a profile grinding tool to thereby form a plurality of ridges and grooves on the front side of the resin layer, thereby increasing the surface area of the front side of the resin layer, and next dividing the package substrate along each division line to obtain a plurality of individual semiconductor packages.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: March 2, 2021
    Assignee: DISCO CORPORATION
    Inventors: Youngsuk Kim, Byeongdeck Jang
  • Patent number: 10930495
    Abstract: Examples of an integrated circuit with a gate structure and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate having a channel region. A gate dielectric is formed on the channel region, and a layer containing a dopant is formed on the gate dielectric. The workpiece is annealed to transfer the dopant to the gate dielectric, and the layer is removed after the annealing. In some such examples, after the layer is removed, a work function layer is formed on the gate dielectric and a fill material is formed on the work function layer to form a gate structure.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Liang Cheng, Yen-Yu Chen
  • Patent number: 10930698
    Abstract: There is provided a structure to improve BSI global shutter efficiency. In a sensor pixel circuit, at least one strong electric field is formed at the position of a floating diffusion region to accordingly have the effect of shielding the floating diffusion region. Or, the semiconductor material from the floating diffusion node toward a light incident direction is removed in the manufacturing process such that a depletion region cannot be formed in this direction. Or, a reflection layer or a photoresist layer is formed in the light incident direction to block the light. In these ways, charges generated by the undesired noises are reduced, and noise charges are difficult to reach the floating diffusion region thereby improving the shutter efficiency.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: February 23, 2021
    Assignee: PIXART IMAGING INC.
    Inventors: Kai-Chieh Chuang, Yung-Chung Lee, Yen-Min Chang
  • Patent number: 10923362
    Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including a plurality of etching regions and element regions each containing a plurality of convex and concave portions, holding the substrate and a frame with a holding sheet, forming a protective film by applying a first mixture to form a coated film above the substrate and by drying the coated film to form the protective film along the convex and concave portions, the first mixture containing a water-soluble first resin, water and a water-soluble organic solvent and has a vapor pressure higher than water, removing the protective film by irradiating a laser beam thereon to expose the substrate in the etching regions, plasma-etching the substrate along the etching regions while maintaining the protective film in the element regions to individualize the substrate, and removing the protective film by contacting the protective film with an aqueous rinse solution.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: February 16, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Noriyuki Matsubara, Shogo Okita, Hidehiko Karasaki
  • Patent number: 10923333
    Abstract: A substrate processing apparatus includes a first mounting unit, a second mounting unit and an adjusting unit. The first mounting unit is configured to mount thereon a target substrate to be processed that is a plasma processing target. The second mounting unit is disposed to surround the first mounting unit to mount thereon a focus ring. The adjusting unit is configured to adjust a height of a peripheral portion of the target substrate with respect to a height of a central portion of the target substrate in response to consumption of the focus ring.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: February 16, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Kenji Matsumoto
  • Patent number: 10923480
    Abstract: Systems, apparatuses, and methods related to capacitance reduction in a semiconductor device are described. An example method may include forming an oxide only spacer over a portion of a sense line, formed on a semiconductor substrate, to separate the sense line from a storage node contact region of a semiconductor device and to reduce a capacitance between the sense line and the storage node contact region. The method may further include forming the storage node contact region in an active area of the semiconductor device neighboring the sense line and conductively connecting the sense line to the storage node contact region to enable a storage node to be sensed by the sense line.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shyam Surthi, Litao Yang, Gurtej S. Sandhu, Richard J. Hill
  • Patent number: 10916466
    Abstract: A wafer uniting method includes a thermocompression bonding step of causing a thermocompression bonding sheet having a size comparable to or greater than a size and a shape of a wafer and a front surface of the wafer to face each other, and pressing them against each other while applying heat to thermocompression bond the thermocompression bonding sheet to the front surface of the wafer. The thermocompression bonding sheet thermocompression bonded to the wafer in the thermocompression bonding step includes at least a first thermocompression bonding sheet and a second thermocompression bonding sheet.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: February 9, 2021
    Assignee: DISCO CORPORATION
    Inventor: Kazuma Sekiya
  • Patent number: 10910514
    Abstract: Techniques related to molded etch masks are disclosed. Etch masks can be formed based on pressing a mold against a layer of pliable masking material applied to a surface of an epitaxial layered structure. The epitaxial layered structure includes a first semiconductor layer, a second semiconductor layer, and a light-emitting layer between the first and second semiconductor layers. The epitaxial layered structure is etched using the molded etch masks to form etched structures. The etched structures may be optical structures that modify light emitted through the surface or epitaxial mesas that collimate light within the epitaxial layered structure.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: February 2, 2021
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventors: Daniel Brodoceanu, David Massoubre, Karsten Moh
  • Patent number: 10896901
    Abstract: The disclosure is provided with: a temporary crimping step in which one or more semiconductor chips 10 are sequentially laminated while being temporarily crimped in each of two or more locations on a substrate 30 to thereby form chip stacks ST in a temporarily crimped state; and a permanent crimping step in which the top surfaces of all of the chip stacks ST formed in the temporarily crimped state are sequentially heated, pressurized, and permanently crimped. Furthermore, a specifying step is provided prior to the temporary crimping step for specifying a separation distance Dd which is the distance from the chip stacks ST under permanent crimping to a location at which the temperature of the substrate 30, the temperature having been raised by heating for the permanent crimping, becomes less than or equal to a prescribed permissible temperature Td, and in the temporary crimping step, the chip stacks ST in the temporarily crimped state are formed separated from each other by the separation distance Dd or more.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: January 19, 2021
    Assignee: SHINKAWA LTD.
    Inventors: Tomonori Nakamura, Toru Maeda
  • Patent number: 10892328
    Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack over a substrate, the nanosheet stack including alternating sacrificial and channel layers, the channel layers providing nanosheet channels for nanosheet field-effect transistors. The method also includes forming vertical fins in the nanosheet stack and a portion of the substrate, and forming indents in sidewalls of the sacrificial layers at sidewalls of the vertical fins. The method further includes forming nanosheet extension regions in portions of the channel layers which extend from the indented sidewalls of the sacrificial layers to the sidewalls of the vertical fins, the nanosheet extension regions increasing in thickness from the indented sidewalls of the sacrificial layers to the sidewalls of the vertical fins. The method further includes forming inner spacers using a conformal deposition process that forms air gaps in spaces between the nanosheet extension regions and the indented sidewalls of the sacrificial layers.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: January 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Yi Song, Zhenxing Bi, Kangguo Cheng, Chi-Chun Liu
  • Patent number: 10892249
    Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: January 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Brian M. Erwin, Mark W. Kapfhammer, Brian W. Quinlan, Charles L. Reynolds, Thomas Weiss
  • Patent number: 10892307
    Abstract: A display device includes a display pixel and a sensor pixel. The display pixel includes a light-emitting element including a first pixel electrode. The display pixel further includes a pixel circuit electrically coupled to the light-emitting element. The sensor pixel includes a sensor electrode overlapping the first pixel electrode. The sensor pixel further includes a sensor circuit electrically coupled to the sensor electrode. The first pixel electrode includes a first opening in a region overlapping the sensor electrode.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: January 12, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sun Hwa Lee, Mu Kyung Jeon, Il Gon Kim
  • Patent number: 10893225
    Abstract: An electronic device includes a first sensing module and a first threshold voltage generation module. The first sensing module includes a first sensing transistor having a first gate, a second gate and a semiconductor layer. The semiconductor layer of the first sensing transistor is disposed between the first gate and the second gate of the first sensing transistor. The first gate of the first sensing transistor is coupled to a top gate line. The first threshold voltage generation module includes a node coupled to the second gate of the first sensing transistor, and is used to provide a first threshold voltage in a dark state to the node of the first threshold voltage generation module.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: January 12, 2021
    Assignee: InnoLux Corporation
    Inventor: Junya Shibata
  • Patent number: 10879064
    Abstract: Provided is a method for manufacturing a semiconductor device, the semiconductor device including a substrate, and an oxide semiconductor TFT that is supported by the substrate and includes an oxide semiconductor film as an active layer. The method includes: (A) preparing MO gas containing a first organometallic compound that contains In and a second organometallic compound that contains Zn; and (B) supplying gas containing the MO gas and oxygen to the substrate placed in a chamber under a condition in which the substrate is heated to 500° C. or lower, and growing an oxide semiconductor film containing In and Zn on the substrate using an MOCVD method. Step (B) is performed under a condition in which plasma is formed in the chamber.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: December 29, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shinji Nakajima, Hirohiko Nishiki, Hirohide Mimura, Yuhichi Saitoh, Yujiro Takeda, Shogo Murashige, Izumi Ishida, Tohru Okabe
  • Patent number: 10879400
    Abstract: Field effect transistor and manufacturing method thereof are disclosed. Field effect transistor includes a substrate, a fin, spacers, a gate structure, a hard mask pattern, an insulating layer, and a gate contact. The fin protrudes from the substrate and extends in a first direction. The spacers run in parallel over the fin and extending in a second direction perpendicular to the first direction. The gate structure extends between the spacers and covers the fin. The hard mask pattern covers the gate structure and extends in between the spacers. The insulating layer is disposed over the substrate and covers the hard mask pattern, the gate structure and the spacers. The gate contact penetrates the insulating layer and physically contacts the gate structure. A bottom surface of the gate contact is coplanar with top surfaces of the spacers and the hard mask pattern.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chiang Tsai, Jyh-Huei Chen, Fu-Hsiang Su
  • Patent number: 10879264
    Abstract: An alternating layer stack of insulating layers and sacrificial material layers is formed over a semiconductor substrate, and memory stack structures are formed through the vertically-alternating layer stack. A pair of unconnected barrier trenches or a moat trench is formed through the alternating stack concurrently with formation of backside trenches. Backside recesses are formed by isotropically etching the sacrificial material layers selective to the insulating layers while a dielectric liner covers the barrier trenches or the moat trench. A vertically alternating sequence of the insulating plates and the dielectric spacer plates is provided between the pair of barrier trenches or inside the moat trench. Electrically conductive layers are formed in the backside recesses. A first conductive via structure is formed through the vertically alternating sequence concurrently with formation of a second conductive via structure through a dielectric material portion adjacent to the alternating stack.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: December 29, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yoshitaka Otsu, Kei Nozawa, Naoto Hojo
  • Patent number: 10879135
    Abstract: A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Shang-Wei Fang, Jing-Sen Wang, Yuan-Yao Chang, Wei-Ray Lin, Ting-Hua Hsieh, Pei-Hsuan Lee, Yu-Hsuan Huang
  • Patent number: 10872921
    Abstract: An image sensor and a method for fabricating the image sensor are provided. In the method for fabricating the image sensor, at first, a substrate having a first surface and a second surface opposite to the first surface is provided. Then, light-sensitive regions are formed in the substrate. Thereafter, transfer gate structures are formed on the first surface of the substrate. Then, the first surface of the substrate is formed to form recess structures on the light-sensitive regions. Thereafter, light-reflective layers are formed to cover the recess structures of the first surface of the substrate, in which the recess structures are filled with protrusion structures of the light-reflective layers. Further, the second surface of the substrate may be etched to form recess structures corresponding to the light-sensitive regions.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Hsin-Chi Chen