Patents Examined by Brian Turner
  • Patent number: 11515179
    Abstract: Exemplary semiconductor processing systems may include a processing chamber, and may include a remote plasma unit coupled with the processing chamber. Exemplary systems may also include a mixing manifold coupled between the remote plasma unit and the processing chamber. The mixing manifold may be characterized by a first end and a second end opposite the first end, and may be coupled with the processing chamber at the second end. The mixing manifold may define a central channel through the mixing manifold, and may define a port along an exterior of the mixing manifold. The port may be fluidly coupled with a first trench defined within the first end of the mixing manifold. The first trench may be characterized by an inner radius at a first inner sidewall and an outer radius, and the first trench may provide fluid access to the central channel through the first inner sidewall.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: November 29, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Mehmet Tugrul Samir, Dongqing Yang
  • Patent number: 11508692
    Abstract: A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: November 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kung-Chen Yeh, Szu-Wei Lu, Tsung-Fu Tsai, Ying-Ching Shih
  • Patent number: 11502042
    Abstract: A method of mounting electronic components on one or more carrier bodies is disclosed. The method comprises providing a support body with at least one first alignment mark, mounting the one or more carrier bodies, each having at least one second alignment mark, on the support body by alignment between the at least one first alignment mark and the at least one second alignment mark. Thereafter, the method includes mounting the plurality of electronic components on a respective one of the one or more carrier bodies by alignment using the at least one second alignment mark.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: November 15, 2022
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Thomas Behrens, Martin Gruber, Thorsten Scharf, Peter Strobel
  • Patent number: 11501968
    Abstract: Method for filling a gap, comprising providing in a deposition chamber a semiconductor substrate having a gap, wherein a bottom of the gap includes a crystalline semiconducting material and wherein a side wall of the gap includes an amorphous material; depositing a silicon precursor in the gap.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: November 15, 2022
    Assignee: ASM IP Holding B.V.
    Inventors: Dieter Pierreux, Anna Trovato, Kelly Houben, Steven van Aerde, Bert Jongbloed, Wilco A. Verweij
  • Patent number: 11495682
    Abstract: Nanostructure field-effect transistors (NSFETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a gate stack over the semiconductor substrate, the gate stack including a gate electrode and a gate dielectric layer; a first epitaxial source/drain region adjacent the gate stack; and a high-k dielectric layer extending between the semiconductor substrate and the first epitaxial source/drain region, the high-k dielectric layer contacting the first epitaxial source/drain region, the gate dielectric layer and the high-k dielectric layer including the same material.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chuan Yang, Shih-Hao Lin
  • Patent number: 11488875
    Abstract: A semiconductor substrate measuring apparatus includes a light source to generate irradiation light having a sequence of on/off at a predetermined interval, the light source to provide the irradiation light to a chamber with an internal space for processing a semiconductor substrate using plasma, an optical device between the light source and the chamber, the optical device to split a first measurement light into a first optical path, condensed while the light source is turned on, to split a second measurement light into a second optical path, condensed while the light source is turned off, and to synchronize with the on/off sequence, and a photodetector connected to the first and second optical paths, the photodetector to subtract spectra of first and second measurement lights to detect spectrum of reflected light, and to detect plasma emission light emitted from the plasma based on the spectrum of the second measurement light.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: November 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junbum Park, Younghwan Kim, Jongsu Kim, Youngjoo Lee, Yoojin Jeong
  • Patent number: 11482417
    Abstract: A method includes providing a first plate including a first surface, a second surface opposite to the first surface, and a first recess indented from the first surface towards the second surface; providing a semiconductor structure including a third surface, a fourth surface opposite to the third surface, and a first sidewall extending between the third surface and the fourth surface; placing the semiconductor structure over the first plate; and disposing a priming material over the third surface of the semiconductor structure, wherein a peripheral portion of the fourth surface of the semiconductor structure is in contact with the first surface of the first plate upon the disposing of the priming material.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: October 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yung-Yao Lee, Chen Yi Hsu, Wei-Hsiang Tseng
  • Patent number: 11482533
    Abstract: An apparatus and a method for forming a 3-D NAND device are disclosed. The method of forming the 3-D NAND device may include forming a plug fill and a void. Advantages gained by the apparatus and method may include a lower cost, a higher throughput, little to no contamination of the device, little to no damage during etching steps, and structural integrity to ensure formation of a proper stack of oxide-nitride bilayers.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: October 25, 2022
    Assignee: ASM IP Holding B.V.
    Inventors: BokHeon Kim, David Kohen, Alexandros Demos
  • Patent number: 11476166
    Abstract: A semiconductor device is provided. The device includes a first pair and a second pair of source/drain features over a semiconductor substrate. The first pair of source/drain features are p-type doped. The second pair of source/drain features are n-type doped. A first stack of semiconductor layers connect the first pair of source/drain features along a first direction. A second stack of semiconductor layers connect the second pair of source/drain features along a second direction. A first gate is between vertically adjacent layers of the first stack of semiconductor layers. The first gate has a first portion that has a first dimension along the first direction. A second gate is between vertically adjacent layers of the second stack of semiconductor layers. The second gate has a second portion that has a second dimension along the second direction. The second dimension is larger than the first dimension.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: October 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11476217
    Abstract: A method of manufacturing an augmented LED array assembly is described which comprises providing an LED array assembly configured for inclusion in an LED lighting circuit, the LED array assembly comprising a micro-LED array mounted onto a driver integrated circuit, the driver integrated circuit comprising contact pads configured for electrical connections to a circuit board assembly; providing an essentially planar carrier comprising a plurality of contact bridges, each contact bridge extending between a first contact pad and a second contact pad; and mounting the contact bridge carrier to the LED array assembly by forming solder bonds between the first contact pads of the contact bridge carrier and the contact pads of the driver integrated circuit.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: October 18, 2022
    Assignee: Lumileds LLC
    Inventors: Michael Deckers, Tze Yang Hin, Ronald Bonne
  • Patent number: 11462439
    Abstract: A wafer processing method includes a pattern region detecting step, an evaluation region setting step, and an evaluation region deploying step. The pattern region detecting step is a step of detecting a period and positional information in which a substantially identical image appears in an imaged image and detecting a pattern region corresponding to one period. The evaluation region setting step is a step of detecting a position in which no metallic pattern is formed on planned dividing lines and setting the position as an evaluation region for evaluating quality of a processed groove. The evaluation region deploying step is a step of recording the position of the evaluation region in the pattern region and deploying the evaluation region at similar positions in different pattern regions.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: October 4, 2022
    Assignee: DISCO CORPORATION
    Inventors: Hironari Ohkubo, Keita Obara, Shinya Honda
  • Patent number: 11456260
    Abstract: A wafer processing method for forming a modified layer within a wafer along planned dividing lines forms the modified layer within the wafer, positions a condensing point within the wafer or at a top surface of the wafer and applies a second laser beam while moving the condensing point, images reflected light, and determines a processed state of the wafer on the basis of an imaged image. The second laser beam is formed such that a sectional shape of the second laser beam in a plane perpendicular to a traveling direction of the second laser beam is not axisymmetric with respect to an axis along the planned dividing lines.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: September 27, 2022
    Assignee: DISCO CORPORATION
    Inventors: Shunsuke Teranishi, Shigefumi Okada, Shuichiro Tsukiji, Yuki Ikku
  • Patent number: 11456214
    Abstract: A method of processing a workpiece includes a thermosetting step of heating an area of an expandable sheet around a workpiece to a predetermined temperature or higher and thereafter cooling the heated area of the expandable sheet to make the area harder than before the area has been heated, and after the thermosetting step, an expanding step of expanding the area of the expandable sheet around the workpiece in planar directions to divide the workpiece into chips or to increase distances between the adjacent chips.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: September 27, 2022
    Assignee: DISCO CORPORATION
    Inventor: Yoshinobu Saito
  • Patent number: 11450601
    Abstract: Some embodiments include an assembly having a memory stack which includes dielectric levels and conductive levels. A select gate structure is over the memory stack. A trench extends through the select gate structure. The trench has a first side and an opposing second side, along a cross-section. The trench splits the select gate structure into a first select gate configuration and a second select gate configuration. A void is within the trench and is laterally between the first and second select gate configurations. Channel material pillars extend through the memory stack. Memory cells are along the channel material pillars.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: September 20, 2022
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, George Matamis
  • Patent number: 11450673
    Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chuan Yang, Chia-Hao Pao, Yu-Kuan Lin, Lien Jung Hung, Ping-Wei Wang, Shih-Hao Lin
  • Patent number: 11444202
    Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of semiconductor nanosheets, a source/drain (S/D) region, a gate stack, and a liner layer. The substrate includes at least one fin. The plurality of semiconductor nanosheets are stacked on the at least one fin. The S/D region abuts the plurality of semiconductor nanosheets. The gate stack wraps the plurality of semiconductor nanosheets. The liner layer lines a bottom surface and a sidewall of the S/D region and is sandwiched between the S/D region and the gate stack.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: September 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chi-On Chui, Chien-Ning Yao
  • Patent number: 11437519
    Abstract: A TFT device and a manufacturing method of the same, a TFT array substrate and a display device is provided by this disclosure. A light-shielding layer is configured under the active layer, and one of the source doping member and the drain doping member is attached to the buffer layer and the light-shielding layer to generate a stable voltage on the light-shielding layer. At the same time, forming holes in the light-shielding layer and the buffer layer is avoided and connecting a source electrode, the active layer and the light-shielding layer with conductive lines is no more needed, which decreases one mask, and corresponding exposure and etching process, thus decreases manufacturing cost of the TFT.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: September 6, 2022
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Wenbo Zhang
  • Patent number: 11430816
    Abstract: The present disclosure provides a method for preparing an interlayer insulating layer and a method for manufacturing a thin film transistor, and a thin film transistor, belongs to the field of display technology, and can solve the problem of poor resistance to breakdown of the interlayer insulating layer in the related art. The method for preparing an interlayer insulating layer includes the following steps: forming a silicon oxide layer with a first reaction gas and forming a silicon nitride layer with a second reaction gas such that hydrogen content in the silicon nitride layer is less than or equal to hydrogen content in the silicon oxide layer.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: August 30, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ming Wang, Ce Zhao, Wei Song
  • Patent number: 11430819
    Abstract: The present invention provides an array substrate and a manufacturing method thereof. The manufacturing method of the array substrate adopts a multi-stage mask to expose and develop, so that a thickness of a remaining photoresist layer in a channel region corresponding to a display region is same as a thickness of a remaining photoresist layer in a channel region corresponding to a GOA region. Therefore, the two channel regions can be completely etched to prevent short-circuiting, and make up for defects of different action efficiency of developers caused by different densities of thin film transistors in the display region and the GOA region.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: August 30, 2022
    Assignee: TCL China Star Optoelectronics Technology Co., Ltd.
    Inventor: Weina Yong
  • Patent number: 11424338
    Abstract: A semiconductor device according to the present disclosure includes a vertical stack of channel members, a gate structure over and around the vertical stack of channel members, and a first source/drain feature and a second source/drain feature. Each of the vertical stack of channel members extends along a first direction between the first source/drain feature and the second source/drain feature. Each of the vertical stack of channel members is spaced apart from the first source/drain feature by a silicide feature.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Pei-Yu Wang