Abstract: The present technology relates to an image sensor and an electronic device that can reduce an FD capacity. An image sensor includes a substrate, a first pixel including a first photoelectric conversion area provided in the substrate, a second pixel including a second photoelectric conversion area adjacent to the first photoelectric conversion area and provided in the substrate, a trench provided in the substrate between the first photoelectric conversion area and the second photoelectric conversion area, a first area included in the first pixel, a second area included in the second pixel, and a third area in contact with the first area, the second area, and the trench. The present technology can be applied to, for example, a CMOS image sensor.

Abstract: A device includes a first vertical stack of first nanostructures formed over a substrate, a second vertical stack of second nanostructures adjacent to the first vertical stack, and a first gate structure adjacent the first nanostructures. The first gate structure includes a first gate portion between the first nanostructures, and a second gate portion extending from a first sidewall of the first gate portion to a second sidewall of the first gate portion. The second sidewall is between the first sidewall and the substrate, and is a different material than the first gate portion. A second gate structure is adjacent the second nanostructures, and a second wall structure is between the second gate portion and the second gate structure.

Abstract: A temporary adhesion method for temporarily adhering a wafer to a support via a temporary adhesive layer, the wafer having a first main surface including a circuit and a second main surface to be processed, the second main surface being located on an opposite side to the first main surface, wherein a temporary adhesion between the first main surface of the wafer and the support is performed via the temporary adhesive layer including a dry adhesive fiber structure having a plurality of pillar structures.

Abstract: A vertically protruding structure is formed. The vertically protruding structure includes a substrate, a first semiconductor layer disposed over the substrate, a channel layer disposed over the first semiconductor layer, and a second semiconductor layer disposed over the channel layer. The first semiconductor layer and the second semiconductor layer each contain a first type of semiconductive material. The channel layer contains a second type of semiconductive material different from the first type. First recesses are formed in the first semiconductor layer and the second semiconductor layer. Each of the first recesses protrudes laterally inward. The first recesses are filled with dielectric spacers. The channel layer and the substrate are laterally trimmed. The remaining portions of the channel layer and the dielectric spacers define second recesses that protrude laterally inward. Gate structures are formed in the second recesses.

Abstract: Disclosed are a quantum dot and a preparation method therefor, a quantum dot light-emitting device, and a display apparatus. The quantum dot includes a core structure and a shell structure that surrounds the core structure, wherein the material of the outermost shell in the shell structure includes an electron transport material and a hole transport material.

Abstract: A semiconductor device includes: a chip having a main surface; a trench insulation structure that defines an active region in the main surface; a first conductivity type well region formed in the active region; a second conductivity type first impurity region formed in the well region; a second impurity region formed in the well region and surrounding the first impurity region in a plan view; a gate electrode formed on the well region between the first impurity region and the second impurity region, and surrounding the first impurity region in a plan view; a gate insulating film formed between the gate electrode and the well region; a gate contact portion formed on the trench insulation structure; and a gate connection portion that crosses the second impurity region from a boundary between the trench insulation structure and the active region and connects the gate contact portion and the gate electrode.

Abstract: Semiconductor die assemblies with molded semiconductor dies, and associated methods and systems are disclosed. In some embodiments, a semiconductor die assembly includes a package substrate and a controller die attached to the package substrate. The semiconductor die assembly comprises a mold structure including the controller die and having a surface facing away from the package substrate. The controller die may be completely encased within the mold structure. Further, one or more stacks of semiconductor dies (e.g., memory dies) are attached to the surface of the mold structure. Accordingly, the semiconductor die assembly does not include support structures for the stacks of semiconductor dies attached above the controller die.

Abstract: A memory array comprising strings of memory cells comprises conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprising a vertical stack comprises alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Conducting material of a lower of the conductive tiers directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The conducting material in the lower conductive tier comprises upper conductively-doped semiconductive material, lower conductively-doped semiconductive material, and intermediate material vertically there-between. Other embodiments, including method, are disclosed.

Abstract: A method includes forming a semiconductor fin protruding from a substrate, forming a dummy gate structure across the semiconductor fin, recessing the semiconductor fin in a region adjacent the dummy gate structure to form a recess, growing an epitaxial feature in the recess to fully covers an end of the semiconductor fin that is otherwise exposed in the recess, trimming the epitaxial feature to reduce a width of the epitaxial feature to expose again a portion of the end of the semiconductor fin in the recess, depositing a dielectric layer on the epitaxial feature and in physical contact with the exposed portion of the end of the semiconductor fin, and replacing the dummy gate structure with a metal gate structure.

Abstract: A display device includes a display area, a bending area, and a contact area between the display area and the bending area, a first gate connection line, in the contact area and extended toward the display area, a first source connection line on the first gate connection line and electrically connected to the first gate connection line, in the contact area, a second source connection line on the first source connection line and electrically connected to the first source connection line, in the contact area, and a blocking line on the second source connection line and electrically connected to the second source connection line, in the contact area.

Abstract: A semiconductor structure includes a channel structure, a gate structure, two source/drain features, and a plurality of inner spacers. The channel structure includes a plurality of channel features which are spaced apart from each other. The gate structure is disposed to surround the channel features. The source/drain features are disposed at two opposite sides of the channel structure such that each of the channel features interconnects the source/drain features. Each of the inner spacers is disposed to separate the gate structure from a corresponding one of the source/drain features. Each of the inner spacers includes an inner spacer body and a lateral nitrided portion. The lateral nitrided portion is in direct contact with the corresponding one of the source/drain features and has a nitrogen content greater than that of the inner spacer body.

Abstract: Various example embodiments are directed to an image sensor, a method of forming a pixel, a pixel readout circuit, and a calibration method. The image sensor includes a substrate including a plurality of pixels, each pixel of the plurality of pixels configured to convert light into a corresponding electric signal, each pixel including a first photoelectric sensor and a second photoelectric sensor, a plurality of deep trench isolation (DTI) structures, each DTI structure of the plurality of DTI structures configured to isolate the first photoelectric sensor and the second photoelectric sensor of a corresponding pixel of the plurality of pixels, each DTI structure in the corresponding pixel in the substrate, a plurality of metal gates (MGs) on the plurality of DTI structures, and in each pixel of the plurality of pixels, the second photoelectric sensor is included inside the first photoelectric sensor.

Abstract: A system configured to detect defects on a wafer is provided. The system includes an inspection subsystem configured to acquire scan data of a target region on the wafer. The target region comprises a plurality of circuit layout streaming data on the wafer and the defects in proximity to the circuit layout streaming data or in the circuit layout streaming data. A graphic design subsystem (GDS) is configured to store a map of circuit layout streaming data of the wafer. A software tool for designing electronic systems is configured to label the scan data with attributes from the map of circuit layout streaming data. A decision subsystem is configured to qualify the process based on a predetermined defect level from the labeled scan data by using a multi-dimension clustering method, wherein the predetermined defect level is an accumulated defect formed on the semiconductor wafer during processing.

Abstract: Gate-all-around (GAA) devices and methods of manufacturing such devices are described herein. A method includes forming a multi-layer structure over a substrate and forming a plurality of source/drain regions in the multi-layer structure. Fins are then patterned into the multi-layer structure through adjacent source/drain regions. A wire release process is performed to remove materials of one or more of the layers in the multi-layer stack. The remaining layers of the multi-layer stack form a stack of nanostructures connecting adjacent source/drain regions of the fins.

Abstract: In an embodiment, a device includes: a first semiconductor strip over a substrate, the first semiconductor strip including a first channel region; a second semiconductor strip over the substrate, the second semiconductor strip including a second channel region; a dielectric strip disposed between the first semiconductor strip and the second semiconductor strip, a width of the dielectric strip decreasing along a first direction extending away from the substrate, the dielectric strip including a void; and a gate structure extending along the first channel region, along the second channel region, and along a top surface and sidewalls of the dielectric strip.

Abstract: Provided are a power semiconductor device using a lead frame, in which deformation and bending of terminals is suppressed, insulation is secured between terminals, and mounting onto a control board is facilitated, and a manufacturing method thereof. A package in which a semiconductor element mounted on a lead frame is sealed, terminals being bent and exposed from side surfaces of the package, and, a terminal bending portion being a portion bent in each of the terminals, a width thereof being larger than a width of a tip of the terminal, and being equal to or smaller than the width of a contact portion of the terminal in contact with the package are provided; therefore, deformation and bending of the terminals is suppressed, a necessary insulation is secured between the adjacent terminals, and mounting onto a control board is facilitated.

Abstract: A method for modulating a threshold voltage of a device. The method includes providing a fin extending from a substrate, where the fin includes a plurality of semiconductor channel layers defining a channel region for a P-type transistor. In some embodiments, the method further includes forming a first gate dielectric layer surrounding at least three sides of each of the plurality of semiconductor channel layers of the P-type transistor. Thereafter, the method further includes forming a P-type metal film surrounding the first gate dielectric layer. In an example, and after forming the P-type metal film, the method further includes annealing the semiconductor device. After the annealing, and in some embodiments, the method includes removing the P-type metal film.

Abstract: A manufacturing method of a semiconductor device, includes: preparing a wafer having a first surface on which a plurality of semiconductor elements is formed and to which a support plate is attached through an adhesive; grinding a second surface of the wafer opposite to the first surface in a state where the support plate is attached to the first surface of the wafer; forming a vertical crack inside the wafer and along a boundary between the adjacent semiconductor elements by pressing a scribe wheel against the wafer along the boundary; separating the support plate from the wafer while leaving the adhesive on the first surface of the wafer; cleaving the wafer along the boundary by pressing a breaking bar against the wafer over the adhesive and along the boundary; and removing the adhesive from at least one of the semiconductor elements divided from the wafer by the cleaving.

Abstract: Disclosed are a method of transferring semiconductor chips. The method may include providing a first substrate, adhering a support substrate to the first substrate, supplying and aligning a plurality of semiconductor chips, partially adhering a second substrate to a first surface of the first substrate, separating the support substrate from the first substrate, and adhering the plurality of semiconductor chips to the second substrate by supplying a fluid to a periphery of a second surface of the first substrate and applying a pressure to the second surface.

Abstract: A nitride-based semiconductor device includes a first and second nitride-based semiconductor layers, two or more source/drain (S/D) electrodes, a gate electrode, a doped III-V semiconductor layer, a gate protection layer and a first passivation layer. The doped III-V semiconductor layer is disposed between the second nitride-based semiconductor layer and the gate electrode. The gate protection layer caps the gate electrode and the doped III-V semiconductor layer and is separated from the S/D electrodes. The first passivation layer covers the second nitride-based semiconductor layer and the gate protection layer and abuts against sidewalls of the S/D electrodes which are separated from the gate protection layer by the first passivation layer.