Abstract: Provided is a method for manufacturing a semiconductor structure and a semiconductor structure, and relates to the field of semiconductor technology. The method for manufacturing the semiconductor structure includes: providing a substrate, stacking and forming a bit line contact layer, a first mask layer, a second mask layer and a plurality of mask structures arranged spaced apart from each other in sequence on the substrate, and forming first openings between adjacent mask structures; and removing a part of the second mask layer exposed in the first openings so as to form first grooves in the second mask layer.

Abstract: A device includes a semiconductor region, an interfacial layer over the semiconductor region, the interfacial layer including a semiconductor oxide, a high-k dielectric layer over the interfacial layer, and an intermixing layer over the high-k dielectric layer. The intermixing layer includes oxygen, a metal in the high-k dielectric layer, and an additional metal. A work-function layer is over the intermixing layer. A filling-metal region is over the work-function layer.

Abstract: A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.

Abstract: An overlay mark forming a Moire pattern, an overlay measurement method using the overlay mark, an overlay measurement apparatus using the overlay mark, and a manufacturing method of a semiconductor device using the overlay mark are provided. The overlay mark for measuring an overlay based on an image is configured to determine a relative misalignment between at least two pattern layers. The overlay mark includes a first overlay mark including a pair of first grating patterns which has a first pitch along a first direction and which is rotationally symmetrical by 180 degrees, and includes a second overlay mark including a pair of second grating patterns and a pair of third grating patterns. The second grating patterns partially overlap the first grating patterns and are rotationally symmetrical by 180 degrees, and the third grating patterns partially overlap the first grating patterns and are rotationally symmetrical by 180 degrees.

Abstract: A capacitor includes a first electrode, a second electrode facing the first electrode, and a dielectric layer disposed between the first and second electrodes and being in contact with each of the first and second electrodes. The dielectric layer has a thickness of 10 nm or more. The first electrode contains carbon. At the interface between the dielectric layer and the first electrode, an elemental percentage of carbon is 30 atomic % or less.

Abstract: A method for sawing a semiconductor wafer is provided. The method includes sawing the semiconductor wafer with a first dicing blade to form a first opening. The semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape. The first opening is formed in the upper portion of the substrate. The method also includes sawing the semiconductor wafer with a second dicing blade from the first opening to form a second opening under the first opening and in the middle portion of the substrate. The method further includes sawing the semiconductor wafer with a third dicing blade from the second opening to form a third opening under the second opening and penetrating the lower portion of the substrate, so that the semiconductor wafer is divided into two dies. The first dicing blade, the second dicing blade, and the third dicing blade have different widths.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.

Abstract: A display device includes: a substrate defining an opening and including a display area and a non-display area between the opening and display area, a pixel array including a plurality of pixels in the display area, each of the pixels having a pixel electrode, an opposite electrode facing the pixel electrode, and an intermediate layer between the pixel electrode and opposite electrode, a plurality of data lines bypassing the opening in the non-display area, first and second insulating layers, which cover the plurality of data lines, a conductive layer between the first and second insulating layers, and a thin film encapsulation layer covering the pixel array, the thin film encapsulation layer including at least one organic encapsulation layer and at least one inorganic encapsulation layer, and wherein, in the non-display area, a first groove is defined by the first insulating layer, the conductive layer, and the second insulating layer.

Abstract: A component manufacturing method includes a step of obtaining a holding tool. The holding tool includes: a frame body having an opening; and a holding film placed on the frame body. The step is a step of placing the holding film on the frame body while stretching the holding film in at least three different directions or in all directions to the frame body. The holding film includes a base layer and a holding layer. The holding tool forming device includes: a mechanism that pushes a plain film from a base layer side to bring about a stretched state; a mechanism that fixes the plain film to the frame body such that the stretched state is maintained; and a mechanism that isolates an unnecessary portion from the plain film to obtain the holding film.

Abstract: A semiconductor device includes first and second active patterns on first and second active regions of a substrate, respectively, a pair of first source/drain patterns and a first channel pattern therebetween which are in an upper portion of the first active pattern, a pair of second source/drain patterns and a second channel pattern therebetween which are in an upper portion of the second active pattern, and first and second gate electrodes intersecting the first and second channel patterns, respectively. Each of the first and second gate electrodes includes a first metal pattern adjacent to a corresponding one of the first and second channel patterns. The first and second channel patterns include SiGe. A Ge concentration of the second channel pattern is higher than a Ge concentration of the first channel pattern. A thickness of the first metal pattern of the second gate electrode is greater than a thickness of the first metal pattern of the first gate electrode.

Abstract: A semiconductor device, including a silicon on insulator (SOI) substrate is disclosed. The device may include gate structures formed on the SOI substrate and being spaced apart from each other in a horizontal direction, and a plurality of channels spaced apart from each other in a vertical direction. Each of the channels may extend through each of the gate structures in the horizontal direction. The device may include a seed layer and a source/drain region. The source/drain region may be connected to the channels, and each sidewall of the source/drain region in the horizontal direction may have a concave-convex shape. The device may include a protruding portion of the source/drain region formed between the gate structures that protrudes in the horizontal direction compared to a non-protruding portion of the source/drain region formed between the channels.

Abstract: A semiconductor device includes a fin structure that protrudes vertically out of a substrate, wherein the fin structure contains silicon germanium (SiGe). An epi-silicon layer is disposed on a sidewall of the fin structure. The epi-silicon layer contains nitrogen. One or more dielectric liner layers are disposed on the epi-silicon layer. A dielectric isolation structure is disposed over the one or more dielectric liner layers.

Abstract: Semiconductor structures is provided. The semiconductor structure includes a semiconductor substrate having at least one first region, a plurality of second regions and a plurality of third regions; at least one second fin formed on one second region of the plurality of second region; at least one third fin formed on one third region of the plurality of third regions; a first epitaxial layer formed in the at least one first fin; and a second epitaxial layer formed in the at least one second fin and the at least one third fin.

Abstract: A substrate processing apparatus configured to process a substrate includes a holder configured to hold, in a combined substrate in which a first substrate and a second substrate are bonded to each other, the second substrate; and a modifying device configured to form, to an inside of the first substrate held by the holder, a peripheral modification layer by radiating laser light for periphery along a boundary between a peripheral portion of the first substrate as a removing target and a central portion thereof, and, also, configured to form an internal modification layer by radiating laser light for internal surface along a plane direction of the first substrate. The modifying device switches the laser light for periphery and the laser light for internal surface by adjusting at least a shape or a number of the laser light for periphery and the laser light for internal surface.

Abstract: Provided is a memory device including a substrate, a stack structure, a polysilicon layer, a vertical channel structure, and a charge storage structure. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The polysilicon layer is disposed between the substrate and the stack structure. The vertical channel structure penetrates through the stack structure and the polysilicon layer. The charge storage structure is at least disposed between the vertical channel structure and the plurality of conductive layers.

Abstract: A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (11-14, 17-20) which are separated from one another by a barrier oxide layer (15) and which are separately processed to form first remnant silicon germanium nanosheet layers (12, 14) in the bottom Si/SiGe superlattice structures having a first gate length dimension (DG1) and to form second remnant silicon germanium nanosheet layers (18, 20) in the top Si/SiGe superlattice structures having a second, smaller gate length dimension (DG2) so that the nanosheet transistor stack may then be processed to simultaneously form bottom and top gate electrodes which replace, respectively, the first and second remnant silicon germanium nanosheet layers.

Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

Abstract: Provided is a semiconductor device comprising an active region on a substrate and including first and second sidewalls extending in a first direction and an epitaxial pattern on the active region, wherein the epitaxial pattern includes first and second epitaxial sidewalls extending from the first and second sidewalls, respectively, the first epitaxial sidewall includes a first epitaxial lower sidewall, a first epitaxial upper sidewall, and a first epitaxial connecting sidewall connecting the first epitaxial lower sidewall and the first epitaxial upper sidewall, the second epitaxial sidewall includes a second epitaxial lower sidewall, a second epitaxial upper sidewall, and a second epitaxial connecting sidewall connecting the second epitaxial lower sidewall and the second epitaxial upper sidewall, a distance between the first and second epitaxial upper sidewalls decreases away from the active region, and the first and second epitaxial lower sidewalls extend in parallel to a top surface of the substrate.

Abstract: A memory includes: a dielectric fin formed over a substrate; and a pair of memory cells disposed along respective sidewalls of the dielectric fin, each of the pair of memory cells comprising: a first conductor layer; a selector layer; a resistive material layer; and a second conductor layer, wherein the first conductor layer, selector layer, resistive material layer, and second conductor layer each includes upper and lower boundaries, and at least one of the upper and lower boundaries is tilted away from one of the sidewalls of the dielectric fin by an angle.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.