Abstract: Gate-all-around (GAA) devices and methods of manufacturing such devices are described herein. A method includes forming a multi-layer structure over a substrate and forming a plurality of source/drain regions in the multi-layer structure. Fins are then patterned into the multi-layer structure through adjacent source/drain regions. A wire release process is performed to remove materials of one or more of the layers in the multi-layer stack. The remaining layers of the multi-layer stack form a stack of nanostructures connecting adjacent source/drain regions of the fins.

Abstract: In an embodiment, a device includes: a first semiconductor strip over a substrate, the first semiconductor strip including a first channel region; a second semiconductor strip over the substrate, the second semiconductor strip including a second channel region; a dielectric strip disposed between the first semiconductor strip and the second semiconductor strip, a width of the dielectric strip decreasing along a first direction extending away from the substrate, the dielectric strip including a void; and a gate structure extending along the first channel region, along the second channel region, and along a top surface and sidewalls of the dielectric strip.

Abstract: Provided are a power semiconductor device using a lead frame, in which deformation and bending of terminals is suppressed, insulation is secured between terminals, and mounting onto a control board is facilitated, and a manufacturing method thereof. A package in which a semiconductor element mounted on a lead frame is sealed, terminals being bent and exposed from side surfaces of the package, and, a terminal bending portion being a portion bent in each of the terminals, a width thereof being larger than a width of a tip of the terminal, and being equal to or smaller than the width of a contact portion of the terminal in contact with the package are provided; therefore, deformation and bending of the terminals is suppressed, a necessary insulation is secured between the adjacent terminals, and mounting onto a control board is facilitated.

Abstract: A method for modulating a threshold voltage of a device. The method includes providing a fin extending from a substrate, where the fin includes a plurality of semiconductor channel layers defining a channel region for a P-type transistor. In some embodiments, the method further includes forming a first gate dielectric layer surrounding at least three sides of each of the plurality of semiconductor channel layers of the P-type transistor. Thereafter, the method further includes forming a P-type metal film surrounding the first gate dielectric layer. In an example, and after forming the P-type metal film, the method further includes annealing the semiconductor device. After the annealing, and in some embodiments, the method includes removing the P-type metal film.

Abstract: A manufacturing method of a semiconductor device, includes: preparing a wafer having a first surface on which a plurality of semiconductor elements is formed and to which a support plate is attached through an adhesive; grinding a second surface of the wafer opposite to the first surface in a state where the support plate is attached to the first surface of the wafer; forming a vertical crack inside the wafer and along a boundary between the adjacent semiconductor elements by pressing a scribe wheel against the wafer along the boundary; separating the support plate from the wafer while leaving the adhesive on the first surface of the wafer; cleaving the wafer along the boundary by pressing a breaking bar against the wafer over the adhesive and along the boundary; and removing the adhesive from at least one of the semiconductor elements divided from the wafer by the cleaving.

Abstract: Disclosed are a method of transferring semiconductor chips. The method may include providing a first substrate, adhering a support substrate to the first substrate, supplying and aligning a plurality of semiconductor chips, partially adhering a second substrate to a first surface of the first substrate, separating the support substrate from the first substrate, and adhering the plurality of semiconductor chips to the second substrate by supplying a fluid to a periphery of a second surface of the first substrate and applying a pressure to the second surface.

Abstract: A nitride-based semiconductor device includes a first and second nitride-based semiconductor layers, two or more source/drain (S/D) electrodes, a gate electrode, a doped III-V semiconductor layer, a gate protection layer and a first passivation layer. The doped III-V semiconductor layer is disposed between the second nitride-based semiconductor layer and the gate electrode. The gate protection layer caps the gate electrode and the doped III-V semiconductor layer and is separated from the S/D electrodes. The first passivation layer covers the second nitride-based semiconductor layer and the gate protection layer and abuts against sidewalls of the S/D electrodes which are separated from the gate protection layer by the first passivation layer.

Abstract: Embodiments of the disclosure relate to methods of depositing seam-free gapfill. In some embodiments, the gapfill consists of titanium nitride. The gapfill methods comprise forming a first layer and a second layer. The firs layer is formed without treatment or densification, while the second layer is formed with periodic treatment. The resulting gapfill in advantageously seam-free.

Abstract: An integrated circuit (IC) structure includes a fin structure protruding from a semiconductor substrate, the fin structure including a first portion having a first width, a second portion having a second width that is different from the first width, and a third portion extending continuously along a first direction over the semiconductor substrate, the first width and the second width being measured along a second direction perpendicular to the first direction. The IC structure also includes a first standard cell including a first metal gate stack engaged with the first portion, a second standard cell including a second metal gate stack engaged with the second portion, and a filler cell disposed between the first standard cell and the second standard cell, where the filler cell includes the third portion that connects the first portion to the second portion.

Abstract: A semiconductor device includes first and second gate structures, first and second contact plug structures and a first wiring on a substrate. The first and second source/drain layers are formed on portions of the substrate adjacent to the first and second gate structures, respectively. The first and second contact plug structures are formed on the first and second source/drain layers, respectively. The first wiring contacts an upper surface of the first gate structure. The first gate structure includes a first gate electrode and a first gate insulation pattern on a lower surface and a sidewall of the first gate electrode. The second gate structure includes a second gate electrode and a second gate insulation pattern on a lower surface and a sidewall of the second gate electrode. The upper surface of the second gate electrode is lower than an upper surface of the first gate electrode.

Abstract: An image sensing device includes a semiconductor substrate, an insulation layer disposed below the semiconductor substrate, a through hole formed to extend to the inside of the insulation layer while penetrating the semiconductor substrate, a through silicon via (TSV) structure formed along an inner surface of the through hole, and a photoresist formed over the TSV to gap-fill at least a portion of the through hole.

Abstract: A light emitting device structure including a first light emitting element and a second light emitting element is provided. The first light emitting element includes a first anode and a first cathode. The second light emitting element is stacked on the first light emitting element and includes a second anode and a second cathode, wherein the second cathode is electrically connected to the first anode. An operation method of the light emitting device structure is also provided.

Abstract: A power electronics device comprises a power electronics carrier includes a non-corrosive metal substrate and a region of electrical isolation material that forms a direct interface with the metal substrate, and a first semiconductor die mounted on the region of electrical isolation material, and a coefficient of thermal expansion of the region of electrical isolation material substantially matches a coefficient of thermal expansion of metal from the metal substrate at the direct interface.

Abstract: A light emitting device including a first semiconductor stacked structure configured to emit multi-color light, and a red light source configured to emit red light, in which the first semiconductor stacked structure includes a first conductivity-type nitride semiconductor layer, an active layer disposed on the first conductivity-type nitride semiconductor layer, and a second conductivity-type nitride semiconductor layer disposed on the active layer, the active layer has a multi-quantum well structure including a plurality of barrier layers and a plurality of well layers stacked one over another, and the active layer is configured to emit multi-color light.

Abstract: A storage device includes a substrate, a storage unit array, and word lines extending in the first direction. The storage unit array includes storage units arranged along a first direction and a second direction. Each storage unit includes: an active region extending in a third direction and including a vertical stack of first source/drain, channel and second source/drain layers, and a gate stack between the first and second source/drain layers in a vertical direction and sandwiching the channel layer from at least two opposite sides. First source/drain layers of each column are continuous to form a bit line extending in the second direction in a zigzag shape. Each word line extends in the first direction to intersect the active regions of a respective row, and is electrically connected to the gate stack of each storage unit on two opposite sides of the channel layer.

Abstract: A die bonding apparatus includes a push-up unit, a head having a collet that sucks a die, and a control device. The control device is configured to suck a dicing tape using a dome plate; land the collet onto the die using the head; suck the die using the collet; lift plural blocks from the dome plate; stop the outermost block disposed on the outermost side among the plural blocks from lifting at a height where the die is peeled off from the dicing tape; and lift blocks other than the outermost block among the plural blocks higher than the outermost block to a predefined height.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes: forming a transistor region in a substrate; forming a gate dielectric layer over the transistor region; forming a diffusion-blocking layer over the gate dielectric layer; forming a first portion of a work function layer over the diffusion-blocking layer; forming a second portion of the work function layer over the first portion of the work function layer; forming a plurality of barrier elements on or under a top surface of the second portion of the work function layer; and forming a gate electrode over the work function layer, wherein the plurality of barrier elements block oxygen from diffusing into the work function layer during the formation of the gate electrode.

Abstract: A semiconductor device includes parallel active regions on a substrate and extending in a first horizontal direction; gate structures intersecting the active regions, extending in a second horizontal direction, and including first and second gate structures opposing each other in the second horizontal direction; source/drain regions including first and second source/drain regions, on at least one side of the gate structures and on the active regions; a gate separation pattern between the first and second gate structures; a vertical conductive structure in the gate separation pattern; contact plugs including a first contact plug electrically connected to the first source/drain region and the vertical conductive structure, and a second contact plug electrically connected to the second source/drain region and spaced apart from the vertical conductive structure; and a contact separation pattern separating the first and second contact plugs, having a portion contacting an upper surface of the vertical conductive s

Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

Abstract: A method is provided for fabricating a semiconductor wafer having a device side, a back side opposite the device side and an outer periphery edge. Suitably, the method includes: forming a top conducting layer on the device side of the semiconductor wafer; forming a passivation layer over the top conducting layer, the passivation layer being formed so as not to extend to the outer periphery edge of the semiconductor wafer; and forming a protective layer over the passivation layer, the protective layer being spin coated over the passivation layer so as to have a smooth top surface at least in a region proximate to the outer periphery edge of the semiconductor wafer.