Patents Examined by Brian Turner
  • Patent number: 10418240
    Abstract: A nitride semiconductor structure includes a substrate, a nitride semiconductor layer, and a buffer stack layer between the substrate and the nitride semiconductor layer. The buffer stack layer includes a plurality of metal nitride multilayers repeatedly stacked, wherein each of the metal nitride multilayers consists of a first, a second, and a third metal nitride thin films in sequence, or consists of the first, the third, the second, and the third metal nitride thin films in sequence. The aluminum concentration of the first metal nitride thin film is higher than that of the third metal nitride thin film, and the aluminum concentration of the third metal nitride thin film is higher than that of the second metal nitride thin film.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: September 17, 2019
    Assignee: ELITE ADVANCED LASER CORPORATION
    Inventors: Kun-Chuan Lin, Jin-Hsiang Liu, Yu-Lin Hsiao
  • Patent number: 10403814
    Abstract: A method of cleaning a substrate processing apparatus that etches a film including a metal, the method include a first cleaning step of providing a gas containing a hydrogen-containing gas, and removing a carbon-containing deposition by plasma generated from the gas containing the hydrogen-containing gas; a second cleaning step of, after the first cleaning step, providing an inert gas, and removing a metal-containing deposition by plasma generated from the inert gas; and a third cleaning step of, after the second cleaning step, providing a gas containing a fluorine-containing gas and an oxygen-containing gas, and removing a silicon-containing deposition by plasma generated from the gas containing the fluorine-containing gas and the oxygen-containing gas.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: September 3, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Takuya Kubo, Song yun Kang, Keiichi Shimoda, Tetsuya Ohishi
  • Patent number: 10396176
    Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Scott B. Clendenning, Szuya S. Liao, Florian Gstrein, Rami Hourani, Patricio E. Romero, Grant M. Kloster, Martin M. Mitan
  • Patent number: 10373907
    Abstract: Conductive structures and method of manufacture thereof are disclosed. A barrier layer can line the first recess of a substrate. A first seed layer can be formed on the barrier layer and line a bottom of the first recess and partially line sidewalls of the recess. A first conductive material can partially fill the first recess to form a second recess. The top surface of the first conductive material can coincide with a vertical extent of the first seed layer and have a depression formed therein. A second seed layer can be formed on the barrier layer and line the second recess. A second conductive material can fill the second recess.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: August 6, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pin-Wen Chen, Chih-Wei Chang
  • Patent number: 10365528
    Abstract: The present disclosure relates to an array substrate, a method of manufacturing the same, a display panel and a display device. The array substrate includes: a plurality of pixel units, the plurality of pixel units being arranged in rows and columns and each row of the pixel units comprising a first sub-pixel row, a second sub-pixel row and a third sub-pixel row being adjacent successively; and a plurality of gate lines, each of the gate lines being configured to drive one sub-pixel row, and gate lines for driving the first sub-pixel row and the second sub-pixel row in a same pixel unit being located between the first sub-pixel row and the second sub-pixel row in the pixel unit.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: July 30, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Yoon-Sung Um
  • Patent number: 10359526
    Abstract: Amplitude-versus-angle analysis for quantitative interpretation can include creation of a plurality of angle gathers from imaging a subsurface location with multiples in a near-offset range and imaging primaries outside the near-offset range and application of an amplitude-versus-angle analysis to the plurality of angle gathers to produce a quantitative interpretation pertaining to the subsurface location.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: July 23, 2019
    Assignee: PGS Geophysical AS
    Inventors: Grunde Rønholt, Nizar Chemingui, Alejandro Antonio Valenciano Mavilio, Shaoping Lu
  • Patent number: 10359542
    Abstract: Techniques to generate dynamically calibrated geo-models green fields are described. A geo-model representing a field on which wells are drilled in a hydrocarbon-bearing formation adjusted to generate multiple adjusted geo-models. Each adjusted geo-model represents a variant of the numerical geo-model. Using each adjusted geo-model, multiple simulated rates of change of bottomhole pressures over time in a well drilled in the hydrocarbon-bearing formation are determined. A measured rate of change of bottomhole pressures over time in the well is compared with the multiple simulated rates of change of bottomhole pressures over time in the well. Based on a result of the comparing, the adjusted geo-model that yielded simulated rates of change of bottomhole pressures that best matched the measured rate of change of bottomhole pressure is identified.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: July 23, 2019
    Assignee: Saudi Arabian Oil Company
    Inventors: Babatope Kayode, Faisal Thawad
  • Patent number: 10361112
    Abstract: The present disclosure describes a method of forming a dielectric layer or a dielectric stack on a photoresist layer while minimizing or avoiding damage to the photoresist. In addition, the dielectric layer or dielectric stack can till high-aspect ratio openings and can be removed with etching. The dielectric layer or dielectric stack can be deposited with a conformal, low-temperature chemical vapor deposition process or a conformal, low-temperature atomic layer deposition process that utilizes a number of precursors and plasmas or reactant gases.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Lin Tsai, Shing-Chyang Pan, Sung-En Lin, Tze-Liang Lee, Jung-Hau Shiu, Jen Hung Wang
  • Patent number: 10354922
    Abstract: Semiconductor devices and methods of forming the same include forming a wet-strippable hardmask over semiconductor fins. The wet-strippable hardmask is anisotropically etched away in a first device region. At least one semiconductor fin is doped in the first device region. The wet-strippable hardmask is isotropically etched away in a second device region. Semiconductor devices are formed from the fins in the first and second device regions.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: July 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekmini Anuja De Silva, Indira Seshadri, Romain Lallement, Nelson Felix
  • Patent number: 10353099
    Abstract: A method and system of processing seismic data is presented. The method may include, for each of a plurality of seismic traces, generating a respective intermediate set of reflectivity coefficients and a partial deconvolution of an estimated wavelet from the respective seismic trace. The method may also include decomposing a model into a plurality of orthogonal components, and projecting each of a plurality of eigenvectors corresponding to one of the orthogonal components onto intermediate reflectivity coefficients corresponding with all of the plurality of seismic traces at each of a plurality of times to generate a plurality of eigen-coefficients associated with each of the plurality of times. The eigen-coefficients may be used to generate a plurality of basis coefficients, which may then be used to generate a respective updated set of reflectivity coefficients for each of the seismic traces.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: July 16, 2019
    Assignee: ION Geophysical Corporation
    Inventor: Douglas Spencer Sassen
  • Patent number: 10347642
    Abstract: A manufacturing method of a semiconductor memory device is provided in the present invention. A cleaning treatment to a storage node contact on a semiconductor substrate is performed, and a metal silicide layer is formed after the cleaning treatment. A gate contact opening penetrating a capping layer of a transistor on the semiconductor substrate is formed after the step of forming the metal silicide layer for exposing a gate structure of the transistor. By the manufacturing method of the semiconductor memory device in the present invention, the gate structure of the transistor may be kept from being influenced and/or damaged by the cleaning treatment of the storage node contact, and the electrical performance of the transistor may be ensured accordingly.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: July 9, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Chien-Ting Ho, Shih-Fang Tzou, Fu-Che Lee
  • Patent number: 10345398
    Abstract: Systems and methods are provided for analyzing magnetic hysteresis. A reversible component associated with an applied magnetic field is determined for establishing a series-distributed model. One or more hysteresis loops are generated for analyzing magnetic hysteresis of a magnetic material.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: July 9, 2019
    Assignee: ANSYS, Inc.
    Inventors: Ping Zhou, Dingsheng Lin
  • Patent number: 10340458
    Abstract: Perovskite hybrid solar cells utilize a bulk heterojunction (BHJ) active layer that is formed as a composite of an organometal halide perovskite and a water soluble fullerene, such as A10C60. In alternative embodiments, the BHJ active layer may be formed as a composite of an organometal halide perovskite material and a fullerene, such as PC61BM. Thus, the fullerene acts as an electron extraction acceptor within the BHJ, allowing such solar cells to more efficiently transport the electrons from the fullerene/perovskite interface to a fullerene-based electron transport layer (ETL). As a result, increased fill factor (FF), as well as improvements in the short-circuit current density (JSC) and power conversion efficiency (PCE) are achieved by the solar cells.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: July 2, 2019
    Assignee: The University of Akron
    Inventors: Xiong Gong, Chang Liu, Kai Wang
  • Patent number: 10330809
    Abstract: A method and apparatus for noise attenuation. The method includes receiving seismic data associated with at least two vintages (di, dj) collected for a same subsurface, wherein the first and second vintages (di, dj) are taken at different times; calculating a set of filters (fi, fj) that minimizes an energy function (E), wherein the energy function (E) includes a term representing a 4D difference between the first and second vintages (di, dj); calculating primaries (pi, pj) corresponding to the first and second vintages (di, dj) based on the set of (fi, fj); and calculating a 4D difference (?ij) based on the primaries (pi, pj). The 4D difference (?ij) is minimized.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: June 25, 2019
    Assignee: CGG SERVICES SAS
    Inventors: Henning Hoeber, Adel Khalil, Erik Hicks
  • Patent number: 10332900
    Abstract: A vertical memory device includes a gate structure on a peripheral circuit region of a substrate, the substrate including a cell region and the peripheral circuit region, and the gate structure including a first gate electrode, second, third, and fourth gate electrodes sequentially disposed at a plurality of levels, respectively, on the cell region of the substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a first epitaxial layer extending through the second gate electrode on the cell region of the substrate, a channel extending through the third and fourth gate electrodes in the vertical direction on the first epitaxial layer, and a second epitaxial layer on a portion of the peripheral circuit region of the substrate adjacent the gate structure.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su-Ok Yun, Jang-Gn Yun, Joon-Sung Lim, Sung-Min Hwang
  • Patent number: 10333048
    Abstract: In this disclosure, example networks of coupled superconducting nanowires hosting MZMs are disclosed that can be used to realize a more powerful type of non-Abelian defect: a genon in an IsingĂ—Ising topological state. The braiding of such genons provides the missing topological single-qubit ?/8 phase gate. Combined with joint fermion parity measurements of MZMs, these operations provide a way to realize universal TQC.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: June 25, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Maissam Barkeshli, Jay Deep Sau
  • Patent number: 10325004
    Abstract: Optimization of optical parametric models for structural analysis using optical critical dimension metrology is described. A method includes determining a first optical model fit for a parameter of a structure. The first optical model fit is based on a domain of quantities for a first model of the structure. A first near optical field response is determined for a first quantity of the domain of quantities and a second near optical field response is determined for a second, different quantity of the domain of quantities. The first and second near optical field responses are compared to locate a common region of high optical field intensity for the parameter of the structure. The first model of the structure is modified to provide a second, different model of the structure. A second, different optical model fit is determined for the parameter of the structure based on the second model of the structure.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: June 18, 2019
    Assignee: KLA-TENCOR CORPORATION
    Inventors: Thaddeus G. Dziura, Yung-Ho Chuang, Bin-Ming Benjamin Tsai, Xuefeng Liu, John J. Hench
  • Patent number: 10325944
    Abstract: The present inventive concept relates to a display device and a manufacturing method thereof. A display device according to an exemplary embodiment of the present inventive concept includes: a substrate; a first gate conductor provided on the substrate; and a gate insulator provided on the first gate conductors, wherein edges of the first gate conductor are recessed from edges of the first gate insulator, and the edges of the first gate insulator are respectively parallel with the edges of the first gate conductor.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: June 18, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young Jae Jeon, Jae-Hyun Park, Sang Ju Lee, Jae Ho Choi, Hye Won Hyeon
  • Patent number: 10326031
    Abstract: Methods of patterning an amorphous semiconductor layer according to a predetermined pattern via laser ablation with a pulsed laser having a laser wavelength are disclosed. In one aspect, a method may include providing the amorphous semiconductor layer on a substrate, providing a distributed Bragg reflector on the amorphous semiconductor layer, wherein the distributed Bragg reflector is reflective at the laser wavelength, providing an absorbing layer on the distributed Bragg reflector, wherein the absorbing layer is absorptive at the laser wavelength, patterning the absorbing layer by laser ablation, in accordance with the predetermined pattern, patterning the distributed Bragg reflector by performing an etching step using the patterned absorbing layer as an etch mask, and etching the amorphous semiconductor layer using the patterned distributed Bragg reflector as an etch mask.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: June 18, 2019
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Menglei Xu, Miha Filipic, Twan Bearda
  • Patent number: 10325970
    Abstract: A display device including a first pixel electrode and a second pixel electrode disposed adjacent to each other on a substrate; a pixel defining layer including a first opening corresponding to the first pixel electrode, a second opening corresponding to the second pixel electrode, and a first convex portion arranged adjacent to the first opening; a first intermediate layer arranged on the first pixel electrode to correspond to the first opening and including a first emission layer; and a first conductive inorganic layer arranged on the first intermediate layer to correspond to the first opening. At least one end of the first conductive inorganic layer extends beyond an end of the first intermediate layer and is disposed on the pixel defining layer between the first opening and the second opening.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: June 18, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyunsung Bang, Arong Kim, Jungsun Park, Duckjung Lee, Jiyoung Choung