Abstract: The present invention provides an array substrate and a manufacturing method thereof. The manufacturing method of the array substrate adopts a multi-stage mask to expose and develop, so that a thickness of a remaining photoresist layer in a channel region corresponding to a display region is same as a thickness of a remaining photoresist layer in a channel region corresponding to a GOA region. Therefore, the two channel regions can be completely etched to prevent short-circuiting, and make up for defects of different action efficiency of developers caused by different densities of thin film transistors in the display region and the GOA region.

Abstract: The present disclosure provides a method for preparing an interlayer insulating layer and a method for manufacturing a thin film transistor, and a thin film transistor, belongs to the field of display technology, and can solve the problem of poor resistance to breakdown of the interlayer insulating layer in the related art. The method for preparing an interlayer insulating layer includes the following steps: forming a silicon oxide layer with a first reaction gas and forming a silicon nitride layer with a second reaction gas such that hydrogen content in the silicon nitride layer is less than or equal to hydrogen content in the silicon oxide layer.

Abstract: Methods for improving profiles of channel regions in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, the semiconductor fin including germanium, a germanium concentration of a first portion of the semiconductor fin being greater than a germanium concentration of a second portion of the semiconductor fin, a first distance between the first portion and a major surface of the semiconductor substrate being less than a second distance between the second portion and the major surface of the semiconductor substrate; and trimming the semiconductor fin, the first portion of the semiconductor fin being trimmed at a greater rate than the second portion of the semiconductor fin.

Abstract: The present disclosure relates to a back grinding tape including a polymer resin layer including a urethane (meth)acrylate resin containing 10 to 40 wt % of a repeating unit derived from a (meth)acrylate monomer or oligomer having a glass transition temperature of 0° C. or higher, wherein the polymer resin layer has a glass transition temperature of ?30° C. to 0° C. The present disclosure also relates to a method of grinding a wafer using the back grinding tape.

Abstract: A semiconductor device according to the present disclosure includes a vertical stack of channel members, a gate structure over and around the vertical stack of channel members, and a first source/drain feature and a second source/drain feature. Each of the vertical stack of channel members extends along a first direction between the first source/drain feature and the second source/drain feature. Each of the vertical stack of channel members is spaced apart from the first source/drain feature by a silicide feature.

Abstract: A semiconductor device, including a silicon on insulator (SOI) substrate is disclosed. The device may include gate structures formed on the SOI substrate and being spaced apart from each other in a horizontal direction, and a plurality of channels spaced apart from each other in a vertical direction. Each of the channels may extend through each of the gate structures in the horizontal direction. The device may include a seed layer and a source/drain region. The source/drain region may be connected to the channels, and each sidewall of the source/drain region in the horizontal direction may have a concave-convex shape. The device may include a protruding portion of the source/drain region formed between the gate structures that protrudes in the horizontal direction compared to a non-protruding portion of the source/drain region formed between the channels.

Abstract: A light emitting diode (LED) array is formed by bonding an LED substrate to a backplane substrate via fitted nanotube interconnects. The backplane substrate may include circuits for driving the LED array. The LED substrate may be a chip or wafer, and may include one or more LED devices. The LED substrate is positioned above the backplane substrate, such that a LED device of the LED substrate is aligned to a corresponding circuit in the backplane substrate. Each of the fitted interconnects electrically connect a LED device to the corresponding circuit of the backplane substrate.

Abstract: Semiconductor structures and fabrication methods thereof are provided. The method includes: providing a substrate, the substate having a first opening; forming a first epitaxial layer in the first opening, the first epitaxial layer having a second opening; forming a stop layer on sidewall surfaces and a bottom surface of the second opening; forming a second epitaxial layer on a top surface of the stop layer; after forming the second epitaxial layer, forming a dielectric layer on the substrate, the dielectric layer having a third opening exposing a surface of the second epitaxial layer; forming a fourth opening in the second epitaxial layer by etching the second epitaxial layer exposed by the third opening until the stop layer is exposed; and forming a contact layer on sidewall surfaces and a bottom surface of the fourth opening by performing a semiconductor metallization process.

Abstract: A method of forming a semiconductor device includes forming a fin of alternating layers of semiconductor nanostructures and sacrificial layers, laterally etching sidewall portions of the sacrificial layers, and depositing additional semiconductor material over the sidewalls of the semiconductor nanostructures and sacrificial layers. Following deposition of a dielectric material over the additional semiconductor material and additional etching, the remaining portions of the semiconductor structures and additional semiconductor material collectively form a hammer shape at each opposing side of the fin. Epitaxial source/drain regions formed on the opposing sides of the fin will contact the heads of the hammer shapes.

Abstract: An integrated device that includes a substrate and a first transistor formed over the substrate. The first transistor includes a first source disposed over the substrate, a first drain disposed over the substrate, a first plurality of channels coupled to the first source and the first drain, where the first plurality of channels is located between the first source and the first drain; at least one inner spacer located between two adjacent channels from the first plurality of channels; at least two voids located between the two adjacent channels; and a first gate surrounding the first plurality of channels.

Abstract: A semiconductor device according to the present disclosure includes a first plurality of gate-all-around (GAA) devices in a first device area and a second plurality of GAA devices in a second device area. Each of the first plurality of GAA devices includes a first vertical stack of channel members extending along a first direction, and a first gate structure over and around the first vertical stack of channel members. Each of the second plurality of GAA devices includes a second vertical stack of channel members extending along a second direction, and a second gate structure over and around the second vertical stack of channel members. Each of the first plurality of GAA devices includes a first channel length and each of the second plurality of GAA devices includes a second channel length smaller than the first channel length.

Abstract: A method of forming a microelectronic device comprises forming openings in an interdeck region and a first deck structure, the first deck structure comprising alternating levels of a first insulative material and a second insulative material, forming a first sacrificial material in the openings, removing a portion of the first sacrificial material from the interdeck region to expose sidewalls of the first insulative material and the second insulative material in the interdeck region, removing a portion of the first insulative material and the second insulative material in the interdeck region to form tapered sidewalls in the interdeck region, removing remaining portions of the first sacrificial material from the openings, and forming at least a second sacrificial material in the openings. Related methods of forming a microelectronic devices and related microelectronic devices are disclosed.

Abstract: Systems and methods of detecting marine seismic survey parameters are provided. A data processing system can obtain seismic data from seismic data acquisition units disposed on a seabed responsive to an acoustic signal propagated from an acoustic source through a water column. The data processing system can determine from the seismic data, a direct arrival time for the acoustic signal at each of the plurality of seismic data acquisition units, and can obtain an estimated depth value of each of the plurality of seismic data acquisition units and an estimated water column transit velocity of the acoustic signal. The data processing system can apply a depth model and a water column transit velocity model to the estimated depth value and to the estimated water column transit velocity determine an updated depth value and an updated water column transit velocity for each of the plurality of seismic data acquisition units.

Abstract: A semiconductor device includes first and second active patterns on first and second active regions of a substrate, respectively, a pair of first source/drain patterns and a first channel pattern therebetween which are in an upper portion of the first active pattern, a pair of second source/drain patterns and a second channel pattern therebetween which are in an upper portion of the second active pattern, and first and second gate electrodes intersecting the first and second channel patterns, respectively. Each of the first and second gate electrodes includes a first metal pattern adjacent to a corresponding one of the first and second channel patterns. The first and second channel patterns include SiGe. A Ge concentration of the second channel pattern is higher than a Ge concentration of the first channel pattern. A thickness of the first metal pattern of the second gate electrode is greater than a thickness of the first metal pattern of the first gate electrode.

Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having at least one first region, at least one second region and at least one third region; forming at least one first fin on the at least one first region, at least one second fin on the at least one second region and at least one third fin on the at least one third region; forming a first opening in the first fin; forming a second opening in the second fin; forming a first epitaxial layer in the first opening and the second opening; forming a third opening in the at least one third fin; removing at least a portion of the first epitaxial layer in the at least one second fin to form a fourth opening; and forming a second epitaxial layer in the third opening and the fourth opening.

Abstract: A method includes forming a fin over a substrate, forming an isolation region adjacent the fin, forming a dummy gate structure over the fin, and recessing the fin adjacent the dummy gate structure to form a first recess using a first etching process. The method also includes performing a plasma clean process on the first recess, the plasma clean process including placing the substrate on a holder disposed in a process chamber, heating the holder to a process temperature between 300° C. and 1000° C., introducing hydrogen gas into a plasma generation chamber connected to the process chamber, igniting a plasma within the plasma generation chamber to form hydrogen radicals, and exposing surfaces of the recess to the hydrogen radicals. The method also includes epitaxially growing a source/drain region in the first recess.

Abstract: A process for handling MEMS wafers includes the steps of: (i) attaching a first carrier substrate to a first side of a MEMS wafer, the first carrier substrate being attached via a first wafer bonding tape and a silicone-free peel tape, the peel tape contacting the first side of the MEMS wafer; (ii) performing wafer processing steps on an opposite second side of the MEMS wafer; (iii) releasing the first carrier substrate from the first side of the MEMS wafer via exposure to an energy source, the energy source selectively releasing the wafer bonding tape from the first side of the MEMS wafer; and (iv) peeling the peel tape away from the first side of the MEMS wafer.

Abstract: A method may include forming a plasma of a fluorine-containing precursor and contacting a semiconductor substrate with plasma effluents. The semiconductor substrate may include a layer of a first silicon-containing material having a first germanium content formed over the semiconductor substrate, and alternating layers of a second silicon-containing material and a third silicon-containing material over the layer of the first silicon-containing material. The third silicon-containing material may have a second germanium content. The method may further include laterally recessing the third silicon-containing material relative to the first and second silicon-containing materials. The method may further include depositing a spacer material adjacent to the third silicon-containing material relative to the first and second silicon-containing materials. The method may also include etching the first silicon-containing material relative to the second silicon-containing material and the spacer material.

Abstract: A semiconductor device of an embodiment includes semiconductor layer including first and second planes, and in order from the first plane's side to the second plane's side, first region of first conductivity type, second region of second conductivity type, third region of second conductivity type having second conductivity type impurity concentration higher than the second region, fourth region of first conductivity type, and fifth region of second conductivity type, and including first and second trench on the first plane's side; first gate electrode in the first trench; first gate insulating film in contact with the fifth semiconductor region; second gate electrode in the second trench; second gate insulating film; a first electrode on the first plane; second electrode on the second plane; first gate electrode pad connected to the first gate electrode; and second gate electrode pad connected to the second gate electrode.

Abstract: A semiconductor device includes a semiconductor die, a semiconductor integrated circuit, an outer crack detection structure, a plurality of inner crack detection structures and a plurality of path selection circuits. The semiconductor die includes a central region and an edge region surrounding the central region. The semiconductor integrated circuit is in a plurality of sub regions of the central region. The outer crack detection structure is in the edge region. The plurality of inner crack detection structures are respectively in the plurality of sub regions, respectively. The path selection circuits are configured to control an electrical connection between the outer crack detection structure and the plurality of inner crack detection structures. A crack in the central region in addition to a crack in the edge region may be detected efficiently through selective electrical connection of the outer crack detection structure and the inner crack detection structures.