Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, vertically oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and horizontally oriented digit lines coupled to the first source/drain regions. In one example, an insulator material is formed on a surface of the first source/drain region and a conductor material formed on the insulator material to form a metal insulator semiconductor (MIS) interface between the horizontally oriented digit lines and the first source/drain regions of the horizontally oriented access devices.

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

Abstract: A semiconductor device includes channel region, first and second two-dimensional metallic contacts, a gate structure, and first and second metal contacts. The channel region includes a two-dimensional semiconductor material. The first two-dimensional metallic contact is disposed at a side of the channel region and includes a two-dimensional metallic material. The second two-dimensional metallic contact is disposed at an opposite side of the channel region and includes the two-dimensional metallic material. The gate structure is disposed on the channel region in between the first and second two-dimensional metallic contacts. The first metal contact is disposed at an opposite side of the first two-dimensional metallic contact with respect to the channel region. The second metal contact is disposed at an opposite side of the second two-dimensional metallic contact with respect to the channel region.

Abstract: A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.

Abstract: Exemplary semiconductor processing systems may include a processing chamber, and may include a remote plasma unit coupled with the processing chamber. Exemplary systems may also include a mixing manifold coupled between the remote plasma unit and the processing chamber. The mixing manifold may be characterized by a first end and a second end opposite the first end, and may be coupled with the processing chamber at the second end. The mixing manifold may define a central channel through the mixing manifold, and may define a port along an exterior of the mixing manifold. The port may be fluidly coupled with a first trench defined within the first end of the mixing manifold. The first trench may be characterized by an inner radius at a first inner sidewall and an outer radius, and the first trench may provide fluid access to the central channel through the first inner sidewall.

Abstract: A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.

Abstract: Method for filling a gap, comprising providing in a deposition chamber a semiconductor substrate having a gap, wherein a bottom of the gap includes a crystalline semiconducting material and wherein a side wall of the gap includes an amorphous material; depositing a silicon precursor in the gap.

Abstract: A method of mounting electronic components on one or more carrier bodies is disclosed. The method comprises providing a support body with at least one first alignment mark, mounting the one or more carrier bodies, each having at least one second alignment mark, on the support body by alignment between the at least one first alignment mark and the at least one second alignment mark. Thereafter, the method includes mounting the plurality of electronic components on a respective one of the one or more carrier bodies by alignment using the at least one second alignment mark.

Abstract: Nanostructure field-effect transistors (NSFETs) including isolation layers formed between epitaxial source/drain regions and semiconductor substrates and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a gate stack over the semiconductor substrate, the gate stack including a gate electrode and a gate dielectric layer; a first epitaxial source/drain region adjacent the gate stack; and a high-k dielectric layer extending between the semiconductor substrate and the first epitaxial source/drain region, the high-k dielectric layer contacting the first epitaxial source/drain region, the gate dielectric layer and the high-k dielectric layer including the same material.

Abstract: A semiconductor substrate measuring apparatus includes a light source to generate irradiation light having a sequence of on/off at a predetermined interval, the light source to provide the irradiation light to a chamber with an internal space for processing a semiconductor substrate using plasma, an optical device between the light source and the chamber, the optical device to split a first measurement light into a first optical path, condensed while the light source is turned on, to split a second measurement light into a second optical path, condensed while the light source is turned off, and to synchronize with the on/off sequence, and a photodetector connected to the first and second optical paths, the photodetector to subtract spectra of first and second measurement lights to detect spectrum of reflected light, and to detect plasma emission light emitted from the plasma based on the spectrum of the second measurement light.

Abstract: An apparatus and a method for forming a 3-D NAND device are disclosed. The method of forming the 3-D NAND device may include forming a plug fill and a void. Advantages gained by the apparatus and method may include a lower cost, a higher throughput, little to no contamination of the device, little to no damage during etching steps, and structural integrity to ensure formation of a proper stack of oxide-nitride bilayers.

Abstract: A method includes providing a first plate including a first surface, a second surface opposite to the first surface, and a first recess indented from the first surface towards the second surface; providing a semiconductor structure including a third surface, a fourth surface opposite to the third surface, and a first sidewall extending between the third surface and the fourth surface; placing the semiconductor structure over the first plate; and disposing a priming material over the third surface of the semiconductor structure, wherein a peripheral portion of the fourth surface of the semiconductor structure is in contact with the first surface of the first plate upon the disposing of the priming material.

Abstract: A method of manufacturing an augmented LED array assembly is described which comprises providing an LED array assembly configured for inclusion in an LED lighting circuit, the LED array assembly comprising a micro-LED array mounted onto a driver integrated circuit, the driver integrated circuit comprising contact pads configured for electrical connections to a circuit board assembly; providing an essentially planar carrier comprising a plurality of contact bridges, each contact bridge extending between a first contact pad and a second contact pad; and mounting the contact bridge carrier to the LED array assembly by forming solder bonds between the first contact pads of the contact bridge carrier and the contact pads of the driver integrated circuit.

Abstract: A semiconductor device is provided. The device includes a first pair and a second pair of source/drain features over a semiconductor substrate. The first pair of source/drain features are p-type doped. The second pair of source/drain features are n-type doped. A first stack of semiconductor layers connect the first pair of source/drain features along a first direction. A second stack of semiconductor layers connect the second pair of source/drain features along a second direction. A first gate is between vertically adjacent layers of the first stack of semiconductor layers. The first gate has a first portion that has a first dimension along the first direction. A second gate is between vertically adjacent layers of the second stack of semiconductor layers. The second gate has a second portion that has a second dimension along the second direction. The second dimension is larger than the first dimension.

Abstract: A wafer processing method includes a pattern region detecting step, an evaluation region setting step, and an evaluation region deploying step. The pattern region detecting step is a step of detecting a period and positional information in which a substantially identical image appears in an imaged image and detecting a pattern region corresponding to one period. The evaluation region setting step is a step of detecting a position in which no metallic pattern is formed on planned dividing lines and setting the position as an evaluation region for evaluating quality of a processed groove. The evaluation region deploying step is a step of recording the position of the evaluation region in the pattern region and deploying the evaluation region at similar positions in different pattern regions.

Abstract: A method of processing a workpiece includes a thermosetting step of heating an area of an expandable sheet around a workpiece to a predetermined temperature or higher and thereafter cooling the heated area of the expandable sheet to make the area harder than before the area has been heated, and after the thermosetting step, an expanding step of expanding the area of the expandable sheet around the workpiece in planar directions to divide the workpiece into chips or to increase distances between the adjacent chips.

Abstract: A wafer processing method for forming a modified layer within a wafer along planned dividing lines forms the modified layer within the wafer, positions a condensing point within the wafer or at a top surface of the wafer and applies a second laser beam while moving the condensing point, images reflected light, and determines a processed state of the wafer on the basis of an imaged image. The second laser beam is formed such that a sectional shape of the second laser beam in a plane perpendicular to a traveling direction of the second laser beam is not axisymmetric with respect to an axis along the planned dividing lines.

Abstract: Some embodiments include an assembly having a memory stack which includes dielectric levels and conductive levels. A select gate structure is over the memory stack. A trench extends through the select gate structure. The trench has a first side and an opposing second side, along a cross-section. The trench splits the select gate structure into a first select gate configuration and a second select gate configuration. A void is within the trench and is laterally between the first and second select gate configurations. Channel material pillars extend through the memory stack. Memory cells are along the channel material pillars.

Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of semiconductor nanosheets, a source/drain (S/D) region, a gate stack, and a liner layer. The substrate includes at least one fin. The plurality of semiconductor nanosheets are stacked on the at least one fin. The S/D region abuts the plurality of semiconductor nanosheets. The gate stack wraps the plurality of semiconductor nanosheets. The liner layer lines a bottom surface and a sidewall of the S/D region and is sandwiched between the S/D region and the gate stack.