Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. A semiconductor device may include isolation areas above a substrate to form a trench between the isolation areas. A first buffer layer is over the substrate, in contact with the substrate, and within the trench. A second buffer layer is within the trench over the first buffer layer, and in contact with the first buffer layer. A channel area is above the first buffer layer, above a portion of the second buffer layer that are below a source area or a drain area, and without being vertically above a portion of the second buffer layer. In addition, the source area or the drain area is above the second buffer layer, in contact with the second buffer layer, and adjacent to the channel area. Other embodiments may be described and/or claimed.

Abstract: A method of fabricating a semiconductor structure includes forming a GaN-based semiconductor layer on a substrate, forming a silicon-containing insulating layer on the GaN-based semiconductor layer, forming a recess in the silicon-containing insulating layer in a first etching step, wherein the first etching step is performed by using a fluorine-containing etchant and applying a first bias power, and enlarging the recess to extend into the GaN-based semiconductor layer in a second etching step, wherein the second etching step is performed by using the same fluorine-containing etchant as the first etching step and applying a second bias power that is greater than the first bias power. In addition, a method of fabricating a high electron mobility transistor is provided.

Abstract: A method includes forming an N well and a P well in a substrate; depositing a first layer having silicon over the N well and the P well; depositing a first dielectric layer over the first layer; forming a resist pattern over the first dielectric layer, the resist pattern providing an opening directly above the N well; etching the first dielectric layer and the first layer through the opening, leaving a first portion of the first layer over the N well; removing the resist pattern; and epitaxially growing a second layer having silicon germanium (SiGe) over the first portion of the first layer. The epitaxially growing the second layer includes steps of (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a SiGe layer over the silicon seed layer, wherein the steps (a), (b), and (c) are performed under about a same temperature.

Abstract: A semiconductor device according to the present disclosure includes a fin structure over a substrate, a vertical stack of silicon nanostructures disposed over the fin structure, an isolation structure disposed around the fin structure, a germanium-containing interfacial layer wrapping around each of the vertical stack of silicon nanostructures, a gate dielectric layer wrapping around the germanium-containing interfacial layer, and a gate electrode layer wrapping around the gate dielectric layer.

Abstract: A device may include a first package and a second package where the first package has a warped shape. First connectors attached to a redistribution structure of the first package include a spacer embedded therein. Second connectors attached to the redistribution structure are fee from the spacer, the spacer of the first connectors keeping a minimum distance between the first package and the second package during attaching the first package to the second package.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an active pattern, a gate electrode extending in a first direction and crossing the active pattern which extends in a second direction, a separation structure crossing the active pattern and extending in the first direction, a first gate dielectric pattern disposed on a side surface of the gate electrode, a second gate dielectric pattern disposed on a side surface of the separation structure, and a gate capping pattern covering a top surface of the gate electrode. A level of a top surface of the separation structure is higher than a level of a top surface of the gate capping pattern.

Abstract: Gate-all-around (GAA) devices and methods of manufacturing such devices are described herein. A method includes forming a multi-layer structure over a substrate and forming a plurality of source/drain regions in the multi-layer structure. Fins are then patterned into the multi-layer structure through adjacent source/drain regions. A wire release process is performed to remove materials of one or more of the layers in the multi-layer stack. The remaining layers of the multi-layer stack form a stack of nanostructures connecting adjacent source/drain regions of the fins.

Abstract: A memory device is provided with a support and several superimposed levels of resistive memory cells formed on the support, each level having one or more rows of one or more resistive memory cell(s), each resistive memory cell having a variable resistance memory element formed by an area of variable resistivity material arranged between a first electrode and a second electrode. The memory element is connected to a source region or drain region of a control transistor, the control transistor being formed in a given semiconductor layer of a stack of semiconductor layers formed on the support and wherein respective channel regions of respective control transistors of resist memory cells are arranged.

Abstract: An apparatus comprises a first conductive structure and at least one transistor in electrical communication with the first conductive structure. The at least one transistor comprises a lower conductive contact coupled to the first conductive structure and a split-body channel on the lower conductive contact. The split-body channel comprises a first semiconductive pillar and a second semiconductive pillar horizontally neighboring the first semiconductive pillar. The at least one transistor also comprises a gate structure horizontally interposed between the first semiconductive pillar and the second semiconductive pillar of the split-body channel and an upper conductive contact vertically overlying the gate structure and coupled to the split-body channel. Portions of the gate structure surround three sides of each of the first semiconductive pillar and the second semiconductive pillar. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.

Abstract: A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion.

Abstract: A semiconductor device includes a plurality of lower electrode structures disposed on a substrate, and a supporter pattern disposed between pairs of lower electrode structures of the plurality of lower electrode structures. The semiconductor device further includes a capacitor dielectric layer disposed on surfaces of each of the plurality of lower electrode structures and the supporter pattern, and an upper electrode disposed on the capacitor dielectric layer. The plurality of lower electrode structures includes a first lower electrode and a second lower electrode disposed on the first lower electrode and having a cylindrical shape. The first lower electrode has a pillar shape. The first lower electrode includes an insulating core. The insulating core is disposed in the first lower electrode. An outer side surface of the first lower electrode and an outer side surface of the second lower electrode are coplanar.

Abstract: Self-aligned gate cutting techniques are disclosed herein that provide dielectric gate isolation fins for isolating gates of multigate devices from one another. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A dielectric gate isolation fin separates the first metal gate from the second metal gate. The dielectric gate isolation fin includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is greater than the first dielectric constant. The first metal gate and the second metal gate physically contact the first channel layer and the second channel layer, respectively, and the dielectric gate isolation fin.

Abstract: Examples of an integrated circuit with a gate structure and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate having a channel region. A gate dielectric is formed on the channel region, and a layer containing a dopant is formed on the gate dielectric. The workpiece is annealed to transfer the dopant to the gate dielectric, and the layer is removed after the annealing. In some such examples, after the layer is removed, a work function layer is formed on the gate dielectric and a fill material is formed on the work function layer to form a gate structure.

Abstract: A method and device for automatic film expansion and a storage medium are provided. The method includes the following. Perform overall stretching on an expanded film. An interval between each two adjacent LED wafers on the expanded film is monitored in real time. When an interval between two adjacent LED wafers on the expanded film is greater than or equal to a preset target interval, stop performing overall stretching, and search the expanded film for a local region where an absolute difference between an interval between two adjacent LED wafers and the preset target interval is greater than a preset error threshold. When the local region exists on the expanded film, perform local stretching on the local region until an absolute difference between an interval between each two adjacent LED wafers in the local region and the preset target interval is less than or equal to the preset error threshold.

Abstract: A method of manufacturing a semiconductor nanowire semiconductor device is described. The method includes forming an amorphous channel material layer on a substrate, patterning the channel material layer to form semiconductor nanowires extending in a lateral direction on the substrate, and forming a cover layer covering an upper of the semiconductor nanowire. The cover layer and the nanowire are patterned to form a trench exposing a side section of an one end of the semiconductor nanowire and a catalyst material layer is formed in contact with a side surface of the semiconductor nanowire, and metal induced crystallization (MIC) by heat treatment is performed to crystallize the semiconductor nanowire in a length direction of the nanowire from the one end of the semiconductor nanowire in contact with the catalyst material.

Abstract: An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.

Abstract: A workpiece processing method includes holding a workpiece unit on a holding table and forming a division start point. The workpiece unit has a workpiece having a front side and a back side, and an additional member formed on the back side of the workpiece. The additional member is different in material from the workpiece. The workpiece unit is held on the holding table with the additional member opposed to the holding table. The division start point is formed by applying a laser beam to the front side of the workpiece with the focal point of the laser beam set inside the workpiece. The laser beam forms a modified layer inside the workpiece and simultaneously forming a division start point inside the additional member due to the leakage of the laser beam from the focal point toward the back side of the workpiece.

Abstract: Exemplary methods of semiconductor processing may include flowing a silicon-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region, and the substrate may be maintained at a temperature below or about 450° C. The methods may include striking a plasma of the silicon-containing precursor. The methods may include forming a layer of amorphous silicon on a semiconductor substrate. The layer of amorphous silicon may be characterized by less than or about 3% hydrogen incorporation.

Abstract: To provide a miniaturized transistor having highly stable electrical characteristics. Furthermore, also in a semiconductor device including the transistor, high performance and high reliability are achieved. The transistor includes, over a substrate, a conductor, an oxide semiconductor, and an insulator. The oxide semiconductor includes a first region and a second region. The resistance of the second region is lower than that of the first region. The entire surface of the first region in the oxide semiconductor is surrounded in all directions by the conductor with the insulator interposed therebetween.