Abstract: A digital/analog converter (30) with a first return-to-zero unit (311) which is connected to a first busbar (321), wherein the first busbar (321) is connected in each case to a first output of several differential units (351, 352, 35n). In this context, the first return-to-zero unit (311) provides at least one clock input which is directly or indirectly connected to a first photodiode, wherein the first photodiode is fed from a pulsed light source (5).

Abstract: There is provided a semiconductor device using low electric power and a small area which can realize highly accurate calibration. The semiconductor device according to the embodiment includes an A/D conversion unit, and a hold signal generating circuit which is coupled to an input side of the A/D conversion unit, and has a hold period not less than two cycles of the A/D conversion unit. The hold signal generating circuit includes: an SC integrator including an input buffer coupled to the input side of the A/D conversion unit, and feedback capacitor coupled to an input and an output of the input buffer; and a logic circuit which compares an output signal of plural bits outputted from the A/D conversion unit with a first and a second threshold values, and outputs a control signal which controls polarity of the SC integrator according to a comparison result.

Abstract: A code converter is provided. The code converter includes a plurality of serial shift registers arranged to convert an input to a thermometer output. The code converter further includes a plurality of clock control circuits each configured to provide a clock to a corresponding one of the shift registers. A method of generating a signal in thermometer code is provided. The method includes enabling a subset of a plurality of shift registers and converting an input to a thermometer output by the plurality of shift registers. Another code converter is further provided. The code converter includes means for converting an input to a thermometer output. The means for converting includes a plurality of shift registers. The code converter further includes means for enabling a subset of the shift registers.

Abstract: Systems, apparatuses, and methods are provided for analog-to-digital converters (ADCs), such as successive-approximation-register (SAR) ADCs and pipelined ADCs that utilize distributed virtual-ground switching (DVS). DVS circuits and systems receive reference signal inputs that are provided to input signal buffers at the input side of the buffers via reference switches. The input signal buffers and corresponding switches are distributed into scaled replicas that each receive an analog input signal via input signal switches during a first operational phase and are connected to top plates of corresponding distributed capacitors. The bottom plates of the capacitors are sampled to provide analog input signal representations.

Abstract: Methods and systems for performing analog-to-digital conversion are described. In one embodiment, a method for performing analog-to-digital conversion involves processing an analog impulse signal to obtain an impulse pattern of the analog impulse signal in a first signal processing path and converting the analog impulse signal into a digital signal based on the impulse pattern in a second signal processing path that is in parallel with the first signal processing path. The impulse pattern of the analog impulse signal includes duty cycle information of the analog impulse signal. Other embodiments are also described.

Abstract: Apparatus and methods are taught for dividing a signal to be processed by a Noise Shaping (Hereafter NS) loop into smaller sections, and applying NS to at least a subset of these smaller sections. The processed signals are then recombined. As noise shaping is performed on smaller sections, the operating speed of each noise shaping loop, and accordingly for the system in general, is faster than if the output signal had been generated by single higher bit NS loop. Embodiments further include a configuration block for configuring the apparatus. For example, the number of sections, the section calculation method, and the NS for each section can each be configurable, and for some embodiments, programmable.

Abstract: Methods and Systems for calibrating a Single Ramp Multiple Slope Analog to Digital Converter (SRMS ADC), the ADC including a counter and a plurality N of charge and discharge elements of different time constant i.e. slope, wherein the relationships between slopes is defined as a function of the shallowest slope SN such that S1=K1·SN, S2=K2·SN, . . . SN-1=KN-1·SN-1 where the K values are integers, and the code count for conversion is C=K1·C1+K2·C2+ . . . KN-1·CN-1+CN where each Ci represents an observed counts per each slope for a conversion, including; sampling for a first calibration pass a voltage with the ADC, discharging the voltage on the steepest slope for a number of counter counts C11, charging and discharging on the remaining slopes up to K2 to KN-1 for a number of counts per slope, Ci1 e.g.

Abstract: Present disclosure describes an improved mechanism for addressing component mismatch in a DAC. The mechanism is based on carefully selecting the first DAC unit of an ordered sequence of DAC units that are switched on to convert a particular digital value to an analog value. The mechanism benefits from recognition that selecting the first DAC based on a value of a band-limited dither signal, where the band of the dither signal is selected to be sufficiently removed from the band of the signal of interest, allows shifting effects of DAC units mismatch away from the signal of interest in a manner that is easy to implement and control. Because dither signal is not added to the signal of interest, but is only used to control which DAC units are turned on, drawbacks of a traditional dithering method can be avoided while benefiting from the use of dither.

Abstract: A method and apparatus for a method of calibrating a transmit digital to analog converter full-scale current. The method comprises generating a tuned reference current and then calibrating the tuned reference current to a selected value in order to produce a predetermined current value. The calibration further comprises dividing a reference voltage input over a resistor string. A band gap current is then generated using the divided reference voltage input. A tuned current output is then produced from a current steering digital to analog converter with the tuned output current stored in a register. The reference current for the transmit DAC is then generated based on the stored tuned output current.

Abstract: The present invention discloses encoding and decoding methods and apparatuses of an Ethernet physical layer, the encoding method includes: determining a to-be-encoded first information group, where the first information group includes m characters, m?2, and m is an integer, where a character attribute of any character is a data character, a boundary character, or a third-type character, and one character occupies one byte; detecting a character attribute of each character in the first information group; if the first information group includes n boundary characters, where n?1, and n is an integer, deleting the n boundary characters, and generating a second information group by using a character, except the n boundary characters, in the first information group, and type information and position information that are of the n boundary characters, where the second information group includes m bytes; and adding header information to the second information group.

Abstract: An efficient analog to digital converter is disclosed. The efficient analog to digital converter includes a coarse analog to digital converter coupled to an input analog signal. The coarse analog to digital converter is configured to provide an approximate digital representation of the input analog signal. The efficient analog to digital converter also includes a fine analog to digital converter coupled to the input analog signal. The output of the coarse analog to digital converter is coupled to the fine analog to digital converter. The fine analog to digital converter is configured to set input range of the fine analog to digital converter as a function of the output of the coarse analog to digital converter.

Abstract: In an ultra-wideband communication system, a 1-trit ternary analog-to-digital converter (“ADC”) having dynamic threshold adaption and providing an output in ternary form [+1, 0, ?1]. The ternary ADC includes a pair of 1-bit binary ADCs, one being configured in a non-inverting form, and one being configured in an inverting form. Each binary ADC includes an feedback network mechanism, thereby allowing for simultaneous and independent adaptation of the pair of thresholds, compensating for the effects of any DC offset that may be present. The use of a trit-based ternary encoding scheme improves system entropy.

Abstract: Generally, this disclosure describes an apparatus, systems and methods for analog to digital conversion with improved spurious free dynamic range.

Abstract: The silicon real estate required for the semiconductor fabrication of a calibrated capacitor-based successive approximation register (SAR) analog-to-digital converter (ADC) (100) is substantially reduced by using a number of shared capacitors (SC1-SCs?1) which are used as calibration capacitors when operating in a calibration mode and as bit capacitors when operating in a normal mode.

Abstract: Functionalized fullerenes are used in a method of combating fungal growth on surfaces and treating fungal diseases of patients. Surfaces that can be treated by the materials comprising an effective amount of functionalized fullerenes include those of fruits, vegetables, harvested grains, plants, or plant seeds. The method of combating fungal growth on a surface can be augmented but is not dependent on irradiation of the surface by light. Functional fullerenes are employed in various dosage forms such as topical, ingestible or administration.

Abstract: A digital-analog converter (DAC) comprises a receiving circuit configured to receive an input bit stream and generate a first bit signal stream of the input bit stream, a first delay circuit coupled to the receiving circuit to receive the first bit signal stream and to generate a second bit signal stream representing a delayed version of the first bit signal stream. The DAC also comprises a first current generation circuit to receive the first bit signal stream, the first current generation circuit configured to provide first current, corresponding to the first bit signal stream, to a first output. The DAC further comprises a second current generation circuit to receive the second bit signal stream and to provide second current to the first output responsive to receiving the second bit signal stream, a waveform of the second current inverted and scaled relative to a waveform of the first current.

Abstract: A binary arithmetic coding scheme is extended by a functionality to encode and decode non-negative integer values with particular low computational complexity.

Abstract: A circuit having an input comparator configured to receive an input voltage and output an input dependent polarity signal along with an input dependent timing signal; a reference comparator configured to receive a reference voltage and output a reference dependent polarity signal along with a reference dependent timing signal; a time-to-digital converter configured to receive the input dependent timing signal and the reference dependent timing signal and output a digital signal; and an output encoder configured to receive the input dependent polarity signal and the digital signal and output an output data representing an analog-to-digital conversion of the input voltage.

Abstract: A system and method for low-power digital signal processing, for example, comprising adjusting a digital representation of an input signal.

Abstract: Disclosed is an integrated circuit including a memory device including a first portion and a second portion. The first portion is a first type of content addressable memory (CAM) with a first set of cells and the second portion is a second type of CAM with a second set of cells. The first set of cells is smaller than the second set of cells. The integrated circuit further includes a decompression accelerator coupled to the memory device, the decompression accelerator to generate a plurality of length codes. Each of the plurality of length codes include at least one bit. The plurality of length codes are generated using a symbol received from an encoded data stream that includes a plurality of symbols. The decompression accelerator further to store the plurality of length codes in the first portion of the memory device in an order according to their respective number of bits.