Abstract: An analog-digital converter with successive approximation includes a capacitor array for being loaded by applying a given input signal potential and for providing a sampling potential, wherein capacitors of the capacitor array are serially coupled with switches. A decision latch is included for evaluating the sampling potential in a number of consecutive decision steps. The analog-digital converter also includes a logic unit for selectively changing the sampling potential by selectively switching switches associated to the capacitors of the capacitor array for each decision step based on an evaluation result of a previous decision step, wherein the switches are respectively coupled with a calibration switch.

Abstract: The semiconductor integrated circuit device includes a T-type switch circuit TS[k] that is between an input port A[k] and an input terminal Ain of an analog/digital conversion circuit and that includes first, second, and third PMOS transistors MP1, MP2, and MPc, and first, second, and third NMOS transistors MN1, MN2, and MNc; and a fourth PMOS transistor MPu for pre-charging the input terminal Ain to a power supply voltage VCCA. In detecting the presence or absence of a disconnection from the input port A[k] to a signal input terminal Vint[k], first, the input terminal Ain is pre-charged to the power supply voltage VCCA via the fourth PMOS transistor MPu and also the second NMOS transistor MN2 and the second PMOS transistor MP2 are turned on, and the first NMOS transistor MN1, the first PMOS transistor MP1, the third PMOS transistor MPc, and third the NMOS transistor MNc are turned off.

Abstract: A communication device including a ground element and an antenna element is provided. The antenna element includes a metal element. The metal element is disposed adjacent to an edge of the ground element. The metal element has a first connection point and a second connection point. A feeding point of the antenna element is coupled through an inductive element to the first connection point. A first feeding path is formed from the feeding point through the inductive element to the first connection point. The feeding point of the antenna element is further coupled through a capacitive element to the second connection point. A second feeding path is formed from the feeding point through the capacitive element to the second connection point. The feeding point of the antenna element is further coupled through a matching circuit to a signal source.

Abstract: An air-to-ground network communication device may include a conductive groundplane and an antenna element. The conductive groundplane may be disposed to be substantially parallel to a surface of the earth. The antenna element may extend substantially perpendicularly away from the groundplane and may have an effective length between about 1? to about 1.5?. The antenna element may be disposed at a distance of about 0.5? to about 1? from the groundplane.

Abstract: A frequency scanning traveling wave antenna array is presented for Y-band application. This antenna is a fast wave leaky structure based on rectangular waveguides in which slots cut on the broad wall of the waveguide serve as radiating elements. A series of aperture-coupled patch arrays are fed by these slots. This antenna offers 2° and 30° beam widths in azimuth and elevation direction, respectively, and is capable of ±25° beam scanning with frequency around the broadside direction. The waveguide can be fed through a membrane-supported cavity-backed CPW which is the output of a frequency multiplier providing 230˜245 GHz FMCW signal. This structure can be planar and compatible with micromachining application and can be fabricated using DRIE of silicon.

Abstract: A SAR ADC is provided. A DAC provides an intermediate analog signal according to an analog input signal, a most significant bit capacitance and a plurality of significant bit capacitances smaller than the most significant bit capacitance. A first switched capacitor array selectively provides the most significant bit capacitance or the significant bit capacitances according to a select signal. Sum of the significant bit capacitances is equal to the most significant bit capacitance. The second switched capacitor array provides the significant bit capacitances when the first switched capacitor array provides the most significant bit capacitance, and provides the most significant bit capacitance when the first switched capacitor array provides the significant bit capacitances. A comparator provides a comparison result according to the intermediate analog signal. A SAR logic provides an digital output signal according to the comparison result.

Abstract: A bandwidth estimator circuit for an analog to digital converter. The bandwidth estimator computes a bandwidth estimate of an analog signal and includes: an amplitude averaging block configured to determine an average change in amplitude of N samples, a delta time block configured to determine a minimum time difference; a peak voltage block configured to determine the maximum magnitude; a peak to root mean square block configured to determine a ratio of a peak voltage to the root mean square of the magnitude; a bandwidth estimator block configured to compute a product of a ratio of the average change in amplitude to the minimum time difference, multiplied by a ratio of the peak voltage to the root mean square, squared, to the peak voltage multiplied by a constant; and a parameter adjustment circuit configured to modify sampler parameters controlling an analog signal sampling rate. Methods are described.

Abstract: Representative implementations of devices and techniques provide analog to digital conversion of an analog input. A multistage modulator using a feed-forward technique can alternately convert integrated samples of the analog input to digital representations. For example, the modulator is arranged to alternately output the digital representations to form a digital representation of the analog input.

Abstract: A compression method is disclosed, which comprises receiving an OFDM data block comprising a plurality of complex valued data samples wherein each in-phase and quadrature sample value is represented by a first number of bits. The method also comprises calculating an average of absolute sample values of the OFDM data block and mapping the average absolute sample value to a standard deviation value. The method further comprises quantizing each of the sample values using quantization thresholds scaled by the standard deviation value to produce quantized in phase and quadrature sample value representations, each comprising a second number of bits, and mapping the standard deviation value and the quantized sample value representations to an OFDM transmission frame. Corresponding de-compression method, compressor, de-compressor and network node are also disclosed.

Abstract: A wearable electronic device includes an active antenna and an attachment component for attaching the wearable electronic device to a wearer. The attachment component includes a floating portion adapted to resonate in the presence of a radio frequency (RF) carrier wave transmitted by the active antenna. The floating portion is positioned relative to the active antenna to achieve a target coupling with the transmitted RF carrier wave.

Abstract: An analog-to-digital converting device includes a converting module for sampling an input voltage according to a plurality of sampling signals, to generate a comparing signal; a control module, for adjusting the plurality of sampling signal according to the comparing signal, to generate a first digital signal corresponding to the input voltage and a plurality of weights; and a calibration module, for adjusting the plurality of sampling signal according to the first digital signal to make the control module generate a second digital signal and for adjusting the plurality of weights according to the first digital signal and the second digital signal; wherein the second digital signal is different from the first digital signal and is corresponding to the plurality of weights.

Abstract: Generally described herein are methods and systems for sample rate conversion of non-integer and integer factors. In one or more embodiments an apparatus can include a sample rate converter that can include an input configured to receive an input signal with a first frequency and an output configured to provide an output signal with a second frequency different from the first frequency. The sample rate converter can include a filter coefficient lookup table and a numerically controlled oscillator configured to provide filter coefficients from the filter coefficient lookup table at a rate that is a function of the first frequency and the second frequency.

Abstract: To compensate for non-linearity of an AD conversion unit and non-linearity of a DA conversion unit in an electronic system including the DA conversion unit and the AD conversion unit, an electronic system includes an A/D conversion unit, a D/A conversion unit, an AD conversion compensation unit, a DA conversion compensation unit, and a calibration unit. During a calibration operation period, the calibration unit sets an operating characteristic of the AD conversion compensation unit and an operating characteristic of the DA conversion compensation unit. The operating characteristic of the AD conversion compensation unit set during the calibration operation period compensates for non-linearity of AD conversion of the A/D conversion unit. The operating characteristic of the DA conversion compensation unit set during the calibration operation period compensates for non-linearity of DA conversion of the D/A conversion unit.

Abstract: An enhanced resolution successive-approximation register (SAR) analog-to-digital converter (ADC) is provided that includes a digital-to-analog converter (DAC), a comparator and enhanced resolution SAR control logic. The DAC includes analog circuitry that is configured to convert an M-bit digital input to an analog output. The comparator includes a plurality of coupling capacitors. The enhanced resolution SAR control logic is configured to generate an M-bit approximation of an input voltage and to store a residue voltage in at least one of the coupling capacitors. The residue voltage represents a difference between the input voltage and the M-bit approximation of the input voltage. The enhanced resolution SAR control logic is further configured to generate an N-bit approximation of the input voltage based on the stored residue voltage, where N>M.

Abstract: An A/D conversion device has an A/D conversion section including A/D conversion units. Each A/D conversion unit has a pulse delay circuit including delay units connected in daisy chain to form a ring delay line. Each delay unit delays a pulse signal by a delay time corresponding to an input voltage. The A/D conversion section counts the number of pulse signals that passed through the delay units during a period counted from a timing when a start signal is switched to an activation level from a non-activation level at a timing when a sampling signal is received. When each two successive timing signals CKi (i=1, 2, . . . and m) have a same specific period. The each two successive timing signals have a different phase shifted by 1/m of the specific period. Each A/D conversion unit receives the timing signal CK1 as the start signal, and the timing signal CKi+1 (CKm+1=CK1) as the sampling signal.

Abstract: According to an embodiment, a power supply noise cancelling circuit includes a generator, a first multiplier, a subtractor and a digital-to-analog converter. The generator generates a sine wave signal. The first multiplier multiplies a digital input signal by a digital signal based on the sine wave signal to generate a first digital product signal. The subtractor subtracts a digital signal based on the first digital product signal from the digital input signal to generate a digital difference signal. The digital-to-analog converter performs a digital-to-analog conversion on the digital difference signal to obtain an analog output signal.

Abstract: A double-integration type A/D converter for performing A/D conversion by integrating an input voltage and a reference voltage is disclosed. The A/D converter includes an integrator configured to integrate the input voltage and the reference voltage; a first switch configured to relay supply of the input voltage to an input terminal of the integrator; a second switch configured to relay supply of the reference voltage to the input terminal; and a control circuit configured to control switching on and off the first switch and the second switch. The control circuit generates a switching signal that switches on and off the first switch and the second switch individually and a switching signal that switches on and off the first switch and the second switch simultaneously. In addition, superimposition of the input voltage and the reference voltage is integrated when the first switch and the second switch are simultaneously switched on.

Abstract: Systems and techniques are disclosed to express sequences of codes, and in particular sequences of ASCII characters, in a lossless compressed format. The techniques may include dividing a universe of expressible codes into smaller subsets, called code sets, such that every code exists within one code set, but no code exists within two code sets. The code sets are then utilized for compression based on the heuristic that it is more likely that a next code in the sequences of codes is in the same code set as a previous code in the sequences of codes, rather than that the next code in sequences of codes being in any other code set (sentence structure).

Abstract: An idle tone dispersion device includes n FDSM (1) to FDSM (n), a phase adjustment unit which relatively adjusts a phase between a measured signal and a reference signal such that a phase of an idle tone is completely different, and generates and supplies n sets of output measured signals and output reference signals to each of the n FDSM (1) to FDSM (n), and an adder which adds output data of the n FDSM (1) to FDSM (n) and outputs a frequency delta-sigma modulation signal.

Abstract: Systems and methods for generating clock phase signals with accurate timing relations are disclosed. For example, four clock signals spaced by 90 degrees can be generating from differential CML clock signals. A CML to CMOS converter converts the differential CML clock signals to differential CMOS clock signals and provides duty cycle correction. Delay cells produce delayed clock signals from the differential CMOS clock signals. The differential CMOS clock signals and the delayed clock signals are logically combined to produce four quarter clock signals having active times of one-quarter clock period. Set-reset latches produce the four clock signals from the quarter clock signals. A calibration module control delays of the delay cells and controls the duty cycle correction of the CML to CMOS converter to adjust the timing relationships of the four clock signals. The four clock signals may be used, for example, in a deserializer.