Abstract: A method for updating a run length encoded (RLE) stream includes: receiving an element having an insertion value to be inserted into the RLE stream at an insertion position, the insertion value having one of a plurality of values, the RLE stream having elements arranged in runs, and each of the elements having one of the values; identifying a run containing the insertion position; determining whether the insertion value is the same as the value of the element at the insertion position; when the insertion value is different from the value of the element at the insertion position: determining whether the insertion position is adjacent to one or more matching runs of the runs, each element of the matching runs having a same value as the insertion value; and extending one of the matching runs when the insertion position is adjacent to only one of the matching runs.

Abstract: A computer system receives information snippets from a mobile device. The information snippets are extracted from a simulcast of a data stream of a radio broadcast received on the mobile device. The system identifies content metadata from the information snippets. The content metadata describes one or more features of the radio broadcast. The system selects a radio station from a radio station repository based on attributes of the radio station. One of the selection criteria is that the attributes of the radio station match at least a portion of the content metadata. The system presents a reference to the radio station to the mobile device as a recommendation.

Abstract: An analog input signal is dithered using a dithering sequence and then partially chopped using a chopping sequence. The dithered and partially chopped signal is then digitized by analog-to-digital converter (ADC) slices operating in alternating fashion, and the resulting digitized signals are adjusted according to the dithering sequence and the chopping sequence to compensate for gain and voltage offset errors of the ADC slices.

Abstract: In one embodiment of the invention, a digital to analog convertor (DAC) is disclosed for converting a digital input signal into an analog output signal. The DAC includes a switch controller coupled to a digital input signal; a bias voltage generator coupled to a first terminal of an analog voltage power supply; and a switched current source array coupled to the switch controller and the bias voltage generator. The bias voltage generator generates a bias voltage. The switch controller generates a plurality of digital enable signals. The switched current source array includes a plurality of hybrid switched current cells coupled to the switch controller and the bias voltage generator. The plurality of hybrid switched current cells are coupled together at an analog output terminal to sum unit currents together, if any, and form the analog output signal in response to the digital input signal.

Abstract: A time to digital converter includes: a first measurement unit measuring a time difference between a start signal and a stop signal as a first time unit by using a first delay line; a second measurement unit measuring a time difference between the stop signal and the start signal delayed by the first delay line as a second time unit by using a second delay line and a third delay line and comparing an output signal of one delay cell included in the second delay line with an output signal of at least two delay cells included in the third delay line; and an output unit outputting a final time difference between the start signal and the stop signal as a digital code on the basis of measurement results of the first measurement unit and the second measurement unit.

Abstract: The present disclosure provides embodiments of an improved current steering switching element for use in a digital to analog (DAC) converter. Typically, each current steering switching element in the DAC converter provides a varying set of currents for converting a digital input signal. Generally, the switches and drivers in the current steering switching elements are scaled down proportionally to the current being provided by the current steering switching element according to a ratio as less and less current is being driven by the switching element in order to overcome timing errors. However, device sizes are limited by the production process. When a switch is not scaled proportionally to the current, settling timing errors are present and affects the performance of the DAC. The improved current steering switching element alleviates this issue of timing errors by replacing the single switch with two complementary current steering switches.

Abstract: An analog to digital conversion system is disclosed which converts an analog signal to a digital representation thereof at a first sampling rate by distributing the analog signal to at least two signal paths, at least one signal path including a limiting mixer to mix the signal with a respective selected square wave and a smoothing (low pass) filter to filter the mixed signal before providing the mixed and filtered signal to a subconverter, the subconverter having a sampling rate less than the first sampling rate, and a digital matrix filter to combine the digital output of each subconverter to form a digital representation of the analog signal as sampled at the first rate.

Abstract: A multiplying digital-to-analog converter (MDAC) with high slew rate and a pipeline Analog-to-digital converter using the same. The first set of capacitors for a first input terminal of the operational amplifier (op-amp) includes active capacitors coupling the first input terminal of the op-amp to a first enhanced reference voltage or a common mode terminal in accordance with first digital bits in an amplifying phase of the MDAC, and includes a feedback capacitor coupling the first input terminal of the op-amp to a first output terminal of the op-amp in the amplifying phase. The first set of capacitors contains M capacitor cells. The feedback capacitor between the first set of capacitors contains at most M/(2n) capacitor cells, where n is a number of effective bits provided by a first analog-to-digital converter generating the first digital bits for the active capacitors.

Abstract: The present invention provides a successive approximation register analog-to-digital converter (SAR ADC), where a high bit capacitor of the SAR ADC is composed of a plurality of sub-capacitors, and these sub-capacitors are calibrated when the SAR ADC is working. Therefore, the working speed of the SAR ADC will not be influenced. In addition, a capacitance of each sub-capacitor is lower than a redundant capacitance of the SAR ADC, therefore, input signals of the SAR ADC are allowed to have full swing.

Abstract: A histogram-based method for testing an electronic converter device, such as an analogue to digital converter, includes steps of defining at least one histogram hyperbin arranged to store hits for at least one subrange of output codes; applying an input test stimulus to an input of the device to test a subrange of output codes matched to the hyperbin; and accumulating the histogram. At least two hyperbins may be provided, each bin being arranged to store hits for at least one subrange of output codes, and the input test stimulus is applied to an input of the device to test a subrange of output codes matched to one of the hyperbins. Both hyperbins may be open while the histogram is being accumulated for any subrange of output codes. The method may further involve varying the input stimulus to test another subrange.

Abstract: A method and apparatus for direct digital synthesis (DDS) of signals using Taylor series expansion is provided. The DDS may include a modified phase-to-amplitude converter that includes read-only-memories (ROMs), registers and, a single size, such as a coarse, intermediate, and fine ROM corresponding to respective higher resolution phase angles. The outputs of the ROMs when combined can form a digital output signal in the form of a Taylor series of a sinusoid function.

Abstract: A capacitance reduction circuit retains a conversion digital code of a previous sampling of an input signal of a delta-sigma modulated ADC and compares a set of least significant data bits and most significant bits of the conversion digital code to a least significant and a most significant boundary codes. When the least significant bits of the conversion digital code are less than or equal to the least significant boundary code or when the most significant bits of the conversion digital code are greater than or equal to the most significant boundary code, the capacitance reduction circuitry generates a capacitance reduction enable/disable code applied to multiple summation-quantization circuits to enable or disable groups of the multiple summation-quantization circuits bits to reduce capacitive loading of the outputs of delta-sigma modulator and an input signal to improve the total harmonic distortion and noise.

Abstract: An arbitrary waveform generator (AWG) comprises a real-time digital signal processor (DSP) configured to process a stream of waveform data based on current values of processing parameters, a DSP memory configured to store information related to the processing parameters, and an update component configured to update in real-time the current values of the processing parameters based on the information stored in the DSP memory.

Abstract: Serializers are provided. The serializer includes a first drive control signal generator and a second drive control signal generator. The first drive control signal generator amplifies a first input data signal in response to a first clock signal and a second clock signal to generate a first pull-up drive control signal and a first pull-down drive control signal. The second drive control signal generator amplifies a second input data signal in response to the second clock signal and a third clock signal to generate a second pull-up drive control signal and a second pull-down drive control signal.

Abstract: A decompression engine may include an input configured to receive an input code comprises one or more bits from a bitstream of encoded data, a symbol decoder coupled with the input, where the symbol decoder is configured to calculate, based on the input code, a plurality of candidate addresses each corresponding to a code group. The symbol decoder may further include a group identifier module coupled with the symbol decoder, wherein the group identifier module is configured to identify one of the plurality of code groups corresponding to the input code, and a multiplexer coupled with the group identifier module, wherein the multiplexer is configured to select as a final address one of the plurality of candidate addresses corresponding to the identified code group.

Abstract: Selectable communication interface configurations for motion sensing devices. In one aspect, a module for a motion sensing device includes a motion processor connected to a device component and a first motion sensor, and a multiplexer having first and second positions. Only one of the multiplexer positions is selectable at a time, where the first position selectively couples the first motion sensor and the device component using a first bus, and the second position selectively couples the first motion sensor and the motion processor using a second bus, wherein communication of information over the second bus does not influence a communication bandwidth of the first bus.

Abstract: A time-to-digital converter includes first and second phase distribution circuits and N time-to-digital conversion circuits. The first and second phase distribution circuits each includes a plurality of frequency dividers connected in a tree structure. The first and second phase distribution circuits each divides a signal received by the frequency dividers of root nodes into N signals. The first and second phase distribution circuits each outputs the N signals each having a different phase. The N time-to-digital conversion circuits each converts a phase difference between an i-th signal (where i is an integer from 0 to N?1) that is output from the first phase distribution circuit and another i-th signal that is output from the second phase distribution circuit into a digital value.

Abstract: The present disclosure is directed dynamic compression/decompression (codec) configuration. In general, a device may include a codec configuration module to determine a configuration for use by the codec based on configuration criteria. The configuration criteria may include, for example, data characteristic information, system condition information and user expectation information. The configuration information may be used to select a codec configuration from one or more available codec configurations. For example, a benchmark module also in the device may determine the available codec configurations. After a codec configuration has been selected, it may be set in the codec. It may also be possible for the codec configuration module to monitor for changes in device operation (e.g., changes in the configuration criteria) and to update the codec configuration based on the monitored changes.

Abstract: Provided is a system and method for synchronization between digital-to-analog converters (DAC) for high speed signal processing. A synchronization method of a multi-DAC apparatus may include: inputting a clock to a multiplexer (MUX) DAC; dividing the clock into a first clock and a second clock; transferring a phase difference between the first clock and the second clock to a D flip-flop; and synchronizing the first clock and the second clock by processing the phase difference.

Abstract: A system and method for decoding quadrature signals includes a quadrature signal generator, a quadrature signal decoder, a key matrix and a driver. The quadrature signal generator generates quadrature signals on rotation. The quadrature signal decoder is configured to convert the quadrature signals into non-overlapping signals. The key matrix is configured to receive the non-overlapping signals. The driver is configured to scan the key matrix to decode the non-overlapping signals to generate an event update corresponding to a direction of rotation of the quadrature signal generator.