Abstract: An A/D converter includes an incremental delta-sigma A/D modulator and a digital operation unit to which a signal from the A/D modulator is input. The A/D modulator includes an analog integrator configured to integrate input signals, a quantizer configured to quantize output signals of the analog integrator, a D/A converter configured to D/A convert an output of the quantizer, and a reset signal output device configured to reset the analog integrator and the digital operation unit. The analog integrator includes plural switched capacitors and a first analog integrator connected to the switched capacitors. The first analog integrator includes an operational amplifier connected to the switched capacitors and a feedback capacitor each connecting an input and an output of the operational amplifier.

Abstract: An analog-to-digital converter (ADC) that comprises a first ADC stage and a second ADC stage. The first ADC stage comprises a successive approximation register (SAR). The first ADC is configured to convert an analog input signal into a first digital signal corresponding to a most-significant-bits (MSB) portion of a digital output signal. The first ADC stage is also configured to generate a residual voltage corresponding to a difference between a voltage value of the analog input signal and the first digital signal. The second ADC stage comprises a plurality of time-to-digital converter (TDC) cells coupled in series. The second ADC is configured to convert the residual voltage into a plurality of second digital signals generated by the TDC cells. The second digital signals correspond to a least-significant-bits (LSB) portion of the digital output signal. The digital output signal is a digital representation of the analog input signal.

Abstract: In one example, a current steering circuit includes an output transistor pair responsive to a first gate bias voltage. The current steering circuit further includes a first switch comprising a first source-coupled transistor pair coupled to the output transistor pair and responsive to a first differential gate voltage, and a second switch comprising a second source-coupled transistor pair coupled to the output transistor pair and responsive to a second differential gate voltage. The current steering circuit further includes a current source configured to source a bias current. The current steering circuit further includes a third switch comprising a third source-coupled transistor pair coupled between the current source and each of the first switch and the second switch, the third source-coupled transistor pair responsive to a third differential gate voltage.

Abstract: Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.

Abstract: In an example, there is disclosed a digital to analog converter (DAC) architecture that in a first aspect provides first and second parallel paths through the DAC so as to allow a separation of a coarse and fine aspect of the DAC transfer function is described. In another aspect a DAC architecture is provided that comprises at an output of the DAC an interpolator arranged to extend the resolution of the overall DAC architecture by interpolating within the voltage range of the DAC stages that precede the interpolator. Such an interpolator can be used with both an amplifier and/or comparator to provide one or more of a buffering of the output and/or a comparison of the DAC output with signals from other circuit elements. Features of the first and second aspects may be used independently of one another.

Abstract: An apparatus may include a scrambler element configured to receive an input signal and generate a scrambled thermometer code-like signal having a plurality of bits based on the input signal and having a plurality of possible quantization values. The scrambler element may generate at least one equivalent code of the scrambled thermometer code-like signal for each possible quantization value. For each of one or more of the possible quantization values, the scrambler element may be configured to generate a plurality of possible equivalent codes of the scrambled thermometer code-like signal. Responsive to the input signal indicating a change in quantization value of the scrambled thermometer code-like signal, the scrambler element may change the scrambled thermometer code-like signal by transitioning the smallest possible number of the plurality of bits of the scrambled thermometer code-like signal to change quantization value of the scrambled thermometer code-like signal in accordance with the input signal.

Abstract: A harmonic time interleave (HTI) system, including a reference signal, a first summing component to produce a summed reference signal, a de-interleave block to receive an input signal and output a plurality of de-interleaved input signals, a plurality of digital-to-analog converters, each digital-to-analog converter configured to receive a corresponding one of a plurality of de-interleaved input signals and to output a corresponding analog signal, a plurality of mixing components, each mixing component configured to receive the summed reference signal and an analog signal from a corresponding of the plurality of digital-to-analog converters, and to output a corresponding mixed signal, and a second summing component configured to receive the mixed signal from each of the corresponding mixing components and to produce a substantially full-bandwidth analog signal representation of the input signal.

Abstract: In one embodiment, an apparatus includes: a first voltage controlled oscillator (VCO) analog-to-digital converter (ADC) unit to receive a first portion of a differential analog signal and convert the first portion of the differential analog signal into a first digital value; a second VCO ADC unit to receive a second portion of the differential analog signal and convert the second portion of the differential analog signal into a second digital value; a combiner to form a combined digital signal from the first and second digital values; a decimation circuit to receive the combined digital signal and filter the combined digital signal into a filtered combined digital signal; and a cancellation circuit to receive the filtered combined digital signal and generate a distortion cancelled digital signal, based at least in part on a coefficient value.

Abstract: A non-transitory computer-readable recording medium stores a compression program that causes a computer to execute a process. The process includes: detecting a matched data that matches a processing target data with a longest length among pieces of data, the pieces of data being extracted from a data sequence that is a compression target; acquiring an appearance frequency of a code corresponding to character data contained in the matched data when a data length of the matched data is smaller than a predetermined length; acquiring an appearance frequency of a code corresponding to the matched data when the data length of the match data is equal to or larger than the predetermined length; and compressing the data sequence using a compression code generated based on the acquired appearance frequency of the code.

Abstract: A continuous-time delta-sigma modulator for analog-to-digital conversion includes a pair of pseudo-differential signal paths including a pair of pseudo-differential signal paths including current-controlled ring oscillators as the load of open-loop common-source amplifiers that are driven by an analog input signal. The signal path produces digital values by sampling the open-loop current-controlled ring oscillators. A calibration circuit measures nonlinear distortion coefficients in a replica of the signal path. A nonlinearity corrector corrects digital values based upon the nonlinear distortion coefficients.

Abstract: An analog to digital converter (ADC) circuit includes an input stage for supplying an input signal to an ADC for conversion to a digital signal and a control unit of the ADC. The ADC circuit further includes an operational parameter setting device configured to receive an operational parameter setting signal indicative of an operating parameter for the input stage from the control unit. The operational parameter setting device is configured to set an operating parameter for the input stage based on the operational parameter setting signal.

Abstract: A digital to time converter is disclosed and includes a code logic and an interpolator. The code logic is configured to receive a first phase signal and a second phase signal and generate a select signal according to the first phase signal and the second phase signal. The interpolator has a bank of inverters. The interpolator is configured to generate an interpolator signal based on the select signal and an input signal.

Abstract: A system includes an interleaved analog-to-digital converter (ADC) comprising a plurality of sub-ADCs, where each of the plurality of sub-ADCs has an adjustable timing. The system includes a data analyzer that analyzes an output of the interleaved ADC, that estimates timing mismatches of the plurality of sub-ADCs, and that corrects the timing mismatches by adjusting the adjustable timing of one or more of the plurality of sub-ADCs based on the estimated timing mismatches.

Abstract: A SAR ADC including a comparator, an input switch unit, a positive conversion capacitor array, a negative conversion capacitor array, and a SAR controller is provided. The input switch unit alternately couples and decouples a differential analog input signal to the comparator. The positive and negative conversion capacitor arrays sample the differential analog input signal during the sampling phase. The SAR controller resets the switches in the capacitor arrays at the end of the sampling phase to change the sampled voltage into a residual signal, generates an intermediate digital code to control the switches during the conversion phase according to an output of the comparator to convert the residual signal to the intermediate digital code, generates the digital code according to the intermediate digital code, and uses an inverted intermediate digital code to control the switches at the end of the conversion phase.

Abstract: A Synchronous Modulation Resonator (SMR) device, the device includes a resonator having coupled to a Vd source and a Vr source, wherein the Vd is DC biased, wherein the Vr is AC, wherein the resonator provides a resonator output in response to Vd and Vr, a Sigma Delta Modulator (SDM) coupled to the resonator and to the Vr source, wherein the SDM provides a signal output in response to the resonator output and to the Vr, and a digital output block coupled to the SDM, wherein the digital output block is configured to provide a digital signal representation of the resonator output, in response to the signal output.

Abstract: Saturation refers to the process of limiting the value of a signal to the maximum or minimum value that can be represented by a given fixed bit width representation of the signal. In fixed bit width implementations of signal processing algorithms, saturation of a signal is an important operation when the output value of a processing step exceeds the number of bits available to represent it. Saturation may be required after each elementary signal processing step. Many signal processing algorithms are often implemented in hardware. Therefore, it is important to have an efficient method that utilizes least amount of hardware to implement the saturation operation. A method and apparatus are disclosed that implement saturation function using reduced hardware requirements and reduced power consumption.

Abstract: Requirements placed on the first integrator of a filter in a continuous-time delta-feedback modulator may be reduced by using circuitry to reduce the speed of a signal provided to the first integrator of the modulator. The reduction in speed applied to the signal received at the first integrator may then be compensated with circuitry elsewhere in the modulator, such that the net effect of the slow down and speed up of signals does not affect the output of the modulator. The sigma-delta modulator may be implemented in converters, such as an analog-to-digital converter (ADC).

Abstract: Determination of digital compensation to compensate for non-linearity of stochastic system configured to sample a phase difference, based on statistical analysis of calibration data generated by the stochastic system in response to a linear phase ramp. The stochastic system may include a set of stochastic sampler circuits to sample a phase difference at periodic events, and calibration data may include a digital value of set of stochastic samples for each of multiple events. The calibration data may include sequences of the digital values in which the digital values increment over a range of the stochastic system (i.e., between saturation states of the stochastic system). Statistical analysis may include histogram analysis to estimate the probability distribution of the calibration data. The stochastic system may be configured as part of a time-to-digital converter, which may be configured within a feedback loop of a digitally controllable phase lock loop.

Abstract: Methods of measuring capacitance error in a successive approximation register (SAR) analog to digital converter (ADC) are described, including a method in which said ADC includes a register and a digital to analog converter (DAC), and the method comprises connecting a first capacitance associated with a first bit of the DAC between a first reference voltage and a second reference voltage, connecting a first set of one or more capacitances associated with one or more other bits of the DAC between the first reference voltage and a third reference voltage, connecting the first capacitance between a first node and the third reference voltage, connecting the first set of one or more capacitances between the first node and the second reference voltage, and measuring a voltage at the first node to determine a representation of a difference between the first capacitance and a total capacitance of the first set of one or more capacitances.

Abstract: A digital-to-time converter includes a first node, a second node configured to receive a reference signal, and a digital-to-analog signal converter configured to couple a passive impedance to the first node. The passive impedance is selected according to the digital code. The digital-to-time converter also includes a first switch configured to selectively couple the first node to a second reference signal in response to the input signal and a comparator configured to generate the output signal based on a first signal on the first node and the reference signal on the second node. The digital-to-time converter may include a second switch configured to selectively couple the first node to a third reference signal in response to a first control signal.