Abstract: A method of filling STI trenches with dielectric with reduced particle formation. A method of depositing unbiased STI oxide on an integrated circuit during STI trench fill that reduces STI defects during STI CMP.

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a laminate on the carrier, wherein the laminate has a built-up portion and a release portion smaller in size than the built-up portion, the release portion covering the bonding pads and the built-up portion being laminated on the release portion and the carrier; forming a plurality of conductive posts in the built-up portion; and removing the release portion and the built-up portion on the release portion such that a cavity is formed in the laminate to expose the bonding pads, the conductive posts being positioned around a periphery of the cavity. Therefore, the present invention has simplified processes.

Abstract: An integrated circuit includes a first replacement gate structure. The first replacement gate structure includes a layer of a first barrier material that is less than 20 ? in thickness and a layer of a p-type workfunction material. The replacement gate structure is less than about 50 nm in width.

Abstract: Methods of manufacturing a magnetic memory device including forming a lower magnetic layer, a tunnel barrier layer, and an upper magnetic layer on a substrate, forming a magnetic tunnel junction (MTJ) pattern by patterning the lower magnetic layer, the tunnel barrier layer, and the upper magnetic layer, forming a first insulating layer exposing an upper surface of the MTJ pattern, forming a polymer pattern on the exposed upper surface of the MTJ pattern, forming a second insulating layer exposing an upper surface of the polymer pattern, removing the polymer pattern to form a cavity in the second insulating layer, the cavity exposing the upper surface of the MTJ pattern, and forming a metal line by filling the cavity with a conductive metal.

Abstract: A process of forming optical sensors includes sealing an imaging portion of each of a plurality of optical sensors on a sensor wafer with a transparent material. The operation of sealing leaves a bonding portion of each of the optical sensors exposed. The process further includes cutting the wafer into a plurality of image sensor dies after sealing the optical sensors such that each image sensor die includes one of the optical sensors sealed with a corresponding portion of the transparent material.

Abstract: A MEMS device is formed by applying a lower polymer film to top surfaces of a common substrate containing a plurality of MEMS devices, and patterning the lower polymer film to form a headspace wall surrounding components of each MEMS device. Subsequently an upper polymer dry film is applied to top surfaces of the headspace walls and patterned to form headspace caps which isolate the components of each MEMS device. Subsequently, the MEMS devices are singulated to provide separate MEMS devices.

Abstract: An antifuse-type one time programming memory cell has following structures. A first doped region, a second doped region, a third doped region and a fourth doped region are formed in a well region. A gate oxide layer covers a surface of the well region. A first gate is formed on the gate oxide layer and spanned over the first doped region and the second doped region. The first gate is connected with a word line. A second gate is formed on the gate oxide layer and spanned over the third doped region and the fourth doped region. The second gate is connected with the word line. A third gate is formed on the gate oxide layer and spanned over the second doped region and the third doped region. The third gate is connected with an antifuse control line.

Abstract: A method of forming image sensor packages may include performing a molding process. Mold material may be formed either on a transparent substrate in between image sensor dies, or on a removable panel in between transparent substrates attached to image sensor dies. Redistribution layers may be formed before or after the molding process. Mold material may be formed after forming redistribution layers so that the mold material covers the redistribution layers. In these cases, holes may be formed in the mold material to expose solder pads on the redistribution layers. Alternatively, redistribution layers may be formed after the molding process and the redistribution layers may extend over the mold material. Image sensor dies may be attached to a glass or notched glass substrate with dam structures. The methods of forming image sensor packages may result in hermetic image sensor packages that prevent exterior materials from reaching the image sensor.

Abstract: A transistor includes a substrate and an electrically conductive gate over the substrate. The gate has a gate length. A source electrode and a drain electrode are over the substrate, and are separated by a gap defining a channel region. The channel region has a channel length that is less than the gate length. A semiconductor layer is in contact with the source electrode and drain electrode. A dielectric stack is in contact with the gate, and has first, second, and third regions. The first region is in contact with the semiconductor layer in the channel region, and has a first thickness. The second region is adjacent to the first region that has the first thickness. The third region is adjacent to the second region, and has a thickness that is greater than the first thickness.

Abstract: Laser assisted bonding for semiconductor die interconnections is disclosed and may, for example, include forming flux on a circuit pattern on a circuit board, placing a semiconductor die on the circuit board where a bump on the semiconductor die contacts the flux, and reflowing the bump by directing a laser beam toward the semiconductor die. The laser beam may volatize the flux and make an electrical connection between the bump and the circuit pattern. A jig plate may be placed on the semiconductor die when the laser beam is directed toward the semiconductor die. Warpage may be reduced during heating or cooling of the semiconductor die by applying pressure to the jig plate. Jig bars may extend outward from the jig plate and may be in contact with the circuit board during the application of pressure to the jig plate. The jig plate may comprise one or more of: silicon, silicon carbide, and glass.

Abstract: This invention discloses a semiconductor power device formed in a semiconductor substrate includes rows of multiple horizontal columns of thin layers of alternate conductivity types in a drift region of the semiconductor substrate where each of the thin layers having a thickness to enable a punch through the thin layers when the semiconductor power device is turned on. In a specific embodiment the thickness of the thin layers satisfying charge balance equation q*ND*WN=q*NA*WP and a punch through condition of WP<2*WD*[ND/(NA+ND)] where ND and WN represent the doping concentration and the thickness of the N type layers 160, while NA and WP represent the doping concentration and thickness of the P type layers; WD represents the depletion width; and q represents an electron charge, which cancel out. This device allows for a near ideal rectangular electric field profile at breakdown voltage with sawtooth like ridges.

Abstract: A semiconductor device and a method for manufacturing the same are provided. A semiconductor device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. A source region and a drain region are disposed on opposite sides of the gate structure on the semiconductor substrate. A lightly-doped drain region is adjacent to a side of the drain region close to the gate structure, and a lightly-doped source region is adjacent to a side of the source region close to the gate structure. An oxidation region is disposed in the lightly-doped drain region. A trench extends from the surface of the semiconductor substrate to the drain region. A source electrode is disposed on the source region, and the drain electrode has a first portion disposed on the drain region and a second portion disposed in the trench.

Abstract: ALD of HfxAlyCz films using hafnium chloride (HfCl4) and Trimethylaluminum (TMA) precursors can be combined with post-deposition anneal processes and ALD liners to control the device characteristics in high-k metal-gate devices. Variation of the HfCl4 pulse time allows for control of the Al % incorporation in the HfxAlyCz film in the range of 10-13%. Combinatorial process tools can be employed for rapid electrical and materials characterization of various materials stacks. The effective work function (EWF) in metal oxide semiconductor capacitor (MOSCAP) devices with the HfxAlyCz work function layer coupled with ALD deposited HfO2 high-k gate dielectric layers was quantified to be mid-gap at ˜4.6 eV. Thus, HfxAlyCz is a promising metal gate work function material allowing for the tuning of device threshold voltages (Vth) for anticipated multi-Vth integrated circuit (IC) devices.

Abstract: An ion implantation method in which an ion beam is scanned in a beam scanning direction and a wafer is mechanically scanned in a direction perpendicular to the beam scanning direction, includes setting a wafer rotation angle with respect to the ion beam so as to be varied, wherein a set angle of the wafer rotation angle is changed in a stepwise manner so as to implant ions into the wafer at each set angle, and wherein a wafer scanning region length is set to be varied, and, at the same time, a beam scanning speed of the ion beam is changed, in ion implantation at each set angle in a plurality of ion implantation operations during one rotation of the wafer, such that the ions are implanted into the wafer and dose amount non-uniformity in a wafer surface in other semiconductor manufacturing processes is corrected.

Abstract: A Light Emitting Diode (LED) component includes a lead frame and an LED that is electrically connected to the lead frame without wire bonds, using a solder layer. The lead frame includes a metal anode pad, a metal cathode pad and a plastic cup. The LED die includes LED die anode and cathode contacts with a solder layer on them. The metal anode pad, metal cathode pad, plastic cup and/or the solder layer are configured to facilitate the direct die attach of the LED die to the lead frame without wire bonds. Related fabrication methods are also described.

Abstract: There is provided a semiconductor light-emitting device including a base layer formed of a first conductivity-type semiconductor material, and a plurality of light-emitting nanostructures disposed on the base layer to be spaced apart from each other, and including first conductivity-type semiconductor cores, active layers, and second conductivity-type semiconductor layers. The first conductivity-type semiconductor cores include rod layers extending upwardly from the base layer, and capping layers disposed on the rod layers. Heights of the rod layers are different in at least a portion of the plurality of light-emitting nanostructures, and heights of the capping layers are different in at least a portion of the plurality of light-emitting nanostructures.

Abstract: Controlled recessing of materials in cavities and resulting devices are disclosed.

Abstract: A method of forming fine patterns for a semiconductor device includes providing a substrate with a first region and a second region, forming a conductive layer on the substrate, the conductive layer including a plate portion covering the first region and first protruding portions extending from the plate portion in a first direction and covering a portion of the second region, forming first mask patterns on the conductive layer, the first mask patterns extending in the first direction and being spaced apart from each other in a second direction crossing the first direction, forming a second mask pattern on the second region to cover the first protruding portions, and patterning the conductive layer using the first and second mask patterns as an etch mask to form conductive patterns. In plan view, each of the first protruding portions is overlapped with a corresponding one of the first mask patterns.

Abstract: A device includes vertically and laterally spaced sensors that sense different physical stimuli. Fabrication of the device entails forming a device structure having a first and second wafer layers with a signal routing layer interposed between them. Active transducer elements of one or more sensors are formed in the first wafer layer and a third wafer layer is attached with the second wafer layer to produce one or more cavities in which the active transducer elements are located. A trench extends through the second wafer and through a portion of the signal routing layer. The trench electrically isolates a region of the second wafer layer surrounded by the trench from a remainder of the second wafer layer. Another active transducer element of another sensor is formed in this region. The transducer element formed in the second wafer layer may be a diaphragm for a pressure sensor of the sensor device.

Abstract: A method of manufacturing a semiconductor device includes providing a first semiconductor substrate having a first main surface and an opposing second main surface, and forming a pattern into the first semiconductor substrate. The pattern includes a plurality of trenches defining a plurality of mesas. Each of the plurality of mesas has sidewalls and a free surface formed by material of the first semiconductor substrate. The method further includes forming a cavity in the first semiconductor substrate such that the pattern is recessed in the cavity, forming an oxide layer in the cavity and on the sidewalls and free surfaces of the plurality of mesas, and etching the oxide layer to remove the oxide layer from the free surfaces of the plurality of mesas and at least a portion of the sidewalls of the plurality of mesas.