Abstract: An eFuse structure of a semiconductor device may include a first metal formed at a first level on a substrate, a second metal formed at a second level between the first level and the substrate, a third metal formed at a third level between the second level and the substrate, a first via connecting the first metal to the second metal, and a second via connecting the second metal to the third metal. The first metal may include a first portion extending in a first direction, a second portion extending in the first direction and being adjacent to the first portion, and a third portion connecting the first portion to the second portion. A first distance between the first portion and the second portion may be greater than a width of the second portion in a second direction perpendicular to the first direction.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a dielectric stack is formed on the substrate, in which the dielectric stack includes a first silicon oxide layer and a first silicon nitride layer. Next, the dielectric stack is patterned, part of the first silicon nitride layer is removed to form two recesses under two ends of the first silicon nitride layer, second silicon oxide layers are formed in the two recesses, a spacer is formed on the second silicon oxide layers, and third silicon oxide layers are formed adjacent to the second silicon oxide layers.

Abstract: In a lateral BJT formed using a BiCMOS process, the collector-to-emitter breakdown voltage (BVCEO) and BJT's gain, are improved by forming a graded collector contact region with lower doping levels toward the base contact.

Abstract: Broadband signal transmissions may be used for object detection and/or ranging. Broadband transmissions may comprise a pseudo-random bit sequence or a bit sequence produced using, a random process. The sequence may be used to modulate transmissions of a given wave type. Various types of waves may be utilized, pressure, light, and radio waves. Waves reflected by objects within the sensing volume may be sampled. The received signal may be convolved with a time-reversed copy of the transmitted random sequence to produce a correlogram. The correlogram may be analyzed to determine range to objects. The analysis may comprise determination of one or more peaks/troughs in the correlogram. Range to an object may be determines based on a time lag of a respective peak.

Abstract: A high power vertical insulated-gate switch is described that includes an active region, containing a cell array, and a surrounding termination region. The termination region is for at least the purpose of controlling a breakdown voltage and does not contain any switching cells. Assuming the anode is the silicon substrate (p-type), it is desirable to have good hole injection efficiency from the substrate in the active region in the device's on-state. Therefore, the substrate should be highly doped (p++) in the active region. It is desirable to have poor hole injection efficiency in the termination region so that there is a minimum concentration of holes in the termination region when the switch is turned off. Various doping techniques are disclosed that cause the substrate to efficiency inject holes into the active region but inefficiently inject holes into the termination region during the on-state.

Abstract: Some embodiments of the present disclosure provide a method of manufacturing a back side illuminated (BSI) image sensor. The method includes receiving a semiconductive substrate; forming a photosensitive element at a front side of the semiconductive substrate; forming a transistor coupled to the photosensitive element; forming a recess at a back side of the semiconductive substrate; forming a first dielectric layer lining to a side portion of the recess and over the back side of the semiconductor substrate; covering a conductive material over the first dielectric layer and filling in the recess; forming a conductive column on top of the recess by patterning the conductive material; and forming a second dielectric layer covering the conductive column and the first dielectric layer.

Abstract: A nanowire transistor is provided that includes a well implant having a local isolation region for insulating a replacement metal gate from a parasitic channel. In addition, the nanowire transistor includes oxidized caps in the extension regions that inhibit parasitic gate-to-source and gate-to-drain capacitances.

Abstract: The present disclosure relates to micro-electromechanical system (MEMS) package that uses polysilicon inter-tier connections to provide for a low parasitic capacitance in MEM device signals, and a method of formation. In some embodiments, the MEMS package has a CMOS substrate with one or more semiconductor devices arranged within a semiconductor body. A MEMS substrate having an ambulatory element is connected to the CMOS substrate by a conductive bonding structure. The conductive bonding structure is arranged on a front-side of the MEMS substrate at a location laterally offset from the ambulatory element. One or more polysilicon vias extend through the conductive MEMS substrate to the bonding structure. The one or more polysilicon vias are configured to electrically couple the MEMS substrate to the CMOS substrate. By connecting the MEMS substrate to the CMOS substrate using the polysilicon vias, the parasitic capacitance and form factor of the MEMS package are reduced.

Abstract: An imaging system includes a pixel array of pixel cells with each one of the pixel cells including a photodiode disposed in a semiconductor material, a global shutter gate transistor, disposed in the semiconductor material and coupled to the photodiode, a storage transistor disposed in the semiconductor material, an optical isolation structure disposed in the semiconductor material to isolate a sidewall of the storage transistor from stray light and stray charge. The optical isolation structure also includes a deep trench isolation structure that is filled with tungsten and a P+ passivation formed over an interior sidewall of the deep trench optical isolation structure. Each one of the pixel cells also include control circuitry coupled to the pixel array to control operation of the pixel array and readout circuitry coupled to the pixel array to readout image data from the plurality of pixels.

Abstract: A method for manufacturing a solar cell is disclosed. The disclosed method includes conductive region formation of forming a first-conduction-type region at one surface of a semiconductor substrate and a second-conduction-type region at another surface of the semiconductor substrate, and electrode formation of forming a first electrode connected to the first-conduction-type region and a second electrode connected to the second-conduction-type region. In the conductive region formation, the first-conduction-type region is formed by forming a dopant layer containing a first-conduction-type dopant over the one surface of the semiconductor substrate, and heat-treating the dopant layer, and the second-conduction-type region is formed by ion-implanting a second-conduction-type dopant into the semiconductor substrate at the another surface of the semiconductor substrate.

Abstract: Embodiments of the invention described herein generally relate to an apparatus and methods for forming high quality buffer layers and Group III-V layers that are used to form a useful semiconductor device, such as a power device, light emitting diode (LED), laser diode (LD) or other useful device. Embodiments of the invention may also include an apparatus and methods for forming high quality buffer layers, Group III-V layers and electrode layers that are used to form a useful semiconductor device. In some embodiments, an apparatus and method includes the use of one or more cluster tools having one or more physical vapor deposition (PVD) chambers that are adapted to deposit a high quality aluminum nitride (AlN) buffer layer that has a high crystalline orientation on a surface of a plurality of substrates at the same time.

Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.

Abstract: A method of manufacturing an ink jet printhead includes: providing a silicon substrate including active ejecting elements; providing a hydraulic structure layer; providing a silicon orifice plate having a plurality of nozzles for ejection of the ink; and assembling the silicon substrate with the hydraulic structure layer and the silicon orifice plate. Providing the silicon orifice plate includes: providing a silicon wafer having a substantially planar extension delimited by a first and a second surfaces; performing a thinning at the second surface so as to remove a central portion having a preset height; and forming in the silicon wafer a plurality of through holes, each defining a respective nozzle for ejection of the ink.

Abstract: A method for fabricating an image sensor array having a first group of photodiodes for detecting light at visible wavelengths a second group of photodiodes for detecting light at infrared or near-infrared wavelengths, the method including forming a germanium-silicon layer for the second group of photodiodes on a first semiconductor donor wafer; defining a first interconnect layer on the germanium-silicon layer; defining integrated circuitry for controlling pixels of the image sensor array on a semiconductor carrier wafer; defining a second interconnect layer on the semiconductor carrier wafer; bonding the first interconnect layer with the second interconnect layer; defining the pixels of an image sensor array on a second semiconductor donor wafer; defining a third interconnect layer on the image sensor array; and bonding the third interconnect layer with the germanium-silicon layer.

Abstract: The present disclosure generally relates to an improved method for forming low resistivity crystalline silicon films for display devices. The processing chamber in which the low resistivity crystalline silicon film is formed is pressurized to a predetermined pressure and a radio frequency power at a predetermined power level is delivered to the processing chamber. In addition, feeding locations of one or more VHF power generator and controlling of each VHF power generator via phase modulation and sweeping allows for plasma uniformity improvements by compensating for the non-uniformity of the thin film patterns produced by the chamber, due to the standing wave effect. Diffuser plate having two curved surfaces helps improve crystallinity uniformity.

Abstract: A packaging structure and a method of forming a packaging structure are provided. The packaging structure, such as an interposer, is formed by optionally bonding two carrier substrates together and simultaneously processing two carrier substrates. The processing includes forming a sacrificial layer over the carrier substrates. Openings are formed in the sacrificial layers and pillars are formed in the openings. Substrates are attached to the sacrificial layer. Redistribution lines may be formed on an opposing side of the substrates and vias may be formed to provide electrical contacts to the pillars. A debond process may be performed to separate the carrier substrates. Integrated circuit dies may be attached to one side of the redistribution lines and the sacrificial layer is removed.

Abstract: A method for fabricating an integrated MEMS-CMOS device. The method can include providing a substrate member having a surface region and forming a CMOS IC layer having at least one CMOS device overlying the surface region. A bottom isolation layer can be formed overlying the CMOS IC layer and a shielding layer and a top isolation layer can be formed overlying a portion of bottom isolation layer. The bottom isolation layer can include an isolation region between the top isolation layer and the shielding layer. A MEMS layer overlying the top isolation layer, the shielding layer, and the bottom isolation layer, and can be etched to form at least one MEMS structure having at least one movable structure and at least one anchored structure.

Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.

Abstract: Semiconductor devices and methods for making the same includes conformally forming a first spacer on a plurality of fins. A second spacer is conformally formed on the first spacer, the second spacer being formed from a different material from the first spacer. The plurality of fins are etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched plurality of fins to fill the fin cavity.

Abstract: A method of forming a via and a wiring structure formed are disclosed. The method may include forming a conductive line in a first dielectric layer; forming a hard mask adjacent to the conductive line after the conductive line forming; forming a second dielectric layer over the hard mask; and forming a via opening to the conductive line in the second dielectric layer. The via opening lands at least partially on the hard mask to self-align the via opening to the conductive line. A via may be formed by filling the via opening with a conductor.